FreeCalypso > hg > tcs211-fcmodem

comparison chipsetsw/drivers/drv_core/spi/spi_drv.h @ 0:509db1a7b7b8

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:509db1a7b7b8
1 /**********************************************************************************/
2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
3 /* */
4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
6 /* product is protected under copyright law and trade secret law as an */
7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
8 /* rights reserved. */
9 /* */
10 /* */
11 /* Filename : spi_drv.h */
12 /* */
13 /* Description : SPI registers and bits definitions. */
14 /* Functions and macros to drive the SPI module. */
15 /* The Serial Port Interface is a bidirectional 3 lines */
16 /* interface dedicated to the transfer of data to and */
17 /* from up to 5 external devices offering a 3 lines */
18 /* serial interface. */
19 /* In this project, it is only used to connect the TI */
20 /* Analog BaseBand (ABB). */
21 /* It is assumed that the ABB is connected as the SPI */
22 /* device 0. */
23 /* */
24 /* This interface is specified to be compatible with */
25 /* the UMA1018M Philips, the FUJITSU MB15F02, the */
26 /* SIEMENS PMB2306T synthesizers and the TI ABB. */
27 /* */
28 /* This serial port is based on a looped shift-register */
29 /* thus allowing both transmit (PISO) and receive (SIPO) */
30 /* modes. */
31 /* */
32 /* */
33 /* Author : Pascal PUEL */
34 /* */
35 /* Version number : 1.28 */
36 /* */
37 /* Date and time : 07/01/03 */
38 /* */
39 /* Previous delta : Rework */
40 /* */
41 /**********************************************************************************/
42
43 #ifndef __SPI_DRV_H__
44 #define __SPI_DRV_H__
45
46 #include "l1sw.cfg"
47 #include "chipset.cfg"
48
49 #include "memif/mem.h"
50 #if (OP_L1_STANDALONE == 0)
51 #include "main/sys_types.h"
52 #else
53 #include "sys_types.h"
54 #endif
55
56 // SPI module registers definition
57 #define SPI_REG_SET1 (MEM_SPI + 0x00)
58 #define SPI_REG_SET2 (MEM_SPI + 0x02)
59 #define SPI_REG_CTRL (MEM_SPI + 0x04)
60 #define SPI_REG_STATUS (MEM_SPI + 0x06)
61 #define SPI_REG_TX_LSB (MEM_SPI + 0x08)
62 #define SPI_REG_TX_MSB (MEM_SPI + 0x0A)
63 #define SPI_REG_RX_LSB (MEM_SPI + 0x0C)
64 #define SPI_REG_RX_MSB (MEM_SPI + 0x0E)
65
66
67 // SPI module bits definition of register SPI_REG_SET1
68 #define SPI_CLK_OFF 0x0000 // default value
69 #define SPI_CLK_ON 0x0001
70 #define SPI_CLOCK_DIV_1 0x0000 // default value
71 #define SPI_CLOCK_DIV_2 0x0002
72 #define SPI_CLOCK_DIV_4 0x0004
73 #define SPI_CLOCK_DIV_8 0x0006
74 #define SPI_CLOCK_DIV_16 0x0008
75 #if (CHIPSET == 12)
76 #define SPI_CLOCK_DIV_32 0x000A
77 #define SPI_CLOCK_DIV_64 0x000C
78 #define SPI_CLOCK_DIV_128 0x000E
79 #endif
80 #define SPI_IT_MASK_0 0x0010 // default value
81 #define SPI_IT_DEMASK_0 0x0000
82 #define SPI_IT_MASK_1 0x0020 // default value
83 #define SPI_IT_DEMASK_1 0x0000
84
85
86 // SPI module bits definition of register SPI_REG_SET2
87 #define SPI_CLK_EDG_FALL 0x0000 // default value for device 0
88 #define SPI_CLK_EDG_RISE 0x0001
89 #define SPI_CLK_EDG_FALL_1 0x0000 // default value for device 1
90 #define SPI_CLK_EDG_RISE_1 0x0002
91 #define SPI_CLK_EDG_FALL_2 0x0000 // default value for device 2
92 #define SPI_CLK_EDG_RISE_2 0x0004
93 #define SPI_CLK_EDG_FALL_3 0x0000 // default value for device 3
94 #define SPI_CLK_EDG_RISE_3 0x0008
95 #define SPI_CLK_EDG_FALL_4 0x0000 // default value for device 4
96 #define SPI_CLK_EDG_RISE_4 0x0010
97 #define SPI_NTSPEN_NEG_LEV 0x0000 // default value for device 0
98 #define SPI_NTSPEN_POS_LEV 0x0020
99 #define SPI_NTSPEN_NEG_LEV_1 0x0000 // default value for device 1
100 #define SPI_NTSPEN_POS_LEV_1 0x0040
101 #define SPI_NTSPEN_NEG_LEV_2 0x0000 // default value for device 2
102 #define SPI_NTSPEN_POS_LEV_2 0x0080
103 #define SPI_NTSPEN_NEG_LEV_3 0x0000 // default value for device 3
104 #define SPI_NTSPEN_POS_LEV_3 0x0100
105 #define SPI_NTSPEN_NEG_LEV_4 0x0000 // default value for device 4
106 #define SPI_NTSPEN_POS_LEV_4 0x0200
107 #define SPI_NTSPEN_LEV_TRIG 0x0000 // default value for device 0
108 #define SPI_NTSPEN_EDG_TRIG 0x0400
109 #define SPI_NTSPEN_LEV_TRIG_1 0x0000 // default value for device 1
110 #define SPI_NTSPEN_EDG_TRIG_1 0x0800
111 #define SPI_NTSPEN_LEV_TRIG_2 0x0000 // default value for device 2
112 #define SPI_NTSPEN_EDG_TRIG_2 0x1000
113 #define SPI_NTSPEN_LEV_TRIG_3 0x0000 // default value for device 3
114 #define SPI_NTSPEN_EDG_TRIG_3 0x2000
115 #define SPI_NTSPEN_LEV_TRIG_4 0x0000 // default value for device 4
116 #define SPI_NTSPEN_EDG_TRIG_4 0x4000
117
118
119 // SPI module bits definition of register SPI_REG_CTRL
120 #define SPI_RDWR_DEACTIV 0x0000 // default value
121 #define SPI_RDWR_ACTIV 0x0001
122 #define SPI_WR_DEACTIV 0x0000 // default value
123 #define SPI_WR_ACTIV 0x0002
124 #define SPI_WNB_0 0x0000 // default value
125 #define SPI_WNB_1 0x0004
126 #define SPI_WNB_2 0x0008
127 #define SPI_WNB_3 0x000c
128 #define SPI_WNB_4 0x0010
129 #define SPI_WNB_5 0x0014
130 #define SPI_WNB_6 0x0018
131 #define SPI_WNB_7 0x001c
132 #define SPI_WNB_8 0x0020
133 #define SPI_WNB_9 0x0024
134 #define SPI_WNB_10 0x0028
135 #define SPI_WNB_11 0x002c
136 #define SPI_WNB_12 0x0030
137 #define SPI_WNB_13 0x0034
138 #define SPI_WNB_14 0x0038
139 #define SPI_WNB_15 0x003c
140 #define SPI_WNB_16 0x0040
141 #define SPI_WNB_17 0x0044
142 #define SPI_WNB_18 0x0048
143 #define SPI_WNB_19 0x004c
144 #define SPI_WNB_20 0x0050
145 #define SPI_WNB_21 0x0054
146 #define SPI_WNB_22 0x0058
147 #define SPI_WNB_23 0x005c
148 #define SPI_WNB_24 0x0060
149 #define SPI_WNB_25 0x0064
150 #define SPI_WNB_26 0x0068
151 #define SPI_WNB_27 0x006c
152 #define SPI_WNB_28 0x0070
153 #define SPI_WNB_29 0x0074
154 #define SPI_WNB_30 0x0078
155 #define SPI_WNB_31 0x007c
156
157
158 // SPI possible device IDs
159 #define SPI_DEV0 0x0000
160 #define SPI_DEV1 0x0080
161 #define SPI_DEV2 0x0100
162 #define SPI_DEV3 0x0180
163 #define SPI_DEV4 0x0200
164
165 // ABB should be mapped as device 0
166 #define ABB SPI_DEV0
167
168
169 // SPI module bits definition of register SPI_REG_STATUS
170 #define RE_ST 0x0001 // bit 0
171 #define WE_ST 0x0002 // bit 1
172
173
174 /* The ARM emulator requires the spi clock always ON to be able to access */
175 /* spi registers through a window.*/
176 /* But it's better to stop the SPI clock in the GSM application to reduce the power consumption. */
177 /* Validate the next line to reduce power consumption */
178 //#define SPI_CLK_LOW_POWER
179
180
181
182 // STRUCTURES
183 typedef struct
184 {
185 SYS_UWORD16 PrescVal;
186 SYS_UWORD16 DataTrLength;
187 SYS_UWORD16 DevAddLength;
188 SYS_UWORD16 DevId;
189 SYS_UWORD16 ClkEdge;
190 SYS_UWORD16 TspEnLevel;
191 SYS_UWORD16 TspEnForm;
192 }T_SPI_DEV; // T_SPI_DEV is used to define an SPI device
193
194
195 // MACROS
196 #define SPI_WRITE_TX_LSB(TxLsb) { \
197 * (volatile SYS_UWORD16 *) SPI_REG_TX_LSB = TxLsb; }
198
199 #define SPI_WRITE_TX_MSB(TxMsb) { \
200 * (volatile SYS_UWORD16 *) SPI_REG_TX_MSB = TxMsb; }
201
202 #define SPI_START_WRITE {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_WR_ACTIV; }
203
204 #define SPI_START_READ {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_RDWR_ACTIV; }
205
206 #define SPI_CLK_DISABLE { \
207 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_CLK_ON; }
208
209 #define SPI_CLK_ENABLE { \
210 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_CLK_ON; }
211
212 #define SPI_MaskIT_WR { \
213 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_0; }
214
215 #define SPI_MaskIT_RD { \
216 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_1; }
217
218 #define SPI_Mask_All_IT { \
219 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_IT_MASK_0 | SPI_IT_MASK_1); }
220
221 #define SPI_UnmaskIT_WR { \
222 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_0; }
223
224 #define SPI_UnmaskIT_RD { \
225 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_1; }
226
227 #define SPI_Unmask_All_IT { \
228 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~(SPI_IT_MASK_0 | SPI_IT_MASK_1); }
229
230 #define SPI_Ready_for_WR { \
231 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0); }
232
233 #define SPI_Ready_for_RD { \
234 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_1); }
235
236 #define SPI_Ready_for_RDWR { \
237 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0 | SPI_IT_MASK_1); }
238
239
240
241 // INLINE FUNCTIONS
242 /*-----------------------------------------------------------------------*/
243 /* SPI_ReadRX_LSB() */
244 /* */
245 /* This function returns the value of SPI_REG_RX_LSB register */
246 /* */
247 /*-----------------------------------------------------------------------*/
248 static inline SYS_UWORD16 SPI_ReadRX_LSB(void)
249 {
250 return * (volatile SYS_UWORD16 *) SPI_REG_RX_LSB;
251 }
252
253
254 /*-----------------------------------------------------------------------*/
255 /* SPI_ReadRX_MSB() */
256 /* */
257 /* This function returns the value of SPI_REG_RX_MSB register */
258 /* */
259 /*-----------------------------------------------------------------------*/
260 static inline SYS_UWORD16 SPI_ReadRX_MSB(void)
261 {
262 return * (volatile SYS_UWORD16 *) SPI_REG_RX_MSB;
263 }
264
265
266
267 /*-----------------------------------------------------------------------*/
268 /* SPI_ReadStatus() */
269 /* */
270 /* This function returns the value of SPI_REG_STATUS register */
271 /* */
272 /*-----------------------------------------------------------------------*/
273 static inline SYS_UWORD16 SPI_ReadStatus(void)
274 {
275 return * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
276 }
277
278
279
280 // PROTOTYPES
281 void SPI_InitDev(T_SPI_DEV *Device);
282
283 #endif // __SPI_DRV_H__