tcs211-l1-reconst: chipsetsw/system/bootloader/src/bootloader.s annotate

annotate chipsetsw/system/bootloader/src/bootloader.s @ 159:3d39075c56bc

l1_trace.c: l1_trace_message() reconstructed

author	Mychaela Falconia <falcon@freecalypso.org>
date	Mon, 06 Jun 2016 20:54:47 +0000
parents	509db1a7b7b8
children

rev	line source
0 509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	1 ;/******************************************************************************
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	2 ; *
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	3 ; * BOOTLOADER.S
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	4 ; *
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	5 ; * This module initializes the system stack for the bootloader and calls the bootloader.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	6 ; * If the bootloader starts the function INT_Initialize is called.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	7 ; *
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	8 ; * (C) Texas Instruments 1999
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	9 ; *
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	10 ; *****************************************************************************/
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	12 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	13 ;/* Define constants used in low-level initialization. */
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	14 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	15
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	16 LOCKOUT .equ 00C0h ; Interrupt lockout value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	17 MODE_MASK .equ 001Fh ; Processor Mode Mask
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	18 SUP_MODE .equ 0013h ; Supervisor Mode (SVC)
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	19
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	20 SYSTEM_SIZE .equ 1024 ; Define the system stack size
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	21
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	22 .ref _sta_select_application
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	23 .ref _INT_Initialize
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	24
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	25 .ref end ; Ending address of BSS section
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	26
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	27
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	28 .sect ".text"
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	29
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	30 .def _INT_Bootloader_Start
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	31
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	32
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	33
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	34 addrCS0 .word 0xfffffb00 ;CS0 address space
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	35
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	36
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	37 .if BOARD = 6 ; EVA4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	38 .if CHIPSET != 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	39 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	40 CS1_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	41 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	42 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	43 CS4_MEM_REG .short 0xe85 ; default reset value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	44 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	45
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	46 .if CHIPSET = 3
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	47 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	48
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	49 .elseif CHIPSET = 4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	50 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	51 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	52
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	53 .elseif CHIPSET = 5
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	54 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	55
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	56 .elseif CHIPSET = 6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	57 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	58
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	59 .elseif CHIPSET = 7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	60 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	61 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	62
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	63 .elseif CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	64 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	65 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	66
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	67 .elseif CHIPSET = 10
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	68 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	69 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	70
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	71 .elseif CHIPSET = 11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	72 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	73 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM - 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	74
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	75 .elseif CHIPSET = 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	76 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	77 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	78 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	79 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	80
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	81 .elseif BOARD = 7 ; B-Sample
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	82 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	83 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	84 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	85 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	86 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	87
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	88 .if CHIPSET = 3
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	89 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	90
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	91 .elseif CHIPSET = 4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	92 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	93 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	94
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	95 .elseif CHIPSET = 5
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	96 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	97
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	98 .elseif CHIPSET = 6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	99 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	100
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	101 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	102
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	103 .elseif BOARD = 8 ; C-Sample SRAM CS0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	104 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	105 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	106 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	107 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	108 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	109
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	110 .if CHIPSET = 4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	111 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	112 CS7_MEM_REG .short 0x0c0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	113
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	114 .elseif CHIPSET = 7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	115 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	116 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	117
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	118 .elseif CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	119 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	120 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	121 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	122
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	123 .elseif BOARD = 9 ; C-Sample FLASH CS0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	124 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	125 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	126 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	127 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	128 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	129
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	130 .if CHIPSET = 4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	131 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	132 CS7_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	133
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	134 .elseif CHIPSET = 7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	135 CS6_MEM_REG .short 0x2c0 ; 1 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	136 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	137
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	138 .elseif CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	139 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	140 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	141 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	142
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	143 .elseif BOARD = 40 ; D-Sample SRAM CS0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	144 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	145 CS1_MEM_REG .short 0x2a3 ; 1 Dummy Cycle 16 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	146 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	147 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	148 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	149
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	150 .if CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	151 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	152 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	153
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	154 .elseif CHIPSET = 10
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	155 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	156 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	157
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	158 .elseif CHIPSET = 11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	159 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	160 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	161 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	162
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	163 .elseif BOARD = 41 ; D-Sample FLASH CS0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	164 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	165 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	166 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	167 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	168 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	169
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	170 .if CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	171 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	172 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	173
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	174 .elseif CHIPSET = 10
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	175 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	176 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	177
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	178 .elseif CHIPSET = 11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	179 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	180 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	181 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	182
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	183 .elseif BOARD = 43 ; E-Sample - FLASH
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	184 .if CHIPSET != 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	185 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	186 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	187 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	188 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	189 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	190
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	191 .else
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	192 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE BOARD 43 - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	193 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	194 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	195 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	196 .endif ; CHIPSET = 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	197
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	198 .elseif BOARD = 45 ; EVA_CONSO - FLASH
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	199
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	200 .if CHIPSET != 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	201 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	202 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	203 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	204 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	205 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	206 .else
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	207 CS0_MEM_REG .short 0x2a1 ; CALYPSO PLUS TEST MODE BOARD 43 - TO BE ERASED - 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	208 CS4_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	209 CS5_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	210 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	211 .endif ; CHIPSET = 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	212 .endif ; BOARD = 6 or 7 or 8 or 9 or 40 or 41 or 43 or 45
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	213
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	214
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	215 CTL_MEM_REG .short 0x02a ; rhea strobe 0/1 + API access size adaptation
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	216
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	217 .if CHIPSET = 4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	218 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	219 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	220 RHEA_CNTL_REG .word 0xFFFFF900 ; RHEA control register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	221
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	222 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	223 ; Use DPLL, Divide by 1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	224 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	225 RHEA_CONTROL_RST .short 0xFF22 ; Set access factor in order to access the DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	226 ; independently of the ARM clock
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	227
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	228 .elseif CHIPSET = 6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	229 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	230 ; Constants to configure ULYSSE G1 with VTCXO at 26MHz
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	231 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	232 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	233 CNTLCLK_26MHZ_SELECTOR .short 0x0040 ; VTCXO_26 selector
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	234
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	235 .elseif CHIPSET = 7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	236 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	237 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	238 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	239 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	240
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	241 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	242 ; Use DPLL, Divide by 1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	243 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	244 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	245 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	246
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	247 .elseif CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	248 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	249 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	250 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	251 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	252
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	253 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	254 ; Use DPLL, Divide by 1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	255 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	256 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	257 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	258
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	259 .elseif CHIPSET = 10
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	260 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	261 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	262 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	263 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	264
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	265 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	266 ; Use DPLL, Divide by 1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	267 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	268 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	269 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	270
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	271 .elseif CHIPSET = 11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	272 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	273 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	274 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	275 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	276
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	277 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	278 ; Use DPLL, Divide by 1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	279 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	280 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	281 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	282
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	283 .elseif CHIPSET = 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	284 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	285 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	286 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	287 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	288 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	289
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	290 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	291 ; Use DPLL, Divide by 1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	292 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	293 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	294 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	295 DBG_DMA_P2_RST .short 0x0002 ; DBG_DMA_P2 register reset value - GPO2 replaces ADD24
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	296
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	297 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	298
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	299 CLKM_MEM_REG .equ 0x31 ;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	300
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	301
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	302 _INT_Bootloader_Start
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	303
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	304 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	305 ; Basic initializations
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	306 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	307
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	308 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	309 ; Configuration of ARM clock and DPLL frequency
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	310 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	311 .if CHIPSET = 4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	312 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	313 ; Configure RHEA access factor in order to allow the access of DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	314 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	315 ldr r1,RHEA_CNTL_REG ; Load address of RHEA control register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	316 ldrh r2,RHEA_CONTROL_RST ; Load RHEA configuration value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	317 strh r2,[r1] ; Store DPLL reset value in RHEA control register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	318
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	319 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	320 ; Configure DPLL register with reset value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	321 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	322 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	323 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	324 strh r2,[r1] ; Store DPLL reset value in DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	325
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	326 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	327 ; Wait that DPLL goes in BYPASS mode
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	328 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	329 Wait_DPLL_Bypass
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	330 ldr r2,[r1] ; Load DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	331 and r2,r2,#1 ; Perform a mask on bit 0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	332 cmp r2,#1 ; Compare DPLL lock bit
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	333 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	334
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	335 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	336 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	337 ; generate ARM clock with division factor of 1.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	338 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	339 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	340 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	341 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	342
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	343 .elseif CHIPSET = 6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	344 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	345 ; Setting of VTCXO_26MHZ bit to '1' in order to divide reference clock for peripherals.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	346 ; This setting is required on ULYSSE G1 with a VTCXO clock to 26MHz.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	347 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	348 ldr r1,CNTL_ARM_CLK_REG ; Load CLKM base register address in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	349 ldrh r2,[r1,#2] ; Load contents of CNTL_CLK register in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	350 ldr r0,CNTLCLK_26MHZ_SELECTOR ; Load configuration of 26MHz selector
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	351 orr r0,r0,r2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	352 strh r0,[r1,#2]
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	353
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	354 .elseif CHIPSET = 7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	355 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	356 ; Configure DPLL register with reset value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	357 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	358 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	359 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	360 strh r2,[r1] ; Store DPLL reset value in DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	361
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	362 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	363 ; Wait that DPLL goes in BYPASS mode
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	364 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	365 Wait_DPLL_Bypass
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	366 ldr r2,[r1] ; Load DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	367 and r2,r2,#1 ; Perform a mask on bit 0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	368 cmp r2,#1 ; Compare DPLL lock bit
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	369 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	370
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	371 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	372 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	373 ; generate ARM clock with division factor of 1.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	374 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	375 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	376 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	377 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	378
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	379 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	380 ; Disable the DU module by setting bit 11 to '1'
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	381 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	382 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	383 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	384 ldrh r0,[r1] ; Load Extra Control register CONF in r0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	385 orr r0,r0,r2 ; Disable DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	386 strh r0,[r1] ; Store configuration in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	387
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	388 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	389 ; Disable all MPU protections
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	390 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	391 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	392 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	393 strh r2,[r1] ; Store reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	394
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	395 .elseif CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	396 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	397 ; Configure DPLL register with reset value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	398 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	399 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	400 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	401 strh r2,[r1] ; Store DPLL reset value in DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	402
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	403 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	404 ; Wait that DPLL goes in BYPASS mode
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	405 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	406 Wait_DPLL_Bypass
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	407 ldr r2,[r1] ; Load DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	408 and r2,r2,#1 ; Perform a mask on bit 0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	409 cmp r2,#1 ; Compare DPLL lock bit
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	410 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	411
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	412 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	413 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	414 ; generate ARM clock with division factor of 1.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	415 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	416 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	417 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	418 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	419
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	420 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	421 ; Disable the DU module by setting bit 11 to '1'
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	422 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	423 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	424 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	425 ldrh r0,[r1] ; Load Extra Control register CONF in r0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	426 orr r0,r0,r2 ; Disable DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	427 strh r0,[r1] ; Store configuration in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	428
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	429 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	430 ; Disable all MPU protections
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	431 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	432 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	433 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	434 strh r2,[r1] ; Store reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	435
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	436
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	437 .elseif CHIPSET = 10
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	438 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	439 ; Configure DPLL register with reset value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	440 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	441 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	442 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	443 strh r2,[r1] ; Store DPLL reset value in DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	444
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	445 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	446 ; Wait that DPLL goes in BYPASS mode
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	447 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	448 Wait_DPLL_Bypass
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	449 ldr r2,[r1] ; Load DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	450 and r2,r2,#1 ; Perform a mask on bit 0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	451 cmp r2,#1 ; Compare DPLL lock bit
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	452 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	453
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	454 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	455 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	456 ; generate ARM clock with division factor of 1.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	457 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	458 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	459 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	460 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	461
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	462 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	463 ; Disable the DU module by setting bit 11 to '1'
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	464 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	465 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	466 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	467 ldrh r0,[r1] ; Load Extra Control register CONF in r0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	468 orr r0,r0,r2 ; Disable DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	469 strh r0,[r1] ; Store configuration in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	470
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	471 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	472 ; Disable all MPU protections
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	473 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	474 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	475 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	476 strh r2,[r1] ; Store reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	477
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	478 .elseif CHIPSET = 11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	479 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	480 ; Configure DPLL register with reset value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	481 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	482 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	483 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	484 strh r2,[r1] ; Store DPLL reset value in DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	485
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	486 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	487 ; Wait that DPLL goes in BYPASS mode
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	488 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	489 Wait_DPLL_Bypass
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	490 ldr r2,[r1] ; Load DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	491 and r2,r2,#1 ; Perform a mask on bit 0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	492 cmp r2,#1 ; Compare DPLL lock bit
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	493 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	494
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	495 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	496 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	497 ; generate ARM clock with division factor of 1.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	498 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	499 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	500 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	501 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	502
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	503 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	504 ; Disable the DU module by setting bit 11 to '1'
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	505 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	506 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	507 ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	508 ldrh r0,[r1] ; Load Extra Control register CONF in r0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	509 orr r0,r0,r2 ; Disable DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	510 strh r0,[r1] ; Store configuration in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	511
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	512 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	513 ; Disable all MPU protections
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	514 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	515 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	516 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	517 strh r2,[r1] ; Store reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	518
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	519 .elseif CHIPSET = 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	520 .if BOARD = 6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	521 ; Configure DBG_DMA_P2 reg => GPO_2 output pin for EVA4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	522 ldr r1,DBG_DMA_P2 ; Load address of DBG_DMA_P2 register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	523 ldrh r2,DBG_DMA_P2_RST ; Load DBG_DMA_P2 reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	524 strh r2,[r1] ; Store reset value in register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	525 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	526 .endif ; BOARD = 6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	527 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	528 ; Configure DPLL register with reset value
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	529 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	530 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	531 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	532 strh r2,[r1] ; Store DPLL reset value in DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	533
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	534 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	535 ; Wait that DPLL goes in BYPASS mode
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	536 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	537 Wait_DPLL_Bypass
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	538 ldr r2,[r1] ; Load DPLL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	539 and r2,r2,#1 ; Perform a mask on bit 0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	540 cmp r2,#1 ; Compare DPLL lock bit
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	541 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0')
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	542
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	543 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	544 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	545 ; generate ARM clock with division factor of 1.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	546 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	547 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	548 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	549 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	550
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	551 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	552 ; Disable the DU module by setting bit 11 to '1'
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	553 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	554 ; ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	555 ; ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	556 ; ldrh r0,[r1] ; Load Extra Control register CONF in r0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	557 ; orr r0,r0,r2 ; Disable DU module
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	558 ; strh r0,[r1] ; Store configuration in Extra Control register CONF
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	559
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	560 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	561 ; Disable all MPU protections
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	562 ;
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	563 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	564 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	565 strh r2,[r1] ; Store reset value of MPU_CTL register
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	566
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	567 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	568
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	569 ldr r1,addrCS0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	570
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	571 .if CHIPSET = 12
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	572 ldrh r2,CS0_MEM_REG ; CALYPSO PLUS TEST MODE - TO BE ERASED - ROM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	573 strh r2,[r1, #0x00] ; CS5
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	574
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	575 ldrh r2,CS5_MEM_REG ; ROM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	576 strh r2,[r1, #0x0A] ; CS5
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	577
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	578 ldrh r2,CS4_MEM_REG ; RAM Initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	579 strh r2,[r1,#0x08] ; CS4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	580
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	581 .else
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	582 ldrh r2,CS0_MEM_REG ; ROM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	583 strh r2,[r1] ; CS0
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	584
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	585 ldrh r2,CS1_MEM_REG ; RAM Initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	586 strh r2,[r1,#2] ; CS1
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	587
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	588 ldrh r2,CS2_MEM_REG ; RAM Initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	589 strh r2,[r1,#4] ; CS2
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	590
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	591 ldrh r2,CS3_MEM_REG ; parallel I/O
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	592 strh r2,[r1,#6] ; CS3
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	593
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	594 ldrh r2,CS4_MEM_REG ; Debug Latch
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	595 strh r2,[r1,#0xa] ; CS4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	596 .endif
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	597
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	598 .if CHIPSET = 3
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	599 ldrh r2,CS6_MEM_REG ; Ulysse/G0 Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	600 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	601
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	602 .elseif CHIPSET = 4
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	603 ldrh r2,CS6_MEM_REG ; Samson Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	604 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	605
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	606 ldrh r2,CS7_MEM_REG ; Internal Boot RAM
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	607 strh r2,[r1,#0x8] ; CS7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	608
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	609 .elseif CHIPSET = 5
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	610 ldrh r2,CS6_MEM_REG ; Ulysse/G1 Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	611 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	612
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	613 .elseif CHIPSET = 6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	614 ldrh r2,CS6_MEM_REG ; Ulysse/G1 Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	615 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	616
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	617 .elseif CHIPSET = 7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	618 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	619 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	620
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	621 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	622 strh r2,[r1,#0x8] ; CS7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	623
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	624 .elseif CHIPSET = 8
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	625 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	626 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	627
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	628 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	629 strh r2,[r1,#0x8] ; CS7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	630
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	631 .elseif CHIPSET = 10
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	632 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	633 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	634
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	635 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	636 strh r2,[r1,#0x8] ; CS7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	637
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	638 .elseif CHIPSET = 11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	639 ldrh r2,CS6_MEM_REG ; Calypso/G2 Internal SRAM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	640 strh r2,[r1,#0xc] ; CS6
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	641
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	642 ldrh r2,CS7_MEM_REG ; Internal Boot ROM initialization
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	643 strh r2,[r1,#0x8] ; CS7
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	644
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	645 .endif ; CHIPSET = 3 or 4 or 5 or 6 or 7 or 8 or 10 or 11
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	646
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	647 ldrh r2,CTL_MEM_REG ; API-RHEA configuration
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	648 strh r2,[r1,#0xe]
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	649
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	650 ; Initialize the system stack to allow to use the bootloader.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	651
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	652 LDR a1,BSS_End ; Pickup the ending address of BSS
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	653 MOV a2,#SYSTEM_SIZE ; Pickup system stack size
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	654 SUB a2,a2,#4 ; Subtract one word for first addr
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	655 ADD a3,a1,a2 ; Build start of system stack area
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	656 BIC a3,a3,#3 ; Insure word aligment of stack
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	657 MOV sp,a3 ; Setup initial stack pointer
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	658
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	659
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	660 ; Call the function which allows to select the bootloader or the user's
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	661 ; application.
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	662
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	663 STMFD sp!, {a1-a4,R12}
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	664 BL _sta_select_application
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	665 LDMFD sp!, {a1-a4,R12}
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	666
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	667 B _INT_Initialize
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	668
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	669 ; /* Define all the global addresses used in this section */
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	670
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	671 BSS_End
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	672 .word end
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	673
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	674 .end
509db1a7b7b8 initial import: leo2moko-r1 Space Falcon <falcon@ivan.Harhan.ORG> parents: diff changeset	675

FreeCalypso > hg > tcs211-l1-reconst

annotate chipsetsw/system/bootloader/src/bootloader.s @ 159:3d39075c56bc