FreeCalypso > hg > tcs211-l1-reconst

annotate chipsetsw/drivers/drv_core/rhea/rhea_arm.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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10
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11 Filename : rhea_arm.h
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12
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13 Description : Header file for the ARM RHEA interface
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14
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15 Project : drivers
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16
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17 Author : pmonteil@tif.ti.com Patrice Monteil.
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18
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19 Version number : 1.5
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20
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21 Date and time : 01/30/01 10:22:28
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22
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23 Previous delta : 12/08/00 11:38:10
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24
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25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.rhea_arm.h
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26
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27 Sccs Id (SID) : '@(#) rhea_arm.h 1.5 01/30/01 10:22:28 '
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28
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29
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30 *****************************************************************************/
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31
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32 #include "chipset.cfg"
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33
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34 /**** RHEA control register ****/
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35
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36 #define RHEA_CNTL_FACT_0 0x000f /* Division factor for strobe 0 */
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37 #define RHEA_CNTL_FACT_1 0x00f0 /* Division factor for strobe 1 */
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38 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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39 #define RHEA_CNTL_TIMEOUT 0xff00 /* RHEA bus access timeout */
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40 #else
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41 #define RHEA_CNTL_TIMEOUT 0xfe00 /* RHEA bus access timeout */
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42 #endif
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43
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44 /**** API control register ****/
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45
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46 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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47 #define RHEA_API_WS_H 0x001f /* API wait states when DSP is in HOM mode */
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48 #define RHEA_API_WS_S 0x03e0 /* API wait states when DSP in in SAM mode */
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49 #else
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50 #define RHEA_API_WS_H 0x001f /* API wait states for High clkout */
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51 #define RHEA_API_WS_L 0x02e0 /* API wait states for Low clkout */
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52 #endif
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53
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54 /**** ARM RHEA control register ****/
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55
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56 #define RHEA_ARM_WEN_0 0x0001 /* Write enable for strobe 0 */
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57 #define RHEA_ARM_WEN_1 0x0002 /* Write enable for strobe 1 */
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58
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59 /*--------------------------------------------------------------
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60 * RHEA_INITRHEA()
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61 *--------------------------------------------------------------
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62 * Parameters :Fac0 acces factor strb0, Fac1 acces factor strb1
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63 * timeout max time periph stall the processor
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64 * Return : none
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65 * Functionality :Initialize the RHEA control register
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66 *--------------------------------------------------------------*/
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67
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68 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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69 #define RHEA_INITRHEA(Fac0,Fac1,TimeOut) (* (unsigned short *) MEM_RHEA_CNTL = (Fac0 | Fac1 << 4 | TimeOut << 8))
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70 #else
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71 #define RHEA_INITRHEA(Fac0,Fac1,TimeOut) (* (unsigned short *) MEM_RHEA_CNTL = (Fac0 | Fac1 << 4 | TimeOut << 9))
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72 #endif
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73
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74 /*--------------------------------------------------------------
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75 * RHEA_INITAPI()
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76 *--------------------------------------------------------------
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77 * Parameters :wsH wait states when freq high, wsL wait states
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78 * when freq low
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79 * Return : none
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80 * Functionality :Initialize the API control register
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81 *--------------------------------------------------------------*/
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82
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83 #define RHEA_INITAPI(wsH, wsL) (* (SYS_UWORD16 *) MEM_API_CNTL = ((wsH) | (wsL) << 5))
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84
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85 /*--------------------------------------------------------------
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86 * RHEA_INITARM()
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87 *--------------------------------------------------------------
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88 * Parameters : Wen0 write enable domain strb0
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89 * Wen1 write enable domain strb1
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90 * Return : none
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91 * Functionality :Initialize the ARM RHEA control register
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92 *--------------------------------------------------------------*/
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93
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94 #define RHEA_INITARM(Wen0,Wen1) (* (SYS_UWORD16 *) MEM_ARM_RHEA = ((Wen0) | (Wen1) << 1))