FreeCalypso > hg > tcs211-l1-reconst
annotate chipsetsw/system/Main/init.asm @ 91:51f3b9364365
l1_ctl.c: l1ctl_dpagc() reconstructed
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Thu, 07 Apr 2016 14:46:04 +0000 |
parents | 509db1a7b7b8 |
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rev | line source |
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1 ;****************************************************************************** |
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2 ; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
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3 ; |
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4 ; Property of Texas Instruments -- For Unrestricted Internal Use Only |
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5 ; Unauthorized reproduction and/or distribution is strictly prohibited. This |
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6 ; product is protected under copyright law and trade secret law as an |
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7 ; unpublished work. Created 1987, (C) Copyright 1996 Texas Instruments. All |
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8 ; rights reserved. |
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9 ; |
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10 ; |
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11 ; Filename : init.asm |
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12 ; |
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13 ; Description : Environment configuration |
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14 ; |
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15 ; Project : drivers |
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16 ; |
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17 ; Author : pmonteil@tif.ti.com Patrice Monteil. |
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18 ; |
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19 ; Version number : 1.4 |
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20 ; |
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21 ; Date and time : 03/06/01 10:44:19 |
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22 ; |
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23 ; Previous delta : 12/19/00 14:28:47 |
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24 ; |
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25 ; SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_C_SAMPLE_REQ1145_BIS/drivers1/board_7/SCCS/s.init.asm |
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26 ; |
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27 ; Sccs Id (SID) : '@(#) init.asm 1.4 03/06/01 10:44:19 ' |
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28 ; |
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29 ; |
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30 ;***************************************************************************** |
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31 |
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32 ; use in int.s for first initializations |
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33 |
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34 .if BOARD = 6 |
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35 |
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36 .if CHIPSET != 12 |
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37 CS0_MEM_REG .short 0x2A0 ;ROM init : 0 WS, 16 bits, little |
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38 CS1_MEM_REG .short 0x281 ;RAM init : 1 WS, 8 bits, little |
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39 CS2_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little |
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40 CS3_MEM_REG .short 0x283 ;RAM init : 5 WS, 8 bits, little |
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41 CS4_MEM_REG .short 0xe85 ;RAM init : 5 WS, 8 bits, little |
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42 .endif |
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43 |
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44 .if CHIPSET = 3 |
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45 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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46 .elseif CHIPSET = 4 |
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47 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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48 CS7_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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49 .elseif CHIPSET = 5 |
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50 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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51 .elseif CHIPSET = 6 |
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52 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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53 .elseif CHIPSET = 7 |
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54 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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55 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
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56 .elseif CHIPSET = 8 |
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57 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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58 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
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59 .elseif CHIPSET = 10 |
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60 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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61 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
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62 .elseif CHIPSET = 11 |
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63 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable |
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64 CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
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65 .elseif CHIPSET = 12 |
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66 CS0_MEM_REG .short 0x2A1 ;CALYPSO PLUS TEST MODE - TO BE ERASED - RAM init : 1 WS, 16 bits, little |
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67 CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little |
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68 CS5_MEM_REG .short 0x2A1 ;ROM init : 0 WS, 16 bits, little |
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69 .endif ; CHIPSET = 3, 4, 5, 6, 7, 8, 10 or 11 or 12 |
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70 |
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71 .elseif BOARD = 7 |
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72 |
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73 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
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74 .if OP_WCP = 1 |
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75 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable |
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76 .else |
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77 CS1_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable |
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78 .endif |
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79 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
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80 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable |
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81 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable |
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82 .if CHIPSET = 3 |
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83 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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84 .elseif CHIPSET = 4 |
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85 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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86 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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87 .elseif CHIPSET = 5 |
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88 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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89 .elseif CHIPSET = 6 |
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90 .if OP_WCP = 1 |
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91 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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92 .else |
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93 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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94 .endif |
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95 .endif ; CHIPSET = 3, 4, 5 or 6 |
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96 |
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97 .elseif BOARD = 8 |
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98 |
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99 CS0_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable |
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100 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
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101 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
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102 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable |
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103 CS4_MEM_REG .short 0xe85 ; default reset value |
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104 .if CHIPSET = 4 |
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105 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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106 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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107 .elseif CHIPSET = 7 |
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108 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
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109 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
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110 .elseif CHIPSET = 8 |
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111 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
112 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
113 .endif ; CHIPSET = 4, 7 or 8 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
114 .elseif BOARD = 9 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
115 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
116 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
117 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
118 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
119 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
120 CS4_MEM_REG .short 0xe85 ; default reset value |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
121 .if CHIPSET = 4 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
122 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
123 CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
124 .elseif CHIPSET = 7 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
125 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
126 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
127 .elseif CHIPSET = 8 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
128 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
129 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
130 .endif ; CHIPSET = 4, 7 or 8 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
131 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
132 .elseif BOARD = 35 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
133 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
134 CS0_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
135 CS1_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
136 CS2_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
137 CS6_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
138 CS7_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
139 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
140 API_ADAPT .equ 0x6A |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
141 CS7_SIZE .equ 0x2000 ; 8 kB |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
142 CS7_ADDR .equ 0x03800000 ; Initial address before toggling nIBOOT |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
143 SRAM_ADDR .equ 0x00800000 ; Internal SRAM start address |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
144 SRAM_SIZE .equ 0x00050000 ; 2.5 MBits |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
145 armio_in .word 0xFFFE4800 ; ARMIO_IN register address |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
146 armio_out .word 0xFFFE4802 ; ARMIO_OUT register address |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
147 addrExtraConf .word 0xFFFFFB10 ; Extra configuration |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
148 addrCS7 .word 0xFFFFFB08 ; CS7 configuration |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
149 DEF_EXTRA_CONF .short 0x033E ; Default configuration |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
150 EXTRA_CONF .short 0x013E ; Boot configuration |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
151 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
152 .elseif BOARD = 40 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
153 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
154 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
155 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
156 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
157 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
158 CS4_MEM_REG .short 0xe85 ; default reset value |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
159 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
160 .if CHIPSET = 8 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
161 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
162 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
163 .elseif CHIPSET = 10 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
164 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
165 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
166 .elseif CHIPSET = 11 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
167 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
168 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
169 .endif ; CHIPSET = 8, 10 or 11 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
170 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
171 .elseif BOARD = 41 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
172 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
173 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
174 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
175 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
176 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
177 CS4_MEM_REG .short 0xe85 ; default reset value |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
178 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
179 .if CHIPSET = 8 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
180 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
181 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
182 .elseif CHIPSET = 10 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
183 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
184 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
185 .elseif CHIPSET = 11 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
186 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
187 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
188 .endif ; CHIPSET = 8, 10 or 11 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
189 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
190 .elseif BOARD = 43 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
191 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
192 .if CHIPSET = 12 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
193 CS0_MEM_REG .short 0x2A0 ;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM init : 1 WS, 16 bits, little |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
194 CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
195 CS5_MEM_REG .short 0x2A0 ;ROM init : 0 WS, 16 bits, little |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
196 .endif ; CHIPSET = 12 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
197 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
198 .elseif BOARD = 45 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
199 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
200 .if CHIPSET = 12 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
201 CS0_MEM_REG .short 0x2A1 ;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM init : 1 WS, 16 bits, little |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
202 CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
203 CS5_MEM_REG .short 0x2A1 ; init : 0 WS, 16 bits, little |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
204 .endif ; CHIPSET = 12 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
205 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
206 .endif ; BOARD |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
207 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
208 CLKM_MEM_REG .equ 0x31 ;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
209 CTL_MEM_REG .short 0x02a ; rhea strobe 0/1 + API access size adaptation |