FreeCalypso > hg > tcs211-l1-reconst

annotate chipsetsw/drivers/drv_core/memif/sys_memif.h @ 15:6814a6bced4f

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beginning of tcs211-l1-reconst: created dummies for all L1 C source files
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Wed, 21 Oct 2015 01:57:01 +0000
parents 509db1a7b7b8
children
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1 /* @(#) nom : sys_memif.h SID: 1.2 date : 05/23/03 */
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2 /* Filename: sys_memif.h */
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3 /* Version: 1.2 */
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4 /******************************************************************************
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5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
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6 *
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7 * (C) 2002 Texas Instruments France. All rights reserved
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8 *
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9 * Author : Francois AMAND
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10 *
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11 *
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12 * Important Note
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13 * --------------
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14 *
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15 * This S/W is a preliminary version. It contains information on a product
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16 * under development and is issued for evaluation purposes only. Features
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17 * characteristics, data and other information are subject to change.
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18 *
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19 * The S/W is furnished under Non Disclosure Agreement and may be used or
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20 * copied only in accordance with the terms of the agreement. It is an offence
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21 * to copy the software in any way except as specifically set out in the
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22 * agreement. No part of this document may be reproduced or transmitted in any
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23 * form or by any means, electronic or mechanical, including photocopying and
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24 * recording, for any purpose without the express written permission of Texas
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25 * Instruments Inc.
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26 *
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27 ******************************************************************************
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28 *
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29 * FILE NAME: sys_memif.h
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30 *
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31 *
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32 * PURPOSE: Include file to use the ARM memory interface drivers for CALYPSO
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33 * PLUS.
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34 * The drivers allows ARM memory interface configuration and
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35 * control.
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36 *
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37 *
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38 * FILE REFERENCES:
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39 *
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40 * Name IO Description
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41 * ------------- -- ---------------------------------------------
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42 *
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43 *
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44 *
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45 * EXTERNAL VARIABLES:
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46 *
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47 * Source:
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48 *
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49 * Name Type IO Description
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50 * ------------- --------------- -- ------------------------------
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51 *
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52 *
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53 *
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54 * EXTERNAL REFERENCES:
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55 *
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56 * Name Description
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57 * ------------------ -------------------------------------------------------
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58 *
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59 *
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60 *
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61 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
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62 *
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63 *
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64 *
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65 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
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66 *
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67 *
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68 *
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69 * NOTES:
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70 *
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71 *
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72 *
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73 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
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74 *
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75 *
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76 *
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77 *
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78 * DEVELOPMENT HISTORY:
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79 *
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80 * Date Name(s) Version Description
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81 * ----------- -------------- ------- -------------------------------------
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82 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation
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83 * 24-Feb-2003 G.Leterrier 0.0.2 change include name for mapping definition
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84 * 25 Feb-2003 G.Leterrier 0.0.3 Change MACRO to take in account reserved bit in registers
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85 *
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86 * ALGORITHM:
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87 *
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88 *
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89 *****************************************************************************/
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90
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91
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92 #ifndef __SYS_MEMIF_H__
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93 #define __SYS_MEMIF_H__
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94
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95 #include "l1sw.cfg"
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96 #include "chipset.cfg"
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97
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98 #if (CHIPSET == 12)
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99
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100 #if (OP_L1_STANDALONE == 0)
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101 #include "main/sys_types.h"
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102 #else
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103 #include "sys_types.h"
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104 #endif
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105
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106 #include "sys_map.h"
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107
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108 /****************************************************************************
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109 * CONSTANT DEFINITION
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110 ***************************************************************************/
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111
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112 /*
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113 * Chip-select offset definition
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114 */
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115 #define C_MEMIF_CS0_OFFSET 0
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116 #define C_MEMIF_CS1_OFFSET 1
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117 #define C_MEMIF_CS2_OFFSET 2
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118 #define C_MEMIF_CS3_OFFSET 3
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119 #define C_MEMIF_CS4_OFFSET 4
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120 #define C_MEMIF_CS5_OFFSET 5
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121
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122 #define C_MEMIF_NB_EXTERNAL_CS 6
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123
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124 #define C_MEMIF_CS_SIZE_MAX_MB 64
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125
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126 #define C_MEMIF_INTERNAL_SRAM_START_ADDR 0x08000000
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127
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128 /*
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129 * Registers offset definition
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130 */
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131 #define C_MEMIF_CONF_CSX_OFFSET(cs_index) (0x00 + 2 * cs_index)
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132 #define C_MEMIF_EXWS_CSX_OFFSET(cs_index) (0x20 + 2 * cs_index)
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133 #define C_MEMIF_DCCTRL_CSX_OFFSET(cs_index) (0x30 + 2 * cs_index)
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134 #define C_MEMIF_API_RHEA_CTRL_OFFSET 0x0E
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135 #define C_MEMIF_EX_CTRL_OFFSET 0x10
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136 #define C_MEMIF_DSPMS_OFFSET 0x2E
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137
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138
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139 /*
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140 * Registers address definition
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141 */
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142 #define C_MEMIF_CONF_CSX_REG(cs_index) * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_CONF_CSX_OFFSET(cs_index))
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
143 #define C_MEMIF_EXWS_CSX_REG(cs_index) * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_EXWS_CSX_OFFSET(cs_index))
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
144 #define C_MEMIF_DCCTRL_CSX_REG(cs_index) * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_DCCTRL_CSX_OFFSET(cs_index))
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
145 #define C_MEMIF_API_RHEA_CTRL_REG * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_API_RHEA_CTRL_OFFSET)
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
146 #define C_MEMIF_EX_CTRL_REG * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_EX_CTRL_OFFSET)
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
147 #define C_MEMIF_DSPMS_REG * (volatile SYS_UWORD16 *) (C_MAP_MEMIF_BASE + C_MEMIF_DSPMS_OFFSET)
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
148
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
149
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
150
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
151 /*
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
152 * CONF_CSx register definition
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
153 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
154 #define C_MEMIF_CONF_CSX_MASK 0x0100
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
155 /* Bits position in the register */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
156 #define C_MEMIF_CONF_WS_POS 0
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
157 #define C_MEMIF_CONF_DVS_POS 5
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
158 #define C_MEMIF_CONF_WE_POS 7
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
159 #define C_MEMIF_CONF_DC_POS 9
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
160 #define C_MEMIF_CONF_RODC_POS 12
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
161 #define C_MEMIF_CONF_WRDC_POS 13
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
162 #define C_MEMIF_CONF_WWS_POS 14
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
163
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
164 /* DVS bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
165 #define C_MEMIF_DVS_8 0 /* device size = 8 bits */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
166 #define C_MEMIF_DVS_16 1 /* device size = 16 bits */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
167 #define C_MEMIF_DVS_32 2 /* device size = 32 bits */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
168
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
169 /* WE bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
170 #define C_MEMIF_WRITE_DIS 0 /* write disable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
171 #define C_MEMIF_WRITE_EN 1 /* write enable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
172
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
173 /* RODC bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
174 #define C_MEMIF_RODC_DIS 0 /* Read Only Dummy Cycle mode Enable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
175 #define C_MEMIF_RODC_EN 1 /* Read Only Dummy Cycle mode Disable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
176
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
177 /* WRDC bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
178 #define C_MEMIF_WRDC_DIS 0 /* Write-Read Insertion Dummy Cycle mode Enable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
179 #define C_MEMIF_WRDC_EN 1 /* Write-Read Insertion Dummy Cycle mode Disable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
180
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
181 /* WWS bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
182 #define C_MEMIF_WWS_VALUE_DIS 1 /* WRSS value use for write and WS for read access */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
183 #define C_MEMIF_WWS_VALUE_EN 0 /* WS value use for write and read access */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
184
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
185
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
186
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
187 /*
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
188 * EXWS_CSx register definition
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
189 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
190 #define C_MEMIF_EXWS_MASK 0x0038
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
191 /* Bits position in the register */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
192 #define C_MEMIF_EXWS_PME_POS 0
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
193 #define C_MEMIF_EXWS_PMS_POS 1
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
194 #define C_MEMIF_EXWS_PMWS_POS 6
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
195 #define C_MEMIF_EXWS_WRWS_POS 11
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
196
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
197 /* PME bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
198 #define C_MEMIF_PAGE_MODE_DIS 0 /* Page mode disable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
199 #define C_MEMIF_PAGE_MODE_EN 1 /* Page mode enable */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
200
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
201 /* PMS bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
202 #define C_MEMIF_PMS_2B 0 /* Page size = 2 bytes */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
203 #define C_MEMIF_PMS_4B 1 /* Page size = 4 bytes */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
204 #define C_MEMIF_PMS_8B 2 /* Page size = 8 bytes */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
205 #define C_MEMIF_PMS_16B 3 /* Page size = 16 bytes */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
206
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
207
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
208
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
209 /*
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
210 * DCCTRL_CSx register definition
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
211 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
212 /* Bits position in the register */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
213 #define C_MEMIF_DCCTRL_DCECS0_POS 0
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
214 #define C_MEMIF_DCCTRL_DCECS1_POS 1
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
215 #define C_MEMIF_DCCTRL_DCECS2_POS 2
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
216 #define C_MEMIF_DCCTRL_DCECS3_POS 3
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
217 #define C_MEMIF_DCCTRL_DCECS4_POS 4
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
218 #define C_MEMIF_DCCTRL_DCECS5_POS 5
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
219
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
220 /* DCECSx bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
221 #define C_MEMIF_DCECS_DIS 0 /* No DC */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
222 #define C_MEMIF_DCECS_EN 1 /* Insert Dummy Cycle if previous CSn is CSn */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
223
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
224
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
225
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
226 /*
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
227 * EX_CTRL register definition
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
228 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
229 #define C_MEMIF_EX_CTRL_MASK 0x0780
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
230 /* Bits position in the register */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
231 #define C_MEMIF_EX_CTRL_WSR_POS 0
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
232 #define C_MEMIF_EX_CTRL_CTRL_WS0_POS 1
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
233 #define C_MEMIF_EX_CTRL_CTRL_WS1_POS 2
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
234 #define C_MEMIF_EX_CTRL_CTRL_WS2_POS 3
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
235 #define C_MEMIF_EX_CTRL_CTRL_WS3_POS 4
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
236 #define C_MEMIF_EX_CTRL_CTRL_WS4_POS 5
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
237 #define C_MEMIF_EX_CTRL_CTRL_WS5_POS 6
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
238 #define C_MEMIF_EX_CTRL_DISABLE_DU_POS 11
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
239 #define C_MEMIF_EX_CTRL_CS_MODE_POS 12
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
240 #define C_MEMIF_EX_CTRL_CS_MODE_EN_POS 14
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
241 #define C_MEMIF_EX_CTRL_EX_PAGEM_POS 15
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
242
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
243 /* DISABLE_DU bit definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
244 #define C_MEMIF_EX_CTRL_DU_EN 0 /* DU capture is enabled */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
245 #define C_MEMIF_EX_CTRL_DU_DIS 1 /* DU capture is disabled */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
246
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
247 /* CS_MODE bits definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
248 #define C_MEMIF_EX_CTRL_CS_MODE_MASK 0x0003
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
249
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
250 #define C_MEMIF_EX_CTRL_CS_MODE_0 0 /* CS_MODE configuration 0 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
251 #define C_MEMIF_EX_CTRL_CS_MODE_1 1 /* CS_MODE configuration 1 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
252 #define C_MEMIF_EX_CTRL_CS_MODE_2 2 /* CS_MODE configuration 2 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
253 #define C_MEMIF_EX_CTRL_CS_MODE_3 3 /* CS_MODE configuration 3 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
254
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
255 /* CS_MODE_EN bit definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
256 #define C_MEMIF_EX_CTRL_CS_MODE_FREEZE 1 /* Freeze CS_MODE configuration and access to CS_MODE_EN bit */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
257
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
258 /* EX_PAGEM bit definition */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
259 #define C_MEMIF_EX_CTRL_EX_PAGEM_DIS 0 /* Disable extended page-mode */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
260 #define C_MEMIF_EX_CTRL_EX_PAGEM_EN 1 /* Enable extended page-mode */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
261
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
262
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
263
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
264 /*
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
265 * API_RHEA_CTRL register definition
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
266 */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
267 #define C_MEMIF_API_RHEA_CTRL_MASK 0x0015
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
268 /* Bits position in the register */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
269 #define C_MEMIF_API_RHEA_CTRL_ADAPT0_POS 1
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
270 #define C_MEMIF_API_RHEA_CTRL_ADAPT1_POS 3
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
271 #define C_MEMIF_API_RHEA_CTRL_ADAPTAPI_POS 5
509db1a7b7b8 initial import: leo2moko-r1
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272 #define C_MEMIF_API_RHEA_CTRL_DEBUG_POS 6
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273
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274 /* ADAPT0, ADAPT1 and ADAPTAPI bits definition */
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275 #define C_MEMIF_API_RHEA_NO_ADAPT 0 /* no memory adaptation */
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276 #define C_MEMIF_API_RHEA_ADAPT 1 /* memory adaptation */
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277
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278 /* DEBUG bits definition */
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279 #define C_MEMIF_API_RHEA_NO_DEBUG 0 /* no ARM address can be observed */
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280 #define C_MEMIF_API_RHEA_DEBUG 1 /* ARM address can be observed */
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281
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282
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283
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Space Falcon <falcon@ivan.Harhan.ORG>
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284 /*
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285 * DSPMS register definition
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Space Falcon <falcon@ivan.Harhan.ORG>
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286 */
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287 /* Bits position in the register */
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288 #define C_MEMIF_DSPMS_POS 0
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289
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290 /* DSPMS bit definition */
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291 #define C_MEMIF_DSPMS_MASK 0x0003
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292 #define C_MEMIF_DSPMS_0MBITS_TO_DSP 0x0000
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293 #define C_MEMIF_DSPMS_0_5MBITS_TO_DSP 0x0001
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294
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295
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296
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297
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298 /****************************************************************************
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299 * MACRO DEFINITION
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300 ***************************************************************************/
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301
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302 #define F_MEMIF_ENABLE_EXTENDED_PAGE_MODE C_MEMIF_EX_CTRL_REG |= (C_MEMIF_EX_CTRL_EX_PAGEM_EN << C_MEMIF_EX_CTRL_EX_PAGEM_POS)
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303
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304 #define F_MEMIF_DU_ENABLE C_MEMIF_EX_CTRL_REG &= ~(C_MEMIF_EX_CTRL_DU_DIS << C_MEMIF_EX_CTRL_DISABLE_DU_POS)
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305 #define F_MEMIF_DU_DISABLE C_MEMIF_EX_CTRL_REG |= (C_MEMIF_EX_CTRL_DU_DIS << C_MEMIF_EX_CTRL_DISABLE_DU_POS)
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306
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307
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Space Falcon <falcon@ivan.Harhan.ORG>
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308 #define F_MEMIF_DEBUG_FREEZE C_MEMIF_API_RHEA_CTRL_REG &= ~(C_MEMIF_API_RHEA_DEBUG <<C_MEMIF_API_RHEA_CTRL_DEBUG_POS)
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309
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310 /****************************************************************************
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311 * STRUCTURE DEFINITION
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312 ***************************************************************************/
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313
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314 typedef struct {
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315 /* CONF_CSx register configuration */
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316 SYS_UWORD8 d_ws;
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317 SYS_UWORD8 d_dvs;
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318 SYS_UWORD8 d_we;
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319 SYS_UWORD8 d_dc;
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320 SYS_UWORD8 d_rodc;
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321 SYS_UWORD8 d_wrdc;
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322 SYS_UWORD8 d_wws;
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323
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324 /* EXWS_CSx register configuration */
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325 SYS_UWORD8 d_pme;
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326 SYS_UWORD8 d_pms;
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327 SYS_UWORD8 d_pmws;
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328 SYS_UWORD8 d_wrws;
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329
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330 /* DCCTRL_CSx register configuration */
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331 SYS_UWORD8 d_dcecs0;
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332 SYS_UWORD8 d_dcecs1;
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333 SYS_UWORD8 d_dcecs2;
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334 SYS_UWORD8 d_dcecs3;
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335 SYS_UWORD8 d_dcecs4;
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336 SYS_UWORD8 d_dcecs5;
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337
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338 } T_MEMIF_CS_CONFIG;
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339
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340
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341
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342 /****************************************************************************
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343 * PROTOTYPE DEFINITION
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344 ***************************************************************************/
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345
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346 void f_memif_init_cs(SYS_UWORD8 d_cs, T_MEMIF_CS_CONFIG *p_cs_config);
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347
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348 void f_memif_init_api_rhea_ctrl(SYS_UWORD8 d_adap0,
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349 SYS_UWORD8 d_adap1,
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350 SYS_UWORD8 d_adap_api,
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351 SYS_UWORD8 d_debug);
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352
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
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353 void f_memif_du_enable(void);
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354
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Space Falcon <falcon@ivan.Harhan.ORG>
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355 void f_memif_du_disable(void);
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356
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357 void f_memif_extended_page_mode_enable(void);
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358
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
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359 void f_memif_shared_sram_allocation(SYS_UWORD16 d_allocation_cfg);
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360
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
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361 void f_memif_cs_mode(SYS_UWORD16 d_cs_mode_cfg);
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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362
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
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diff changeset
363 void f_memif_debug_freeze(void);
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
364
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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365 #endif /* (CHIPSET == 12) */
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
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366
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
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367 #endif /* __SYS_MEMIF_H__ */