FreeCalypso > hg > tcs211-l1-reconst

annotate chipsetsw/layer1/dyn_dwl_include/l1_dyn_dwl_defty.h @ 272:82a9407a75ce

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l1audio_sync.c: l1s_melody0_manager() reconstructed
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 13 Mar 2017 06:24:15 +0000
parents 13c360a4885f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1_DYN_DWL_DEFTY.H
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4 *
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5 * Filename l1_dyn_dwl_defty.h
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6 * Copyright 2004 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9 #if(L1_DYN_DSP_DWNLD==1)
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10
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11 #ifndef _L1_DYN_DWL_DEFTY_H_
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12 #define _L1_DYN_DWL_DEFTY_H_
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13
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14 #include "l1_dyn_dwl_const.h"
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15
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16 /***************************************************************************************/
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17 /* Dynamic download L1A structure to store dynamic download L1A global variables */
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18 /***************************************************************************************/
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19 typedef struct
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20 {
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21 UWORD32 signal_code_vect[MAX_NUM_OF_PATCH_IDS];
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22 UWORD32 num_of_elem;
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23 }T_FIFO_DYN_DWNLD ;
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24 typedef struct
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25 {
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26 UWORD8 state;
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27 UWORD16 num_patches_installed;
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28 UWORD16 patch_id[MAX_NUM_OF_PATCH_IDS];
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29 UWORD16 num_of_elem_to_copy;
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30 UWORD16 next_patch_id[MAX_NUM_OF_PATCH_IDS];
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13c360a4885f starting to compile l1_dyn_dwl_afunc.c
Mychaela Falconia <falcon@ivan.Harhan.ORG>
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31 BOOL semaphore_vect[MAX_NUM_OF_SEMAPHORES];
0
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32 BOOL melody0_E2_flag_activated;
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33 BOOL melody1_E2_flag_activated;
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34 UWORD16 dsp_trace_level_copy;
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35 BOOL trace_flag_blocked;
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36 UWORD16 num_of_primitives;
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37 BOOL dedicated_stop_flag;
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38 T_FIFO_DYN_DWNLD waiting_patch_fifo;
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39 }T_L1A_DYN_DWNLD_GLOBAL;
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40
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41 /***************************************************************************************/
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42 /* Dynamic DSP L1A-L1S structure... */
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43 /***************************************************************************************/
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44 typedef struct
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45 {
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46 BOOL start;
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47 BOOL stop;
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48 } T_DYN_DWNLD_TASK_COMMAND;
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49
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50 /***************************************************************************************/
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51 /* Dynamic DSP download HISR - L1A structure... */
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52 /***************************************************************************************/
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53 typedef struct
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54 {
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55 BOOL restart;
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56 } T_DYN_DWNLD_HISR_COMMAND;
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57
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58 typedef struct
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59 {
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60 UWORD16 num_of_elem;
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61 UWORD32 address[MAX_NUM_OF_PATCH_IDS];
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62 } T_DYN_DWNLD_HISR_UN_PARAM;
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63
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64 typedef struct
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65 {
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66 UWORD32 start_MCU_copy_address[MAX_NUM_OF_PATCH_IDS];
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67 UWORD16 size_of_dwnld_area;
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68 UWORD16 start_of_dwnld_area;
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69 UWORD16 num_of_elem;
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70 UWORD32 address_to_install[MAX_NUM_OF_PATCH_IDS];
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71 UWORD16 crc[MAX_NUM_OF_PATCH_IDS];
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72 UWORD16 size_array[MAX_NUM_OF_PATCH_IDS];
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73 }T_DYN_DWNLD_HISR_CPY_PARAM;
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74
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75 typedef struct
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76 {
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77 T_DYN_DWNLD_HISR_COMMAND command;
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78 T_DYN_DWNLD_HISR_UN_PARAM uninstall_parameters;
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79 T_DYN_DWNLD_HISR_CPY_PARAM copy_parameters;
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80 } T_L1A_DYN_DWNLD_HISR_COM;
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81
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82 /***************************************************************************************/
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83 /* Dynamic download HISR structure to store dynamic download HISR global variables */
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84 /***************************************************************************************/
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85
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86 typedef struct
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87 {
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88 UWORD8 state;
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89 BOOL running;
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90 UWORD16 uninstall_counter;
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91 UWORD16 patch_ids_counter;
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92 UWORD32 running_source_pointer;
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93 UWORD16 tmp_patch_size;
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94 } T_L1_DYN_DWNLD_API_HISR;
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95
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96 /***************************************************************************************/
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97 /* Dynamic Download MCU-DSP API */
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98 /***************************************************************************************/
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99 typedef struct
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100 {
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101 API d_api_dwl_download_ctrl;
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102 API d_api_dwl_error_code;
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103 API d_api_dwl_function_address[2];
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104 API d_api_dwl_crc;
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105 API d_api_dwl_size;
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106 API d_api_dwl_write_pointer;
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107 } T_DYN_DWNLD_MCU_DSP;
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108
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109 typedef struct
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110 {
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111 UWORD32 primitive;
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112 UWORD16 msg_id;
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113 }T_SIGNAL_PATCH;
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114
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115 #define GPRS_PATCH 0
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116 #define AMR_SCH_PATCH 1
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117 #define TTY_PATCH 2
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118 #define AMR_MMS_PATCH 3
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119 #define E2_PATCH 4
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120
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121
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122 #define DEDI_STATE_MACHINE 0
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123 #define TTY_STATE_MACHINE 1
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124 #define E2_STATE_MACHINE 2
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125 #define VOICE_MEMO_AMR_SM 3
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126 #define VOICE_PLAY_AMR_SM 4
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127 #define SPEECH_RECO_SM 5
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128
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129 #endif // _L1_DYN_DWL_DEFTY_H_
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130 #endif // L1_DYN_DSP_DWNLD
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131