FreeCalypso > hg > tcs211-l1-reconst

annotate chipsetsw/drivers/drv_core/drv_core.mak @ 146:a4adf4399559

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l1_sync.c: l1s_task_scheduler_process() reconstructed
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sun, 15 May 2016 19:19:33 +0000
parents 509db1a7b7b8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 #
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2 # Makefile for basic drivers (ARM compiler)
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3 #
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4 # Copyright (c) Texas Instruments 2002
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5 #
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6 # Author: Laurent Sollier
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7 # Date : 17 May 2002
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8
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9 # Compilation flags
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10 DRVC_DBG := $(NODBG) # Debug symbolic option
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11
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12 DRIVERS_FLAGS := $(DRVC_DBG) -mn $(INL) $(16INST) -o $(ALGN) $(CFLAGSDRIVERS)
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13 CFLAGS32 := $(DRVC_DBG) $(INL) -o $(ALGN) $(CFLAGSDRIVERS)
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14
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15 WIN_DRIVERS_FLAGS := $($(TP)CFLAGS) $(CFLAGSDRIVERS)
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16 WIN_CFLAGS32 := $($(TP)CFLAGS) $(CFLAGSDRIVERS)
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17
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18 #For ABB
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19 ABB_FLAGS := $(DRVC_DBG) $(16INST) -mn $(CFLAGSDRIVERS)
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20
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21 ifeq ($(OP_L1_STANDALONE), 0)
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22 ifeq ($(SRVC),0)
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23 ABB_FLAGS += -dIDS=0
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24 else
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25 ABB_FLAGS += -dIDS=1
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26 endif
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27 endif
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28
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29 # Libraries definition
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30 DRIVER_FLASH := $(OUT_LIB_DIR)/drivers_flash.lib
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31 DRIVER_INT_RAM := $(OUT_LIB_DIR)/drivers_int_ram.lib
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32 NIQ32_INT_RAM := $(OUT_LIB_DIR)/niq32_int_ram.lib
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33 LIB_ABB := $(OUT_LIB_DIR)/abb.lib
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34 CFG_LIBS += $(DRIVER_FLASH) $(DRIVER_INT_RAM) $(NIQ32_INT_RAM) $(LIB_ABB)
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35
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36 # Source definition
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37 SRC_DRIVER_FLASH += $(DRIVERS_CORE_DIR)/dsp_dwnld/leadapi.c \
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38 $(DRIVERS_CORE_DIR)/inth/niq.c \
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39 $(DRIVERS_CORE_DIR)/uart/uart.c \
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40 $(DRIVERS_CORE_DIR)/inth/inth.c \
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41 $(DRIVERS_CORE_DIR)/timer/timer.c \
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42 $(DRIVERS_CORE_DIR)/timer/timer1.c \
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43 $(DRIVERS_CORE_DIR)/timer/timer2.c \
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44 $(DRIVERS_CORE_DIR)/timer/timer_sec.c \
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45 $(DRIVERS_CORE_DIR)/security/certificate.c
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46
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47 ifeq ($(OP_L1_STANDALONE), 1)
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48 SRC_DRIVER_FLASH += $(DRIVERS_CORE_DIR)/uart/serialswitch_core.c
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49 endif
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50
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51 SRC_ABB_CORE += $(DRIVERS_CORE_DIR)/spi/spi_drv.c \
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52 $(DRIVERS_CORE_DIR)/abb/abb.c \
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53 $(DRIVERS_CORE_DIR)/abb/abb_core_inth.c
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54
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55 ifeq ($(CHIPSET),12)
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56 SRC_DRIVER_FLASH += $(DRIVERS_CORE_DIR)/dma/sys_dma.c \
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57 $(DRIVERS_CORE_DIR)/dma/sys_dma_it.c \
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58 $(DRIVERS_CORE_DIR)/inth/sys_inth.c \
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59 $(DRIVERS_CORE_DIR)/inth/sys_inth32.c \
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60 $(DRIVERS_CORE_DIR)/memif/sys_memif.c
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61 endif
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62
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63 ifeq ($(CHIPSET),12)
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64 SRC_ASM_DRIVER_INT_RAM += $(DRIVERS_CORE_DIR)/clkm/sys_wait_clkm.s
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65 endif
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66
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67 ifeq ($(findstring 1,$(TI_PROFILER) $(TI_NUC_MONITOR)),1)
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68 SRC_NIQ32_INT_RAM += $(DRIVERS_CORE_DIR)/inth/niq32.c
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69 else
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70 SRC_DRIVER_FLASH += $(DRIVERS_CORE_DIR)/inth/niq32.c
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71 endif
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72
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73 ifeq ($(BOARD),34)
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74 SRC_DRIVER_INT_RAM += $(DRIVERS_CORE_DIR)/clkm/clkm.c \
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75 $(DRIVERS_CORE_DIR)/armio/armio.c
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76 else
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77 ifeq ($(BOARD),35)
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78 SRC_DRIVER_INT_RAM += $(DRIVERS_CORE_DIR)/clkm/clkm.c \
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79 $(DRIVERS_CORE_DIR)/armio/armio.c
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80 else
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81 SRC_DRIVER_FLASH += $(DRIVERS_CORE_DIR)/clkm/clkm.c \
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82 $(DRIVERS_CORE_DIR)/armio/armio.c
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83 endif
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84 endif
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85
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86 # Objects definition
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87 OBJ_DRIVER_FLASH := $(patsubst ../%.c,$(TEMPORARY_FILE_DIR)/%.obj,$(filter %.c,$(SRC_DRIVER_FLASH)))
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88 CFG_OBJS += $(OBJ_DRIVER_FLASH)
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89 CFG_DEPS += $(OBJ_DRIVER_FLASH:.obj=.d)
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90
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91 OBJ_DRIVER_INT_RAM := $(patsubst ../%.c,$(TEMPORARY_FILE_DIR)/%.obj,$(filter %.c,$(SRC_DRIVER_INT_RAM)))
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92 OBJ_ASM_DRIVER_INT_RAM := $(patsubst ../%.s,$(TEMPORARY_FILE_DIR)/%.obj,$(filter %.s,$(SRC_ASM_DRIVER_INT_RAM)))
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93 CFG_OBJS += $(OBJ_DRIVER_INT_RAM) $(OBJ_ASM_DRIVER_INT_RAM)
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94 CFG_DEPS += $(OBJ_DRIVER_INT_RAM:.obj=.d)
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95
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96 OBJ_NIQ32_INT_RAM:= $(patsubst ../%.c,$(TEMPORARY_FILE_DIR)/%.obj,$(filter %.c,$(SRC_NIQ32_INT_RAM)))
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97 CFG_OBJS += $(OBJ_NIQ_32_INT_RAM)
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98 CFG_DEPS += $(OBJ_NIQ_32_INT_RAM:.obj=.d)
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99
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100 OBJ_ABB_CORE:= $(patsubst ../%.c,$(TEMPORARY_FILE_DIR)/%.obj,$(filter %.c,$(SRC_ABB_CORE)))
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101 CFG_OBJS += $(OBJ_ABB_CORE)
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102 CFG_DEPS += $(OBJ_ABB_CORE:.obj=.d)
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103
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104 #Sources that needs to be compiled into 32 bit state code
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105 #They still must be added to the SRC_DRIVER_FLASH due to generation of libraries
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106 SRC32 += $(DRIVERS_CORE_DIR)/inth/niq32.c $(DRIVERS_CORE_DIR)/inth/sys_inth32.c
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107 OBJ32 := $(patsubst ../%.c,$(TEMPORARY_FILE_DIR)/%.obj,$(filter %.c,$(SRC32)))
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108
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109
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110 ######## LIBRARIES #############
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111 $(DRIVER_FLASH) : $(OBJ_DRIVER_FLASH) $(OBJ_ABB_CORE)
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112 $(MKDIR) $(dir $@)
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113 $($(TP)LINKER) $($(TP)LFLAGS) $($(TP)LOUTOUT_FLAG)$@ $^
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114
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115 $(DRIVER_INT_RAM) : $(OBJ_DRIVER_INT_RAM) $(OBJ_ASM_DRIVER_INT_RAM)
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116 $(MKDIR) $(dir $@)
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117 $($(TP)LINKER) $($(TP)LFLAGS) $($(TP)LOUTOUT_FLAG)$@ $^
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118
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119 $(NIQ32_INT_RAM) : $(OBJ_NIQ32_INT_RAM)
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120 $(MKDIR) $(dir $@)
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121 $($(TP)LINKER) $($(TP)LFLAGS) $($(TP)LOUTOUT_FLAG)$@ $^
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122
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123 ######## OBJECTS #############
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124 $(filter-out $(OBJ32), $(OBJ_DRIVER_FLASH)) : $(TEMPORARY_FILE_DIR)/%.obj: ../%.c
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125 $($(TP)COMPILER) $($(TP)DRIVERS_FLAGS) $($(TP)COUTPUT_FLAG)$(@D)/ $<
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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126
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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127 $(filter-out $(OBJ32), $(OBJ_DRIVER_INT_RAM)) : $(TEMPORARY_FILE_DIR)/%.obj: ../%.c
509db1a7b7b8 initial import: leo2moko-r1
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parents:
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128 $($(TP)COMPILER) $($(TP)DRIVERS_FLAGS) $($(TP)COUTPUT_FLAG)$(@D)/ $<
509db1a7b7b8 initial import: leo2moko-r1
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parents:
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129
509db1a7b7b8 initial import: leo2moko-r1
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parents:
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130 $(OBJ32) : $(TEMPORARY_FILE_DIR)/%.obj: ../%.c
509db1a7b7b8 initial import: leo2moko-r1
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parents:
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131 $($(TP)COMPILER) $($(TP)CFLAGS32) $($(TP)COUTPUT_FLAG)$(@D)/ $<
509db1a7b7b8 initial import: leo2moko-r1
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parents:
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132
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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133 $(OBJ_ABB_CORE) : $(TEMPORARY_FILE_DIR)/%.obj: ../%.c
509db1a7b7b8 initial import: leo2moko-r1
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parents:
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134 $($(TP)COMPILER) $($(TP)ABB_FLAGS) $($(TP)COUTPUT_FLAG)$(@D)/ $<
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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135
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
136 # WARNING : sys_wait_clkm.s is compiled thanks to default rule specified in top level makefile