annotate chipsetsw/layer1/tpu_drivers/source/tpudrv.c @ 289:f2f7f4dff6d7

STATUS: analysis complete
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 19 Mar 2017 23:41:49 +0000
parents c933041d07bd
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename tpudrv.c
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8 /*
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9 * TPUDRV.C
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10 *
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11 * TPU driver for Pole Star
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12 *
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13 *
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14 * Copyright (c) Texas Instruments 1996
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15 *
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16 */
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17
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18 #include "l1_macro.h"
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19 #include "iq.h"
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20 #include "l1_confg.h"
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21 #include "l1_const.h"
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22 #include "l1_types.h"
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23
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24 #if (AUDIO_TASK == 1)
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25 #include "l1audio_const.h"
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26 #include "l1audio_cust.h"
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27 #include "l1audio_defty.h"
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28 #endif
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29
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30 #if (L1_GTT == 1)
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31 #include "l1gtt_const.h"
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32 #include "l1gtt_defty.h"
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33 #endif
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34
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35 #if (L1_MIDI == 1)
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36 #include "l1midi_defty.h"
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37 #endif
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38
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39 #include "sys_types.h"
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40
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41 #if TESTMODE
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42 #include "l1tm_defty.h"
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43 #endif
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44
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45 #if (L1_MP3 == 1)
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46 #include "l1mp3_defty.h"
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47 #endif
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48
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49 #if (L1_MIDI == 1)
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50 #include "l1midi_defty.h"
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51 #endif
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52
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53 #if (L1_AAC == 1)
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54 #include "l1aac_defty.h"
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55 #endif
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56 #include "l1_defty.h"
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57 #include "tpudrv.h"
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58 #include "sys_types.h"
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59 #include "clkm.h"
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60 #include "l1_time.h"
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61 #include "l1_varex.h"
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62 #include "l1_trace.h"
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63
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64 #if (L1_MADC_ON == 1)
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65 #if (RF_FAM == 61)
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66 #include "drp_api.h"
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67 #include "l1_rf61.h"
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68 #include "drp_drive.h"
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69 #include "tpudrv61.h"
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70 extern T_DRP_REGS_STR *drp_regs;
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71 #endif
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72 #endif //L1_MADC_ON
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73
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74 /* RFTime environment */
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75 #if defined (HOST_TEST)
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76 #include "hostmacros.h"
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77 #endif
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78
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79
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80 /*
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81 * VEGA and OMEGA receive windows - Defined in Customer-specific file
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82 */
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83
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84 extern UWORD32 debug_tpu;
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85
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86 #if ( OP_WCP == 1 ) && ( OP_L1_STANDALONE != 1 )
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87 // WCS Patch : ADC during RX or TX
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88 extern inline void GC_SetAdcInfo(unsigned char bTxBasedAdc);
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89 #endif
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90
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91 /*
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92 * Global Variables
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93 */
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94 // GSM1.5 : TPU MEMORY is 16-bit instead of 32 in Gemini/Polxx
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95 //------------------------------------------------------------
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96 SYS_UWORD16 *TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
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97
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98
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99 /*--------------------------------------------------------------*/
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100 /* TPU_Reset : Reset the TPU */
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101 /*--------------------------------------------------------------*/
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102 /* Parameters : on/off(1/0) */
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103 /* Return : none */
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104 /* Functionality : ) Reset the TPU */
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105 /*--------------------------------------------------------------*/
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106 void TPU_Reset(SYS_UWORD16 on)
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107 {
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108 if (on)
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109 {
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110 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_RESET;
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111 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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112 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
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113 }
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114 else
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115 {
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116 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_RESET;
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117 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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118 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
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119 }
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120 }
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121
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122 /*--------------------------------------------------------------*/
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123 /* TSP_Reset : Reset the TSP */
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124 /*--------------------------------------------------------------*/
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125 /* Parameters : on/off(1/0) */
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126 /* Return : none */
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127 /* Functionality : ) Reset the TSP */
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128 /*--------------------------------------------------------------*/
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129 void TSP_Reset(SYS_UWORD16 on)
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diff changeset
130 {
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diff changeset
131 if (on)
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diff changeset
132 {
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133 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TSP_CTRL_RESET;
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134 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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135 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
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diff changeset
136 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
137 else
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
138 {
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diff changeset
139 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TSP_CTRL_RESET;
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140 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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diff changeset
141 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
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diff changeset
142 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
143 }
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diff changeset
144
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diff changeset
145 /*--------------------------------------------------------------*/
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diff changeset
146 /* TPU_SPIReset : Reset the SPI of the TPU */
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diff changeset
147 /*--------------------------------------------------------------*/
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diff changeset
148 /* Parameters : on/off(1/0) */
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149 /* Return : none */
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150 /* Functionality : ) the SPI of the TPU */
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diff changeset
151 /*--------------------------------------------------------------*/
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diff changeset
152
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153 void TPU_SPIReset(SYS_UWORD16 on)
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154 {
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
155 if (on)
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
156 {
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157 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_SPI_RST;
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158 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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Mychaela Falconia <falcon@freecalypso.org>
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159 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
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diff changeset
160 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
161 else
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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162 {
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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163 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_SPI_RST;
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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164 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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diff changeset
165 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
166 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
167 }
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
168
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diff changeset
169 /*--------------------------------------------------------------*/
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diff changeset
170 /* TPU_ClkEnable : */
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diff changeset
171 /*--------------------------------------------------------------*/
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diff changeset
172 /* Parameters : on/off(1/0) */
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173 /* Return : none */
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diff changeset
174 /* Functionality : Enable the TPU clock */
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diff changeset
175 /*--------------------------------------------------------------*/
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diff changeset
176
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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177 void TPU_ClkEnable(SYS_UWORD16 on)
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diff changeset
178 {
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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179 if (on)
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180 {
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181 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_CLK_EN;
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diff changeset
182 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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diff changeset
183 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
184 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
185 else
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
186 {
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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187 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_CLK_EN;
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
188 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
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diff changeset
189 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
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diff changeset
190 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
191 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
192
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
193 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
194 /* TPU_Frame_ItOn : */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
195 /*--------------------------------------------------------------*/
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diff changeset
196 /* Parameters : bit of it to enable */
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diff changeset
197 /* Return : none */
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diff changeset
198 /* Functionality : Enable frame it */
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diff changeset
199 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
200
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
201 /*-----------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
202 /* Warning read modify write access to TPU_INT_CTRL register */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
203 /* may generate problems using Hyperion. */
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diff changeset
204 /*-----------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
205
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
206 void TPU_FrameItOn(SYS_UWORD16 it)
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
207 {
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
208 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) &= ~it;
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
209 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
210
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
211 void TPU_FrameItEnable(void)
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
212 {
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
213 #if W_A_ITFORCE
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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214 (*(volatile SYS_UWORD16 *)TPU_INT_CTRL) |= TPU_INT_ITD_F;
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diff changeset
215 #else
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
216 // enable IT_DSP generation on next frame
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
217 // reset by DSP when IT occurs
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
218 (*(volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_D_ENBL;
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
219 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
220 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL));
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
221 #endif
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
222 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
223
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
224 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
225 /* TPU_check_IT_DSP : */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
226 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
227 /* Parameters : none */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
228 /* Return : none */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
229 /* Functionality : check if an IT DSP still pending */
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diff changeset
230 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
231 BOOL TPU_check_IT_DSP(void)
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
232 { // return TRUE if an IT DSP still pending.
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
233 return( (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL) == TPU_CTRL_D_ENBL));
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
234 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
235
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
236 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
237 /* TPU_DisableAllIt : */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
238 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
239 /* Parameters : none */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
240 /* Return : none */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
241 /* Functionality : Disabl all it */
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
242 /*--------------------------------------------------------------*/
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
243 void TPU_DisableAllIt()
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
244 {
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
245 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) |= TPU_INT_ITF_M | TPU_INT_ITP_M | TPU_INT_ITD_M;
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
246
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
247 }
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
248
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
249
7b2986d6f272 tpudrv.c: initial import of LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
250 /*
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
251 * TP_Program
7b2986d6f272 tpudrv.c: initial import of LoCosto source
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diff changeset
252 *
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253 * Write a null-terminated scenario into TPU memory at a given start address
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254 * (Do not write terminating 0)
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255 *
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256 */
189
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257 void TP_Program(const SYS_UWORD16 *src)
187
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258 {
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259 /* Write TPU instructions until SLEEP */
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260 while (*src)
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261 {
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262 *TP_Ptr++ = *src++;
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263 }
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264 }
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265
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266
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267 void TP_Reset(SYS_UWORD16 on)
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268 {
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269 if (on) {
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270 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= (TPU_CTRL_RESET | TSP_CTRL_RESET);
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271 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
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272 }
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273 else {
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274 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~(TPU_CTRL_RESET | TSP_CTRL_RESET);
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275 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
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276 }
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277 }
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278
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279 void TP_Enable(SYS_UWORD16 on)
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280 {
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281 if(on)
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282 {
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283 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_T_ENBL;
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284
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285 // Some time shall be wait before leaving the function to ensure that bit has been taken
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286 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
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287 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
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288 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
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289 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
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290 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
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291 }
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292 else
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293 {
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294 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_T_ENBL;
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295 // Some time shall be wait before leaving the function to ensure that bit has been taken
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296 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
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297 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
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298 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
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299 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
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300 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
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301 }
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302 }
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303
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304
188
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305 #if 0 /* FreeCalypso: function not present in TCS211 */
187
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306 /*-----------------------------------------------------------------------*/
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307 /* Function name: TPU_wait_idle */
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308 /*-----------------------------------------------------------------------*/
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309 /* */
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310 /* Parameters: None */
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311 /* */
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312 /* Return: None */
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313 /* */
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314 /*-----------------------------------------------------------------------*/
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315 /* Description: Wait until TPU scenario execution is complete */
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316 /* */
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317 /*-----------------------------------------------------------------------*/
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318 void TPU_wait_idle(void)
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319 {
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320 while( ((*(volatile SYS_UWORD16 *) (TPU_CTRL)) & TPU_CTRL_TPU_IDLE) == TPU_CTRL_TPU_IDLE)
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321 {
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322 wait_ARM_cycles(convert_nanosec_to_cycles(3000));
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323 }
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324 }
188
81064b792cc8 tpudrv.c: passes compilation, started disasm diffing
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diff changeset
325 #endif
187
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diff changeset
326
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diff changeset
327
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328 /*
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329 * l1dmacro_idle
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330 *
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331 * Write SLEEP instruction, start TPU and reset pointer
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332 */
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333 void l1dmacro_idle (void)
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334 {
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335 *TP_Ptr++ = TPU_SLEEP;
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diff changeset
336
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diff changeset
337 /* start TPU */
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338 TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
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339 TP_Enable(1);
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diff changeset
340 }
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diff changeset
341
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diff changeset
342 /*
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343 * l1dmacro_offset
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diff changeset
344 *
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diff changeset
345 * Set OFFSET register
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346 *
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347 */
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348 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time)
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diff changeset
349 {
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350 // WARNING: 'relative time' and 'offset_value' must always be comprised
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diff changeset
351 // between 0 and TPU_CLOCK_RANGE !!!
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diff changeset
352
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diff changeset
353 if (relative_time != IMM) // IMM indicates to set directly without AT
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diff changeset
354 {
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355 *TP_Ptr++ = TPU_FAT(relative_time);
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diff changeset
356 }
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357 *TP_Ptr++ = TPU_OFFSET(offset_value);
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diff changeset
358 }
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diff changeset
359
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diff changeset
360 /*
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361 * l1dmacro_synchro
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diff changeset
362 *
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diff changeset
363 * Set synchro register
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diff changeset
364 */
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diff changeset
365 void l1dmacro_synchro (UWORD32 when, UWORD32 value)
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diff changeset
366 {
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367 // WARNING: 'when' must always be comprised between 0 and TPU_CLOCK_RANGE !!!
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diff changeset
368 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
190
c933041d07bd tpudrv.c fully reconstructed, matches TCS211 object
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diff changeset
369 trace_fct(CST_L1DMACRO_SYNCHRO, -1);
187
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diff changeset
370 #endif
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diff changeset
371
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diff changeset
372 if (value != IMM) // IMM indicates to set directly without AT
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diff changeset
373 {
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diff changeset
374 *TP_Ptr++ = TPU_FAT(when);
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diff changeset
375 }
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diff changeset
376
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diff changeset
377 *TP_Ptr++ = TPU_SYNC(value);
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diff changeset
378 l1s.tpu_offset_hw = value; // memorize the offset set into the TPU.
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379 }
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380
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381
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382 /*
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383 * l1dmacro_adc_read
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384 *
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385 */
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386 void l1dmacro_adc_read_rx(void)
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387 {
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388
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389 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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390 // TSP needs to be configured in order to send serially to Omega
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391
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392 // *TP_Ptr++ = TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE); // Clock configuration
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393 *TP_Ptr++ = TPU_WAIT (5);
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394 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
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395 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,STARTADC); // Load data to send
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396 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
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397 *TP_Ptr++ = TPU_WAIT (5);
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398 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,0x00);
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399 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
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400
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401 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
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402 #if (GSM_IDLE_RAM == 0)
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403 l1_trace_ADC(0);
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404 #else
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405 l1_trace_ADC_intram(0);
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406 #endif
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407 #endif
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408 #endif
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409
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410 #if (L1_MADC_ON == 1)
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411 #if (ANLG_FAM == 11)
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412
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413 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
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414 #if (GSM_IDLE_RAM == 0)
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415 l1_trace_ADC(0);
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416 #else
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417 l1_trace_ADC_intram(0);
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418 #endif
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419 #endif
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420 #endif
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421
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422 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
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423 // WCS patch: ADC during RX
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424 GC_SetAdcInfo(0);
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425 #endif
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426 #endif
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427 }
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428
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429
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430 #if (CODE_VERSION != SIMULATION)
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431 #if (L1_MADC_ON ==1)
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432 /*
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433 * l1dmacro_adc_read_rx_cs_mode0
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434 *
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435 * Purpose:
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436 * ======
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437 * MADC is not enabled during CS_MODE0 periodically. MADC is enabled in CS_MODE0
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438 * when Layer 1 receives MPHC_RXLEV_REQ from L23. However in CS_MODE0, MPHC_RXLEV_REQ
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439 * is not received periodically. In case network is not found, the period between 2 MPHC_RXLEV_REQ
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440 * increases and can be as high as 360 seconds (Maximum Value)
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441 * This can result in battery related issues like phone powering off without MMI indication.
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442 */
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443
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444
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445 void l1dmacro_adc_read_rx_cs_mode0(void)
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446 {
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447 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC);
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448 *TP_Ptr++ = TPU_WAIT (2);
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449 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0);
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450
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451 #if (L1_MADC_ON == 1)
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452 #if (ANLG_FAM == 11)
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453
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454 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
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455 #if (GSM_IDLE_RAM == 0)
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456 l1_trace_ADC(0);
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457 #else
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458 l1_trace_ADC_intram(0);
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459 #endif
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diff changeset
460 #endif
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461 #endif
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462
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463 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
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464 // WCS patch: ADC during RX
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465 GC_SetAdcInfo(0);
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466 #endif
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467 #endif
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diff changeset
468 }
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diff changeset
469
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diff changeset
470
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471 #endif //If MADC is enabled
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472 #endif //If Not Simulation
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diff changeset
473
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474 /*
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475 * l1dmacro_adc_read_tx
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476 *
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diff changeset
477 */
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diff changeset
478
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diff changeset
479
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diff changeset
480 #if (ANLG_FAM != 11)
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diff changeset
481 void l1dmacro_adc_read_tx(UWORD32 when)
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diff changeset
482 #else
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483 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
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484 #endif
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diff changeset
485 {
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diff changeset
486
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diff changeset
487 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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diff changeset
488
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diff changeset
489 *TP_Ptr++ = TPU_FAT (when);
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490 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
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diff changeset
491 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, STARTADC|BULON|BULENA); // Load data to send
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diff changeset
492 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
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diff changeset
493 *TP_Ptr++ = TPU_WAIT (5);
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diff changeset
494 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, BULON|BULENA);
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diff changeset
495 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
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diff changeset
496
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diff changeset
497 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
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diff changeset
498 l1_trace_ADC(1);
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diff changeset
499 #endif
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diff changeset
500 #endif
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diff changeset
501
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diff changeset
502 #if (L1_MADC_ON == 1)
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503 #if (ANLG_FAM == 11)
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504 *TP_Ptr++ = TPU_FAT (when);
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505 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
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506 *TP_Ptr++ = TPU_WAIT (2);
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507 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
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508
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509 #if 1 // TEMP MEASUREMENT - uncomment and test after MADC
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510 #if (RF_FAM == 61)
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511 *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((START_SCRIPT(DRP_TEMP_CONV))>>8) & 0xFF); \
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512 *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (START_SCRIPT(DRP_TEMP_CONV)) & 0xFF); \
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513 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, (((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)>>8) & 0xFF)); \
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514 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)) & 0xFF); \
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515 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x01); \
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516 //TEMP_MEAS: Call TEMP Conv Script in DRP
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517 //MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TEMP_CONV),(UWORD16)(&drp_regs->SCRIPT_STARTL));
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518 #endif
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519
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520 #endif
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521
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522 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
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523 l1_trace_ADC(1);
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524 #endif
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525
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526 #endif
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527 #endif //L1_MADC_ON
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528
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529 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
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530 // WCS patch: ADC during TX
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531 GC_SetAdcInfo(1);
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532 #endif
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533
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534
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535 }
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536
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diff changeset
537
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538 /*
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539 #if (RF_FAM == 61)
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540
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541 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
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542 {
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543 int i;
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544
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545 *TP_Ptr++ = TPU_FAT (when);
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546 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
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diff changeset
547 *TP_Ptr++ = TPU_WAIT (2);
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548 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
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549
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550 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
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diff changeset
551 l1_trace_ADC(1);
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552 #endif
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553
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diff changeset
554
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555 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
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diff changeset
556 // WCS patch: ADC during TX
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557 GC_SetAdcInfo(1);
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558 #endif
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559 }
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diff changeset
560
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561 #endif
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diff changeset
562 */
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563
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564 /*
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565 * l1dmacro_set_frame_it
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566 *
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567 */
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diff changeset
568 void l1dmacro_set_frame_it(void)
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569 {
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570 TPU_FrameItEnable();
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571 }