FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cust0/l1_rf12.c @ 204:2d691e51d678

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l1_cust.c: passes compilation
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 08 Jun 2016 05:59:55 +0000
parents 5dbf46894dab
children cac3ce96591e
comparison
equal deleted inserted replaced
203:5dbf46894dab 204:2d691e51d678
1 #if (OP_L1_STANDALONE == 1) 1 #if (OP_L1_STANDALONE == 1)
2 // Define the correct enumeration of PA. Consult tpudrv12.h for the enumeration. 2 // Define the correct enumeration of PA. Consult tpudrv12.h for the enumeration.
3 #if ((BOARD == 40) || (BOARD == 41) || (BOARD == 45)) // EvaRita + D-sample or EvaConso 3 #if ((BOARD == 40) || (BOARD == 41) || (BOARD == 45)) // EvaRita + D-sample or EvaConso
4 #define PA 3 4 #define RF_PA 3
5 #else 5 #else
6 #define PA 0 6 #define RF_PA 0
7 #endif 7 #endif
8 #else 8 #else
9 #include "rf.cfg" 9 #include "rf.cfg"
10 //#define PA 3 // Hitachi 10 //#define RF_PA 3 // Hitachi
11 #endif 11 #endif
12 12
13 T_RF rf = 13 T_RF rf =
14 { 14 {
15 RF_RITA_10, //RF revision 15 RF_RITA_10, //RF revision
460 { 100 , 0 } 460 { 100 , 0 }
461 } 461 }
462 }, 462 },
463 { //TX structure 463 { //TX structure
464 {// gsm900 T_LEVEL_TX 464 {// gsm900 T_LEVEL_TX
465 #if (PA == 3) // Hitachi 465 #if (RF_PA == 3) // Hitachi
466 {550, 0, 0}, // 0 466 {550, 0, 0}, // 0
467 {550, 0, 0}, // 1 467 {550, 0, 0}, // 1
468 {550, 0, 0}, // 2 468 {550, 0, 0}, // 2
469 {550, 0, 0}, // 3 469 {550, 0, 0}, // 3
470 {550, 0, 0}, // 4 470 {550, 0, 0}, // 4
530 { 67, 14, 0 }, // 31 530 { 67, 14, 0 }, // 31
531 #endif 531 #endif
532 }, 532 },
533 {// Channel Calibration Tables 533 {// Channel Calibration Tables
534 {// arfcn, tx_chan_cal 534 {// arfcn, tx_chan_cal
535 #if (PA == 3) // Hitachi 535 #if (RF_PA == 3) // Hitachi
536 { 21, 128 }, // Calibration Table 0 536 { 21, 128 }, // Calibration Table 0
537 { 41, 128 }, 537 { 41, 128 },
538 { 62, 128 }, 538 { 62, 128 },
539 { 82, 128 }, 539 { 82, 128 },
540 { 103, 128 }, 540 { 103, 128 },
583 { 885, 128 }, 583 { 885, 128 },
584 { 1023, 128 } 584 { 1023, 128 }
585 } 585 }
586 }, 586 },
587 { // GSM Power Ramp Values 587 { // GSM Power Ramp Values
588 #if (PA == 3) // Hitachi 588 #if (RF_PA == 3) // Hitachi
589 { 589 {
590 {// Ramp-Up #0 profile - Power Level 5 590 {// Ramp-Up #0 profile - Power Level 5
591 0,0,6,0,11,7,1,0,0,11,0,26,23,22,16,5 591 0,0,6,0,11,7,1,0,0,11,0,26,23,22,16,5
592 }, 592 },
593 {// Ramp-Down #0 profile 593 {// Ramp-Down #0 profile
805 { 100 , 0 } 805 { 100 , 0 }
806 } 806 }
807 }, 807 },
808 { //TX structure 808 { //TX structure
809 {// dcs1800 T_LEVEL_TX 809 {// dcs1800 T_LEVEL_TX
810 #if (PA == 3) // Hitachi 810 #if (RF_PA == 3) // Hitachi
811 {720, 0, 0}, // 0 Highest power 811 {720, 0, 0}, // 0 Highest power
812 {637, 1, 0}, // 1 812 {637, 1, 0}, // 1
813 {570, 2, 0}, // 2 813 {570, 2, 0}, // 2
814 {470, 3, 1}, // 3 814 {470, 3, 1}, // 3
815 {390, 4, 1}, // 4 815 {390, 4, 1}, // 4
915 { 870, 128 }, 915 { 870, 128 },
916 { 885, 128 } 916 { 885, 128 }
917 } 917 }
918 }, 918 },
919 { // DCS Power Ramp Values 919 { // DCS Power Ramp Values
920 #if (PA == 3) // Hitachi 920 #if (RF_PA == 3) // Hitachi
921 { 921 {
922 {// Ramp-Up #0 profile - Power Level 0 922 {// Ramp-Up #0 profile - Power Level 0
923 0,0,0,10,16,0,0,0,6,0,0,0,19,31,31,15 923 0,0,0,10,16,0,0,0,6,0,0,0,19,31,31,15
924 }, 924 },
925 {// Ramp-Down #0 profile 925 {// Ramp-Down #0 profile
1146 { 100 , 0 } 1146 { 100 , 0 }
1147 } 1147 }
1148 }, 1148 },
1149 { //TX structure 1149 { //TX structure
1150 {// gsm850 T_LEVEL_TX 1150 {// gsm850 T_LEVEL_TX
1151 #if (PA == 3) // Hitachi 1151 #if (RF_PA == 3) // Hitachi
1152 {560, 0, 0}, // 0 1152 {560, 0, 0}, // 0
1153 {560, 0, 0}, // 1 1153 {560, 0, 0}, // 1
1154 {560, 0, 0}, // 2 1154 {560, 0, 0}, // 2
1155 {560, 0, 0}, // 3 1155 {560, 0, 0}, // 3
1156 {560, 0, 0}, // 4 1156 {560, 0, 0}, // 4
1257 { 885, 128 }, 1257 { 885, 128 },
1258 { 1023, 128 } 1258 { 1023, 128 }
1259 } 1259 }
1260 }, 1260 },
1261 { // gsm850 Power Ramp Values 1261 { // gsm850 Power Ramp Values
1262 #if (PA == 3) // Hitachi 1262 #if (RF_PA == 3) // Hitachi
1263 { 1263 {
1264 {// Ramp-Up #0 profile - Power Level 5 1264 {// Ramp-Up #0 profile - Power Level 5
1265 8,0,0,0,0,0,6,0, 1265 8,0,0,0,0,0,6,0,
1266 0,6,18,29,23,21,17,0 1266 0,6,18,29,23,21,17,0
1267 }, 1267 },
1511 { 100 , 0 } 1511 { 100 , 0 }
1512 } 1512 }
1513 }, 1513 },
1514 { //TX structure 1514 { //TX structure
1515 {// pcs1900 T_LEVEL_TX 1515 {// pcs1900 T_LEVEL_TX
1516 #if (PA == 3) // Hitachi 1516 #if (RF_PA == 3) // Hitachi
1517 {915, 0, 0}, // 0 Highest power 1517 {915, 0, 0}, // 0 Highest power
1518 {715, 1, 0}, // 1 1518 {715, 1, 0}, // 1
1519 {570, 2, 0}, // 2 1519 {570, 2, 0}, // 2
1520 {465, 3, 0}, // 3 1520 {465, 3, 0}, // 3
1521 {390, 4, 0}, // 4 1521 {390, 4, 0}, // 4
1622 { 810, 128 }, 1622 { 810, 128 },
1623 { 810, 128 } 1623 { 810, 128 }
1624 } 1624 }
1625 }, 1625 },
1626 { // PCS Power Ramp Values 1626 { // PCS Power Ramp Values
1627 #if (PA == 3) // Hitachi 1627 #if (RF_PA == 3) // Hitachi
1628 { 1628 {
1629 {// Ramp-Up #0 profile - Power Level 0 1629 {// Ramp-Up #0 profile - Power Level 0
1630 0,0,0,0,6,2,0,1, 1630 0,0,0,0,6,2,0,1,
1631 5,4,12,31,31,25,10,1 1631 5,4,12,31,31,25,10,1
1632 }, 1632 },