FreeCalypso > hg > tcs211-l1-reconst
comparison chipsetsw/layer1/p_cfile/l1p_driv.c @ 317:3a2c43579200
l1p_driv.c: initial import from LoCosto source
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 04 Oct 2017 04:36:06 +0000 |
parents | 6814a6bced4f |
children | 08caa229dfa2 |
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316:ec71c9658110 | 317:3a2c43579200 |
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1 /* dummy C source file */ | 1 /************* Revision Controle System Header ************* |
2 * GSM Layer 1 software | |
3 * L1P_DRIVE.C | |
4 * | |
5 * Filename l1p_driv.c | |
6 * Copyright 2003 (C) Texas Instruments | |
7 * | |
8 ************* Revision Controle System Header *************/ | |
9 | |
10 #define L1P_DRIVE_C | |
11 | |
12 #include "l1_macro.h" | |
13 #include "l1_confg.h" | |
14 | |
15 #if L1_GPRS | |
16 #if (CODE_VERSION == SIMULATION) | |
17 #include <string.h> | |
18 #include "l1_types.h" | |
19 #include "sys_types.h" | |
20 #include "l1_const.h" | |
21 #include "l1_time.h" | |
22 #if TESTMODE | |
23 #include "l1tm_defty.h" | |
24 #endif | |
25 #if (AUDIO_TASK == 1) | |
26 #include "l1audio_const.h" | |
27 #include "l1audio_cust.h" | |
28 #include "l1audio_defty.h" | |
29 #endif | |
30 #if (L1_GTT == 1) | |
31 #include "l1gtt_const.h" | |
32 #include "l1gtt_defty.h" | |
33 #endif | |
34 #if (L1_MP3 == 1) | |
35 #include "l1mp3_defty.h" | |
36 #endif | |
37 #if (L1_MIDI == 1) | |
38 #include "l1midi_defty.h" | |
39 #endif | |
40 #include "l1_defty.h" | |
41 #include "l1_varex.h" | |
42 #include "cust_os.h" | |
43 #include "l1_msgty.h" | |
44 #if L2_L3_SIMUL | |
45 #include "hw_debug.h" | |
46 #endif | |
47 | |
48 #include "l1p_cons.h" | |
49 #include "l1p_msgt.h" | |
50 #include "l1p_deft.h" | |
51 #include "l1p_vare.h" | |
52 #include "l1p_tabs.h" | |
53 | |
54 #include "sim_cons.h" | |
55 #include "sim_def.h" | |
56 extern T_hw FAR hw; | |
57 #include "l1_proto.h" | |
58 | |
59 #else | |
60 | |
61 #include <string.h> | |
62 #include "l1_types.h" | |
63 #include "sys_types.h" | |
64 #include "l1_const.h" | |
65 #include "l1_time.h" | |
66 | |
67 #if TESTMODE | |
68 #include "l1tm_defty.h" | |
69 #endif | |
70 #if (AUDIO_TASK == 1) | |
71 #include "l1audio_const.h" | |
72 #include "l1audio_cust.h" | |
73 #include "l1audio_defty.h" | |
74 #endif | |
75 #if (L1_GTT == 1) | |
76 #include "l1gtt_const.h" | |
77 #include "l1gtt_defty.h" | |
78 #endif | |
79 #if (L1_MP3 == 1) | |
80 #include "l1mp3_defty.h" | |
81 #endif | |
82 #if (L1_MIDI == 1) | |
83 #include "l1midi_defty.h" | |
84 #endif | |
85 #include "l1_defty.h" | |
86 #include "l1_varex.h" | |
87 #include "cust_os.h" | |
88 #include "l1_msgty.h" | |
89 #if L2_L3_SIMUL | |
90 #include "hw_debug.h" | |
91 #endif | |
92 | |
93 #include "l1p_cons.h" | |
94 #include "l1p_msgt.h" | |
95 #include "l1p_deft.h" | |
96 #include "l1p_vare.h" | |
97 #include "l1p_tabs.h" | |
98 | |
99 #include "l1_proto.h" | |
100 #include "tpudrv.h" | |
101 | |
102 #endif | |
103 | |
104 #if(RF_FAM == 61) | |
105 #include "l1_rf61.h" | |
106 #include "tpudrv61.h" | |
107 #include "l1_ctl.h" | |
108 #endif | |
109 | |
110 /*-------------------------------------------------------*/ | |
111 /* Prototypes of external functions used in this file. */ | |
112 /*-------------------------------------------------------*/ | |
113 void l1dmacro_synchro (UWORD32 when, UWORD32 value); | |
114 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time); | |
115 void l1dmacro_afc (UWORD16 afc_value, UWORD8 win_id); | |
116 | |
117 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61) ) | |
118 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq | |
119 #if(REL99 && FF_PRF) | |
120 ,UWORD8 number_uplink_timeslot | |
121 #endif | |
122 ); | |
123 #endif | |
124 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq); | |
125 | |
126 BOOL l1ps_swap_iq_ul (UWORD16 radio_freq); | |
127 BOOL l1ps_swap_iq_dl (UWORD16 radio_freq); | |
128 #if (L1_MADC_ON == 1) | |
129 #if (RF_FAM == 61) | |
130 void l1pdmacro_rx_up (UWORD16 radio_freq,UWORD8 adc_active, UWORD8 csf_filter_choice | |
131 #if (NEW_SNR_THRESHOLD == 1) | |
132 ,UWORD8 saic_flag | |
133 #endif /* NEW_SNR_THRESHOLD == 1*/ | |
134 ); | |
135 #endif | |
136 #else /* RF_FAM == 61*/ | |
137 void l1pdmacro_rx_up (UWORD16 radio_freq, UWORD8 csf_filter_choice); | |
138 #endif | |
139 void l1pdmacro_rx_down (UWORD16 radio_freq, UWORD8 num_rx, BOOL rx_done_flag); | |
140 void l1pdmacro_tx_up (UWORD16 radio_freq); | |
141 void l1pdmacro_tx_down (UWORD16 radio_freq, WORD16 time, BOOL tx_flag, UWORD8 timing_advance,UWORD8 adc_active); | |
142 void l1pdmacro_tx_synth(UWORD16 radio_freq); | |
143 void l1pdmacro_anchor (WORD16 time); | |
144 | |
145 void l1dmacro_rx_synth(UWORD16 radio_freq); | |
146 void l1dmacro_agc(UWORD16 radio_freq, WORD8 agc_value, UWORD8 lna_off | |
147 #if (RF_FAM == 61) | |
148 ,UWORD8 if_ctl | |
149 #endif | |
150 ); | |
151 #if (CODE_VERSION == SIMULATION) | |
152 void l1dmacro_rx_ms (UWORD16 arfcn, BOOL rxnb_select); | |
153 #else | |
154 #if (L1_MADC_ON == 1) | |
155 #if (RF_FAM == 61) | |
156 void l1dmacro_rx_ms (UWORD16 arfcn,UWORD8 adc_active); | |
157 #endif | |
158 #else | |
159 void l1dmacro_rx_ms (UWORD16 arfcn); | |
160 #endif | |
161 #endif | |
162 void l1pdmacro_it_dsp_gen(WORD16 time); | |
163 | |
164 /*-------------------------------------------------------*/ | |
165 /* Prototypes of functions defined in this file. */ | |
166 /*-------------------------------------------------------*/ | |
167 // TPU Drivers... | |
168 | |
169 | |
170 // DSP Drivers... | |
171 void l1pddsp_synchro (UWORD8 switch_mode, UWORD8 camp_timeslot); | |
172 void l1pddsp_idle_prach_data (BOOL polling, UWORD8 cs_type, UWORD16 channel_request_data, | |
173 UWORD8 bsic, UWORD16 radio_freq); | |
174 void l1pddsp_idle_prach_power (UWORD8 txpwr, UWORD16 radio_freq, UWORD8 ts); | |
175 void l1pddsp_single_tx_block (UWORD8 burst_nb, UWORD8 *data, UWORD8 tsc, | |
176 UWORD16 radio_freq); | |
177 #if FF_L1_IT_DSP_USF | |
178 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq, | |
179 UWORD8 timeslot_no, BOOL ptcch_dl, BOOL usf_interrupt); | |
180 #else | |
181 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq, | |
182 UWORD8 timeslot_no, BOOL ptcch_dl); | |
183 #endif | |
184 void l1pddsp_transfer_mslot_ctrl (UWORD8 burst_nb, UWORD8 dl_bitmap, UWORD8 ul_bitmap, | |
185 UWORD8 *usf_table, UWORD8 mac_mode, UWORD8 *ul_buffer_index, | |
186 UWORD8 tsc, UWORD16 radio_freq, UWORD8 synchro_timeslot, | |
187 #if FF_L1_IT_DSP_USF | |
188 UWORD8 dsp_usf_interrupt | |
189 #else | |
190 UWORD8 usf_vote_enable | |
191 #endif | |
192 ); | |
193 void l1pddsp_transfer_mslot_power (UWORD8 *txpwr, UWORD16 radio_freq, UWORD8 ul_bitmap); | |
194 void l1pddsp_ul_ptcch_data (UWORD8 cs_type, UWORD16 channel_request_data, UWORD8 bsic, | |
195 UWORD16 radio_freq, UWORD8 timeslot_no); | |
196 void l1pddsp_interf_meas_ctrl (UWORD8 nb_meas_req); | |
197 void l1pddsp_transfer_meas_ctrl (UWORD8 meas_position); | |
198 | |
199 /*-------------------------------------------------------*/ | |
200 /* l1pd_afc() */ | |
201 /*-------------------------------------------------------*/ | |
202 /* Parameters : */ | |
203 /* Return : */ | |
204 /* Functionality : */ | |
205 /*-------------------------------------------------------*/ | |
206 void l1pd_afc(void) | |
207 { | |
208 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
209 l1ddsp_load_afc(l1s.afc); | |
210 #endif | |
211 #if (RF_FAM == 61) | |
212 l1dtpu_load_afc(l1s.afc); | |
213 #endif | |
214 } | |
215 | |
216 /*-------------------------------------------------------*/ | |
217 /* l1pdtpu_interf_meas() */ | |
218 /*-------------------------------------------------------*/ | |
219 /* Parameters : */ | |
220 /* Return : */ | |
221 /* Functionality : */ | |
222 /*-------------------------------------------------------*/ | |
223 UWORD8 l1pdtpu_interf_meas(UWORD16 radio_freq, | |
224 WORD8 agc, | |
225 UWORD8 lna_off, | |
226 UWORD8 meas_bitmap, | |
227 UWORD32 offset_serv, | |
228 UWORD16 win_id, | |
229 UWORD8 synchro_ts | |
230 #if (RF_FAM == 61) | |
231 ,UWORD8 if_ctl | |
232 #endif | |
233 ) | |
234 { | |
235 UWORD8 bit_mask = 0x80; | |
236 UWORD8 ts; | |
237 BOOL rf_programmed = FALSE; | |
238 UWORD8 count = 0; | |
239 | |
240 if(!win_id) | |
241 { | |
242 // Nothing programmed yet, we must avoid Mirror effect in Ctrl phase. | |
243 l1pdmacro_anchor(l1_config.params.rx_change_offset_time); | |
244 } | |
245 | |
246 for (ts=0; ts<8; ts++) | |
247 { | |
248 // the bitmap corresponds to that of the idle frame of the network!!! | |
249 #if ((CHIPSET==3)||(CHIPSET == 4)) | |
250 // limitation of 5 measurements for SAMSON (TPU RAM size limitation) | |
251 if((meas_bitmap & bit_mask)&&(count <= 4)) | |
252 #else | |
253 if(meas_bitmap & bit_mask) | |
254 #endif | |
255 { | |
256 UWORD16 local_win_id; | |
257 UWORD16 offset; | |
258 WORD16 when; | |
259 UWORD16 offset_chg; | |
260 | |
261 if((ts>synchro_ts) && (count==0)) | |
262 { | |
263 // The 1st Work does not contain any Interf meas. | |
264 // We must ovoid a possible Mirror effect for the rest of TS. | |
265 l1pdmacro_anchor(l1_config.params.rx_change_offset_time); | |
266 } | |
267 | |
268 // Increment nbr of meas. programmed. | |
269 count++; | |
270 | |
271 local_win_id = (8 - synchro_ts + ts) * BP_SPLIT; | |
272 if(local_win_id >= (BP_SPLIT * 8)) local_win_id -= BP_SPLIT * 8; // Modulo. | |
273 | |
274 // Compute offset | |
275 offset_chg = ((local_win_id * BP_DURATION) >> BP_SPLIT_PW2); | |
276 offset = offset_serv + offset_chg; | |
277 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE; | |
278 | |
279 if(!rf_programmed) | |
280 { | |
281 // Compute offset change timing | |
282 when = offset_chg + | |
283 PROVISION_TIME - | |
284 l1_config.params.rx_synth_setup_time - | |
285 EPSILON_OFFS; | |
286 | |
287 if(when < 0) when += TPU_CLOCK_RANGE; | |
288 | |
289 // Program TPU scenario | |
290 l1dmacro_offset (offset, when); // change TPU offset according to win_id | |
291 l1dmacro_rx_synth (radio_freq); // pgme SYNTH. | |
292 #if (RF_FAM !=61) | |
293 l1dmacro_agc (radio_freq, agc,lna_off); // pgme AGC. | |
294 #endif | |
295 | |
296 #if (RF_FAM == 61) | |
297 l1dmacro_agc (radio_freq, agc,lna_off, if_ctl); // pgme AGC. | |
298 #endif | |
299 | |
300 rf_programmed = TRUE; | |
301 } | |
302 else | |
303 { | |
304 // Compute offset change timing | |
305 when = offset_chg - BP_DURATION + PROVISION_TIME + PW_ACQUIS_DURATION + 20; | |
306 if(when < 0) when += TPU_CLOCK_RANGE; | |
307 | |
308 // Program TPU scenario | |
309 l1dmacro_offset (offset, when); // change TPU offset according to win_id | |
310 } | |
311 | |
312 #if (CODE_VERSION == SIMULATION) | |
313 l1dmacro_rx_ms (radio_freq, 1); // pgm PWR acquisition. | |
314 #else | |
315 #if (L1_MADC_ON == 1) | |
316 #if (RF_FAM == 61) | |
317 l1dmacro_rx_ms (radio_freq,INACTIVE); // pgm PWR acquisition. | |
318 #endif | |
319 #else | |
320 l1dmacro_rx_ms (radio_freq); // pgm PWR acquisition. | |
321 #endif | |
322 #endif | |
323 | |
324 l1dmacro_offset (offset_serv, IMM); // restore offset | |
325 } | |
326 | |
327 bit_mask >>= 1; | |
328 | |
329 } // for(ts... | |
330 | |
331 return(count); | |
332 } | |
333 | |
334 /*-------------------------------------------------------*/ | |
335 /* l1dtpu_serv_rx() */ | |
336 /*-------------------------------------------------------*/ | |
337 /* Parameters : */ | |
338 /* rx_id: range 0-7, first slot of RX group */ | |
339 /* rx_group_id: used in case |RX| |RX| */ | |
340 /* */ | |
341 /* Return : */ | |
342 /* Functionality : */ | |
343 /*-------------------------------------------------------*/ | |
344 void l1pdtpu_serv_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, | |
345 UWORD8 rx_id, UWORD32 offset_serv, UWORD8 num_rx, | |
346 UWORD8 rx_group_id, BOOL rx_done_flag,UWORD8 adc_active, | |
347 UWORD8 csf_filter_choice | |
348 #if (RF_FAM == 61) | |
349 ,UWORD8 if_ctl | |
350 #endif | |
351 #if (NEW_SNR_THRESHOLD == 1) | |
352 ,UWORD8 saic_flag | |
353 #endif /* NEW_SNR_THRESHOLD*/ | |
354 ) | |
355 { | |
356 UWORD16 offset; | |
357 | |
358 #if (CODE_VERSION == SIMULATION) | |
359 UWORD32 tpu_w_page; | |
360 | |
361 if (hw.tpu_r_page==0) | |
362 tpu_w_page=1; | |
363 else | |
364 tpu_w_page=0; | |
365 | |
366 hw.rx_id[tpu_w_page][rx_group_id-1]=rx_id; | |
367 hw.num_rx[tpu_w_page][rx_group_id-1]=num_rx; | |
368 hw.rx_group_id[tpu_w_page]=rx_group_id; | |
369 #endif | |
370 | |
371 offset = offset_serv + (rx_id * BP_DURATION); | |
372 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE; | |
373 | |
374 if (rx_group_id == 1) | |
375 { | |
376 // Time tracking. | |
377 l1dmacro_synchro (l1_config.params.rx_change_synchro_time, offset_serv); // Adjust serving OFFSET. | |
378 | |
379 #if L2_L3_SIMUL | |
380 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) | |
381 buffer_trace(3, 0x43, offset_serv, l1s.actual_time.fn, 0); | |
382 #endif | |
383 #endif | |
384 | |
385 // Change offset to align on RX. | |
386 l1dmacro_offset(offset, IMM); | |
387 | |
388 // Program Synth. | |
389 // Program ADC measurement | |
390 // Program AGC. | |
391 l1dmacro_rx_synth(radio_freq); | |
392 if(adc_active == ACTIVE) | |
393 l1dmacro_adc_read_rx(); | |
394 | |
395 l1dmacro_agc (radio_freq, agc, lna_off | |
396 #if (RF_FAM == 61) | |
397 ,if_ctl | |
398 #endif | |
399 ); | |
400 } | |
401 else | |
402 { | |
403 // Change offset to align on RX. | |
404 l1dmacro_offset(offset, IMM); // Change offset to align on RX. | |
405 } | |
406 | |
407 l1pdmacro_rx_up (radio_freq,adc_active, csf_filter_choice | |
408 #if (NEW_SNR_THRESHOLD == 1) | |
409 ,saic_flag | |
410 #endif /* NEW_SNR_THRESHOLD*/ | |
411 | |
412 ); // RX window opened. | |
413 l1pdmacro_rx_down(radio_freq, num_rx, rx_done_flag); // RX window closed. | |
414 | |
415 // Restore offset to synchro value. | |
416 l1dmacro_offset (offset_serv, IMM); | |
417 } | |
418 | |
419 /*-------------------------------------------------------*/ | |
420 /* l1dtpu_serv_tx() */ | |
421 /*-------------------------------------------------------*/ | |
422 /* Parameters : */ | |
423 /* Return : */ | |
424 /* Functionality : */ | |
425 /*-------------------------------------------------------*/ | |
426 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
427 #ifndef ABB_RAMP_UP_TIME //Flexi ABB Delays defines it in tpudrvXX.h | |
428 #define ABB_RAMP_UP_TIME 32 // maximum time for ramp up | |
429 #endif | |
430 | |
431 #ifndef ABB_RAMP_DELAY//Flexi ABB Delays defines it in tpudrvXX.h | |
432 #define ABB_RAMP_DELAY 6 // minimum ramp delay APCDEL | |
433 #endif | |
434 | |
435 #ifndef ABB_BULON_HOLD_TIME //Flexi ABB Delays defines it in tpudrvXX.h | |
436 #define ABB_BULON_HOLD_TIME 32 // min. hold time for BULON after BULENA down | |
437 #endif | |
438 | |
439 | |
440 #endif | |
441 void l1pdtpu_serv_tx(UWORD16 radio_freq, | |
442 UWORD8 timing_advance, | |
443 UWORD32 offset_serv, | |
444 UWORD8 tx_id, | |
445 UWORD8 num_tx, | |
446 UWORD8 tx_group_id, | |
447 UWORD8 switch_flag, | |
448 BOOL burst_type, | |
449 BOOL rx_flag, | |
450 UWORD8 adc_active) | |
451 { | |
452 WORD16 time; | |
453 UWORD32 offset_tx; | |
454 UWORD32 timing_advance_in_qbit = (UWORD32)timing_advance << 2; | |
455 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) | |
456 UWORD16 apcdel1_data, apcdel1_data_up; | |
457 #endif | |
458 UWORD8 i; | |
459 static UWORD8 static_switch_flag = 0; | |
460 | |
461 #if (CODE_VERSION == SIMULATION) | |
462 UWORD32 tpu_w_page; | |
463 | |
464 if (hw.tpu_r_page==0) | |
465 tpu_w_page=1; | |
466 else | |
467 tpu_w_page=0; | |
468 | |
469 hw.tx_id[tpu_w_page][tx_group_id-1]=tx_id; | |
470 hw.num_tx[tpu_w_page][tx_group_id-1]=num_tx; | |
471 hw.tx_group_id[tpu_w_page]=tx_group_id; | |
472 #endif | |
473 | |
474 // Reset timing advance if TA_ALGO not enabled. | |
475 #if !TA_ALGO | |
476 timing_advance_in_qbit = 0; | |
477 #endif | |
478 | |
479 // In case another group of TX bursts is called, the previous slot was a hole | |
480 // An IT has to be generated to the DSP so that ramps and power level are reloaded | |
481 // This does not apply to combinations of PRACH and TX NB | |
482 if ((tx_group_id > 1) && (!static_switch_flag)) | |
483 { | |
484 // exact timing for generation of IT during hole not required but | |
485 // time > time of previous ramp down (BULENA -> BULON down = 32 qb) + margin (10 qb) | |
486 #if (RF_FAM != 61) | |
487 time = TX_TABLE[tx_id-1] + PROVISION_TIME + ABB_BULON_HOLD_TIME + 10 | |
488 - l1_config.params.prg_tx_gsm; | |
489 #endif | |
490 | |
491 #if (RF_FAM == 61) | |
492 time = TX_TABLE[tx_id-1] + PROVISION_TIME + APC_RAMP_DOWN_TIME + 10 | |
493 - l1_config.params.prg_tx_gsm; | |
494 #endif | |
495 | |
496 if (burst_type == TX_NB_BURST) | |
497 time -= timing_advance_in_qbit; // time can never be negative here | |
498 | |
499 l1pdmacro_it_dsp_gen(time); | |
500 } | |
501 | |
502 | |
503 if (tx_group_id == 1) | |
504 { | |
505 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
506 //MS TX, set ABB in MS mode | |
507 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) | |
508 // ABB set to MS mode if |TX|TX|.., |TX|PRACH|, |PRACH|TX| or |PRACH|PRACH| | |
509 // switch_flag is set for the first burst of TX/PRACH or PRACH/PRACH combinations | |
510 // MS mode in ABB must be maintained for second burst (static_switch_flag) | |
511 if ((num_tx > 1) || (switch_flag) || (static_switch_flag)) | |
512 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl | B_MSLOT; | |
513 else | |
514 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl; | |
515 #endif | |
516 #endif | |
517 } | |
518 else | |
519 { | |
520 // handle special case |TX| |TX|TX| | |
521 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
522 //MS TX, set ABB in MS mode | |
523 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) | |
524 if ((num_tx > 1) || (switch_flag) || (static_switch_flag)) | |
525 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl | B_MSLOT; | |
526 #endif | |
527 #endif | |
528 } | |
529 | |
530 // Compute offset value for TX. | |
531 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX ! | |
532 if ((burst_type == TX_NB_BURST) || (switch_flag==1)) | |
533 { | |
534 offset_tx = offset_serv + TX_TABLE[tx_id] + PROVISION_TIME | |
535 - l1_config.params.prg_tx_gsm - timing_advance_in_qbit; | |
536 } | |
537 else | |
538 { | |
539 offset_tx = offset_serv + TX_TABLE[tx_id] + PROVISION_TIME | |
540 - l1_config.params.prg_tx_gsm; | |
541 } | |
542 | |
543 // offset_tx mod 5000 | |
544 if (offset_tx >= TPU_CLOCK_RANGE) | |
545 offset_tx -= TPU_CLOCK_RANGE; | |
546 | |
547 if(rx_flag == TRUE) | |
548 { | |
549 time = offset_tx - | |
550 l1_config.params.tx_synth_setup_time - | |
551 EPSILON_OFFS | |
552 - offset_serv; | |
553 if ((burst_type == TX_NB_BURST) || (switch_flag==1)) | |
554 time += timing_advance_in_qbit - TA_MAX; | |
555 } | |
556 else | |
557 time = TPU_CLOCK_RANGE - EPSILON_SYNC; | |
558 | |
559 if (time < 0) | |
560 time += TPU_CLOCK_RANGE; | |
561 | |
562 if (!static_switch_flag) | |
563 l1dmacro_offset (offset_tx, (WORD32) time); // load OFFSET for TX before each burst. | |
564 | |
565 #if L2_L3_SIMUL | |
566 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) | |
567 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0); | |
568 #endif | |
569 #endif | |
570 | |
571 time=0; | |
572 | |
573 // program PLL only if no TX control carried out in same frame: |TX| |TX|TX| possible | |
574 // |PRACH|TX|, |TX|PRACH| or |PRACH|PRACH| also possible | |
575 if (tx_group_id == 1) | |
576 { | |
577 l1pdmacro_tx_synth(radio_freq); // load SYNTH. | |
578 } | |
579 | |
580 if (!static_switch_flag) // window opened for previous time slot (TX/PRACH or PRACH/PRACH) | |
581 l1pdmacro_tx_up(radio_freq); // TX window opened | |
582 | |
583 | |
584 #if (CODE_VERSION == SIMULATION) | |
585 if (burst_type == TX_RA_BURST) | |
586 { | |
587 time += l1_config.params.tx_ra_duration; | |
588 } | |
589 else | |
590 { | |
591 if (num_tx > 1) | |
592 // num_tx * BP_DURATION | |
593 time += TX_TABLE[num_tx - 1] + l1_config.params.tx_nb_duration; | |
594 else | |
595 time += l1_config.params.tx_nb_duration; | |
596 } | |
597 #else | |
598 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
599 // Read APCDEL1 register DELU(4:0): delay of ramp up start, DELD (9:5) delay of ramp down start | |
600 // This value is used for computations in MS TX or TX/PRACH combinations | |
601 // This value is not modified by the computations | |
602 apcdel1_data = (l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 >> 6) & 0x03ff; | |
603 apcdel1_data_up = apcdel1_data & 0x001f; //delay of ramp up start | |
604 #endif | |
605 | |
606 #if (RF_FAM == 61) | |
607 // Read APCDEL1 register DELU(4:0): delay of ramp up start, DELD (9:5) delay of ramp down start | |
608 // This value is used for computations in MS TX or TX/PRACH combinations | |
609 // This value is not modified by the computations | |
610 apcdel1_data = (l1s_dsp_com.dsp_ndb_ptr->d_apcdel1) & 0x03ff; | |
611 apcdel1_data_up = apcdel1_data & 0x001f; //delay of ramp up start | |
612 #endif | |
613 | |
614 if (!switch_flag) | |
615 { | |
616 if (burst_type == TX_NB_BURST) | |
617 { | |
618 // If PRACH precedes TX normal burst(s) we have to add BP_DURATION | |
619 if (static_switch_flag) | |
620 time += BP_DURATION; | |
621 | |
622 // generate DSP IT for each TX slot after ramp up | |
623 // Margin: | |
624 // ABB_RAMP_DELAY = 4*1.5bits internal ABB delay BULENA ON -> ramp up | |
625 // apcdel1_data_up = additional delay BULENA ON -> ramp up | |
626 // ABB_RAMP_UP_TIME: maximum time for ramp up: 16 coeff. | |
627 // 10 qbits of additional margin | |
628 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
629 for (i=0; i<num_tx; i++) | |
630 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + i*BP_DURATION + apcdel1_data_up + 10); | |
631 #endif | |
632 | |
633 #if (RF_FAM == 61) | |
634 for (i=0; i<num_tx; i++) | |
635 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + i*BP_DURATION + apcdel1_data_up + 10); | |
636 #endif | |
637 | |
638 | |
639 if (num_tx > 1) | |
640 // (num_tx - 1) * BP_DURATION + normal burst duration | |
641 time += TX_TABLE[num_tx - 1] + l1_config.params.tx_nb_duration - (num_tx - 1); | |
642 else | |
643 time += l1_config.params.tx_nb_duration; | |
644 } | |
645 else //PRACH | |
646 { | |
647 // If TX NB precedes PRACH we have to add BP_DURATION and TA (in qbits) | |
648 if (static_switch_flag == 1) | |
649 { | |
650 if (timing_advance_in_qbit > 240) // clip TA, cf. comment below | |
651 timing_advance_in_qbit = 240; | |
652 time += BP_DURATION + timing_advance_in_qbit; | |
653 } | |
654 // If PRACH precedes PRACH we have to add BP_DURATION | |
655 else if (static_switch_flag == 2) | |
656 time += BP_DURATION ; | |
657 | |
658 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
659 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); | |
660 #endif | |
661 | |
662 #if (RF_FAM == 61) | |
663 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); | |
664 #endif | |
665 | |
666 time += l1_config.params.tx_ra_duration; | |
667 } | |
668 | |
669 } | |
670 else if (switch_flag == 1) // |TX|PRACH| or |PRACH|TX| | |
671 { | |
672 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
673 // => ABB windows are opened as for TX_NB in MS mode | |
674 // => Ramp up start of PRACH is delayed inside this window by the TA of the TX_NB | |
675 // => DSP inserts dummy bits such that ramp and modulation match | |
676 // Rem.: the TA passed for the PRACH is the one for the following TX_NB!!! | |
677 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) || (RF_FAM == 61) | |
678 // In combinations of TX_NB and PRACH apcdel1_bis and apcdel2_bis apply to the PRACH | |
679 UWORD16 apcdel1_bis_data, apcdel1_bis_data_up, apcdel2_bis_data_up, prach_delay; | |
680 API d_ctrl_abb_gprs; | |
681 | |
682 // clip TA (in qbit): max. TA supported = BP_DURATION - PRACH duration - max. ramp time | |
683 // = 625 - 88*4 - 32 = 241 | |
684 if (timing_advance_in_qbit > 240) | |
685 timing_advance_in_qbit = 240; | |
686 | |
687 prach_delay = apcdel1_data_up + timing_advance_in_qbit; | |
688 apcdel1_bis_data_up = prach_delay & 0x001f; | |
689 apcdel2_bis_data_up = (prach_delay >> 5) & 0x001f; | |
690 | |
691 // For ramp down delay we need to keep the original value from APCDEL1 (bits 9:5) | |
692 // APCDEL2 default value is '0' | |
693 apcdel1_bis_data = apcdel1_bis_data_up | (apcdel1_data & 0x03e0); | |
694 | |
695 #if(RF_FAM != 61) | |
696 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1_bis = (apcdel1_bis_data << 6) | 0x04; | |
697 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2_bis = (apcdel2_bis_data_up << 6) | 0x34; | |
698 #else | |
699 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1_bis = (apcdel1_bis_data ); | |
700 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2_bis = (apcdel2_bis_data_up); | |
701 #endif | |
702 | |
703 if (burst_type == TX_RA_BURST) // |PRACH|TX| | |
704 { | |
705 | |
706 #if(RF_FAM != 61) | |
707 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + prach_delay + 10); | |
708 #else | |
709 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + prach_delay + 10); | |
710 #endif | |
711 // apcdel1_bis, apcdel2_bis must be programmed for the current ts (PRACH) | |
712 // here we need to overwrite (mask) bits for APCDEL1, APCDEL2 programming done in l1pddsp_transfer_mslot_power() | |
713 d_ctrl_abb_gprs = l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id]; | |
714 d_ctrl_abb_gprs |= ((1 << B_BULRAMPDEL_BIS) | (1 << B_BULRAMPDEL2_BIS)); | |
715 d_ctrl_abb_gprs &= ~((1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
716 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id] = d_ctrl_abb_gprs; | |
717 } | |
718 else // |TX|PRACH| | |
719 { | |
720 #if(RF_FAM != 61) | |
721 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); | |
722 #else | |
723 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); | |
724 #endif | |
725 | |
726 // apcdel1_bis, apcdel2_bis must be programmed for the next ts (PRACH) | |
727 d_ctrl_abb_gprs = l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id + 1]; | |
728 d_ctrl_abb_gprs |= ((1 << B_BULRAMPDEL_BIS) | (1 << B_BULRAMPDEL2_BIS)); | |
729 d_ctrl_abb_gprs &= ~((1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
730 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id + 1] = d_ctrl_abb_gprs; | |
731 } | |
732 #endif // ANALOG | |
733 | |
734 static_switch_flag = 1; | |
735 | |
736 #endif // DSP == 33 || DSP == 34 || (DSP == 36) || (DSP == 37) | |
737 } | |
738 else if (switch_flag == 2) // |PRACH|PRACH| | |
739 // Combination handled by programming ABB with MS mode = 1 | |
740 // => first burst length of first PRACH = BP_DURATION | |
741 { | |
742 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
743 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); | |
744 #endif | |
745 | |
746 #if (RF_FAM == 61) | |
747 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); | |
748 #endif | |
749 | |
750 static_switch_flag = 2; | |
751 } | |
752 #endif //Codeversion | |
753 | |
754 // In case of combinations TX_NB/PRACH or PRACH/PRACH the TX window is kept open | |
755 if (!switch_flag) | |
756 { | |
757 l1pdmacro_tx_down(radio_freq, time, switch_flag, timing_advance_in_qbit,adc_active); // TX window closed | |
758 | |
759 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value. | |
760 | |
761 static_switch_flag = 0; | |
762 } | |
763 | |
764 #if L2_L3_SIMUL | |
765 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) | |
766 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0); | |
767 #endif | |
768 #endif | |
769 } | |
770 | |
771 /*-------------------------------------------------------*/ | |
772 /* l1pddsp_synchro() */ | |
773 /*-------------------------------------------------------*/ | |
774 /* Parameters : */ | |
775 /* Return : */ | |
776 /* Functionality : */ | |
777 /*-------------------------------------------------------*/ | |
778 void l1pddsp_synchro(UWORD8 switch_mode, UWORD8 camp_timeslot) | |
779 { | |
780 // Set "b_abort" to TRUE. | |
781 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= (1 << B_TASK_ABORT); | |
782 | |
783 // Set switch mode within "b_switch_to_gprs" & "b_switch_to_gms" | |
784 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = (switch_mode << B_SWITCH); | |
785 | |
786 // In case of a switch to GPRS_SCHEDULER, last_used_txpwr is set to "NO_TXPWR" | |
787 // in order to force GSM ramp programming when the MS will switch back to | |
788 // GSM_SCHEDULER | |
789 // Moreover, the d_win_start_gprs register must be initialized only during the | |
790 // GSM->GPRS switch too. | |
791 if(switch_mode == GPRS_SCHEDULER) | |
792 { | |
793 l1s.last_used_txpwr = NO_TXPWR; | |
794 | |
795 // Set camp timeslot. | |
796 l1ps_dsp_com.pdsp_ndb_ptr->d_win_start_gprs = camp_timeslot; | |
797 } | |
798 } | |
799 | |
800 | |
801 /*-------------------------------------------------------*/ | |
802 /* l1pddsp_idle_prach_data() */ | |
803 /*-------------------------------------------------------*/ | |
804 /* Parameters : */ | |
805 /* Return : */ | |
806 /* Functionality : */ | |
807 /*-------------------------------------------------------*/ | |
808 void l1pddsp_idle_prach_data(BOOL polling, | |
809 UWORD8 cs_type, | |
810 UWORD16 channel_request_data, | |
811 UWORD8 bsic, | |
812 UWORD16 radio_freq) | |
813 { | |
814 UWORD16 swap_bit; // 16 bit wide to allow shift left. | |
815 | |
816 // UL on TS=3. | |
817 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> 3; | |
818 | |
819 // Swap I/Q management. | |
820 swap_bit = l1ps_swap_iq_ul(radio_freq); | |
821 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; | |
822 | |
823 // Load UL buffer according to "polling" bit. | |
824 if(polling) | |
825 { | |
826 // Select first UL polling buffer. | |
827 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 8; | |
828 | |
829 // Store CS type. | |
830 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = cs_type; | |
831 | |
832 // Store UL data block. | |
833 if(cs_type == CS_PAB8_TYPE) | |
834 { | |
835 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2] = ((API)(bsic << 2)) | | |
836 ((API)(channel_request_data) << 8); | |
837 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][3] = 0; | |
838 } | |
839 else | |
840 { | |
841 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2] = ((API)(channel_request_data) << 5); | |
842 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][3] = ((API)(bsic << 10)); | |
843 } | |
844 } | |
845 else | |
846 { | |
847 // Set "b_access_prach" to indicate 1 Prach only to DSP. | |
848 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= (1 << B_ACCESS_PRACH); | |
849 | |
850 // Select first UL data buffer. | |
851 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 0; | |
852 | |
853 // Store CS type. | |
854 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][0] = cs_type; | |
855 | |
856 // Store UL data block. | |
857 if(cs_type == CS_PAB8_TYPE) | |
858 { | |
859 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][1] = ((API)(bsic << 2)) | | |
860 ((API)(channel_request_data) << 8); | |
861 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][2] = 0; | |
862 } | |
863 else | |
864 { | |
865 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][1] = ((API)(channel_request_data) << 5); | |
866 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][2] = ((API)(bsic << 10)); | |
867 } | |
868 | |
869 if (l1pa_l1ps_com.pra_info.prach_alloc == FIX_PRACH_ALLOC) | |
870 { | |
871 // Set fix alloc bit. | |
872 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs |= (2 << B_MAC_MODE); | |
873 } | |
874 else | |
875 { | |
876 // Reset MAC mode to dynamic allocation | |
877 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= ~(3 << B_MAC_MODE); | |
878 | |
879 #if !FF_L1_IT_DSP_USF | |
880 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
881 // Enable USF vote on timeslot 0 | |
882 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = 0x80; | |
883 #endif | |
884 #endif | |
885 } | |
886 } | |
887 } | |
888 | |
889 /*-------------------------------------------------------*/ | |
890 /* l1pddsp_idle_prach_power() */ | |
891 /*-------------------------------------------------------*/ | |
892 /* Parameters : */ | |
893 /* Return : */ | |
894 /* Functionality : */ | |
895 /*-------------------------------------------------------*/ | |
896 void l1pddsp_idle_prach_power(UWORD8 txpwr, | |
897 UWORD16 radio_freq, | |
898 UWORD8 ts) | |
899 { | |
900 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) | |
901 UWORD16 pwr_data; | |
902 #endif | |
903 | |
904 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) ) | |
905 // Force FIXED transmit power if requested. | |
906 if(l1_config.tx_pwr_code == 0) | |
907 { | |
908 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = l1_config.params.fixed_txpwr; | |
909 | |
910 // Control bitmap: update RAMP, use RAMP[5][..]. | |
911 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = | |
912 ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
913 | |
914 // Store Ramp. | |
915 #if (CODE_VERSION != SIMULATION) | |
916 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[5], | |
917 0, /* not used */ | |
918 0, /* not used */ | |
919 1 /* arbitrary value for arfcn */ ); | |
920 #endif | |
921 } | |
922 else | |
923 { | |
924 // Get H/W value corresponding to txpwr command. | |
925 pwr_data = Cust_get_pwr_data(txpwr, radio_freq | |
926 #if(REL99 && FF_PRF) | |
927 ,1 | |
928 #endif | |
929 ); | |
930 | |
931 // Store Transmit power. | |
932 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = ((pwr_data << 6) | 0x12); | |
933 | |
934 // Control bitmap: update RAMP, use RAMP[5][..]. | |
935 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
936 | |
937 // Store Ramp. | |
938 #if (CODE_VERSION != SIMULATION) | |
939 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[5][0]), txpwr, txpwr, radio_freq); | |
940 #endif | |
941 } | |
942 #endif | |
943 | |
944 #if (RF_FAM == 61) | |
945 // Force FIXED transmit power if requested. | |
946 if(l1_config.tx_pwr_code == 0) | |
947 { | |
948 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = l1_config.params.fixed_txpwr; | |
949 | |
950 // Control bitmap: update RAMP, use RAMP[5][..]. | |
951 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = | |
952 ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
953 | |
954 // Store Ramp. | |
955 #if (DSP ==38) || (DSP == 39) | |
956 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[5], | |
957 0, /* not used */ | |
958 0, /* not used */ | |
959 1 /* arbitrary value for arfcn */ ); | |
960 #endif | |
961 } | |
962 else | |
963 { | |
964 // Get H/W value corresponding to txpwr command. | |
965 pwr_data = Cust_get_pwr_data(txpwr, radio_freq | |
966 #if(REL99 && FF_PRF) | |
967 ,1 | |
968 #endif | |
969 ); | |
970 | |
971 // Store Transmit power. | |
972 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = (API) (pwr_data); | |
973 | |
974 // Control bitmap: update RAMP, use RAMP[5][..]. | |
975 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
976 | |
977 // Store Ramp. | |
978 #if(DSP == 38) || (DSP == 39) | |
979 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[5][0]), txpwr, txpwr, radio_freq); | |
980 #endif | |
981 } | |
982 #endif //RF_FAM == 61 | |
983 | |
984 } | |
985 | |
986 /*-------------------------------------------------------*/ | |
987 /* l1pddsp_single_block() */ | |
988 /*-------------------------------------------------------*/ | |
989 /* Parameters : */ | |
990 /* Return : */ | |
991 /* Functionality : */ | |
992 /*-------------------------------------------------------*/ | |
993 void l1pddsp_single_tx_block(UWORD8 burst_nb, | |
994 UWORD8 *data, | |
995 UWORD8 tsc, | |
996 UWORD16 radio_freq) | |
997 { | |
998 UWORD16 swap_bit; // 16 bit wide to allow shift left. | |
999 | |
1000 // Burst number within a block. | |
1001 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; | |
1002 | |
1003 // UL on TS=3. | |
1004 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> 3; | |
1005 | |
1006 // Swap I/Q management. | |
1007 swap_bit = l1ps_swap_iq_ul(radio_freq); | |
1008 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; | |
1009 | |
1010 // Select first UL polling buffer. | |
1011 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 8; | |
1012 | |
1013 // Store CS type: CS1 for Polling. | |
1014 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS1_TYPE_POLL; | |
1015 | |
1016 if(burst_nb == BURST_1) | |
1017 // Store UL data block. | |
1018 { | |
1019 API *ul_block_ptr = &(l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2]); | |
1020 UWORD8 i,j; | |
1021 | |
1022 // Copy first 22 bytes in the first 11 words after header. | |
1023 for (i=0, j=0; j<11; j++) | |
1024 { | |
1025 ul_block_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8); | |
1026 i += 2; | |
1027 } | |
1028 // Copy last UWORD8 (23rd) in the 12th word after header. | |
1029 ul_block_ptr[11] = data[22]; | |
1030 } | |
1031 | |
1032 // Training sequence. | |
1033 // Rem: bcch_freq_ind is set within Hopping algo. | |
1034 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; | |
1035 } | |
1036 | |
1037 /*-------------------------------------------------------*/ | |
1038 /* l1pddsp_idle_rx_nb() */ | |
1039 /*-------------------------------------------------------*/ | |
1040 /* Parameters : */ | |
1041 /* Return : */ | |
1042 /* Functionality : */ | |
1043 /*-------------------------------------------------------*/ | |
1044 #if FF_L1_IT_DSP_USF | |
1045 void l1pddsp_idle_rx_nb(UWORD8 burst_nb, | |
1046 UWORD8 tsc, | |
1047 UWORD16 radio_freq, | |
1048 UWORD8 timeslot_no, | |
1049 BOOL ptcch_dl, | |
1050 BOOL usf_interrupt) | |
1051 #else | |
1052 void l1pddsp_idle_rx_nb(UWORD8 burst_nb, | |
1053 UWORD8 tsc, | |
1054 UWORD16 radio_freq, | |
1055 UWORD8 timeslot_no, | |
1056 BOOL ptcch_dl) | |
1057 #endif | |
1058 { | |
1059 UWORD16 swap_bit; // 16 bit wide to allow shift left. | |
1060 | |
1061 // DL on TS=0. | |
1062 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= 0x80 >> timeslot_no; | |
1063 | |
1064 // Swap I/Q management. | |
1065 swap_bit = l1ps_swap_iq_dl(radio_freq); | |
1066 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= swap_bit << 15; | |
1067 | |
1068 if(ptcch_dl) | |
1069 { | |
1070 // PTCCH/DL case must be flagged to DSP. | |
1071 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= (1 << B_PTCCH_DL); | |
1072 } | |
1073 | |
1074 // Burst number within a block. | |
1075 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; | |
1076 | |
1077 // Channel coding is forced to CS1. | |
1078 l1ps_dsp_com.pdsp_ndb_ptr->a_ctrl_ched_gprs[timeslot_no] = CS1_TYPE_DATA; | |
1079 | |
1080 // pass information to DSP which good USF value is to be expected | |
1081 l1ps_dsp_com.pdsp_ndb_ptr->a_usf_gprs[0] = (API) 0x07; | |
1082 | |
1083 #if FF_L1_IT_DSP_USF | |
1084 // In case of connection establishment mode with dynamic or fixed | |
1085 // allocation scheme we need to request the DSP USF interrupt for PRACH | |
1086 // scheduling. Latched by DSP during Work3 | |
1087 if (burst_nb == 3) | |
1088 { | |
1089 if (usf_interrupt) | |
1090 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable |= (1 << B_USF_IT); | |
1091 else | |
1092 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable &= ~(1 << B_USF_IT); | |
1093 } | |
1094 #endif | |
1095 | |
1096 // RIF receiver algorithm: select 156.25. | |
1097 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= 0xFFFF ^ (1 << B_RIF_RX_MODE); | |
1098 | |
1099 // Training sequence. | |
1100 // Rem: bcch_freq_ind is set within Hopping algo. | |
1101 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; | |
1102 | |
1103 } | |
1104 | |
1105 | |
1106 /*-------------------------------------------------------*/ | |
1107 /* l1pddsp_transfer_mslot_ctrl() */ | |
1108 /*-------------------------------------------------------*/ | |
1109 /* Parameters : */ | |
1110 /* Return : */ | |
1111 /* Functionality : */ | |
1112 /*-------------------------------------------------------*/ | |
1113 void l1pddsp_transfer_mslot_ctrl(UWORD8 burst_nb, | |
1114 UWORD8 dl_bitmap, | |
1115 UWORD8 ul_bitmap, | |
1116 UWORD8 *usf_table, | |
1117 UWORD8 mac_mode, | |
1118 UWORD8 *ul_buffer_index, | |
1119 UWORD8 tsc, | |
1120 UWORD16 radio_freq, | |
1121 UWORD8 synchro_timeslot, | |
1122 #if FF_L1_IT_DSP_USF | |
1123 UWORD8 dsp_usf_interrupt | |
1124 #else | |
1125 UWORD8 usf_vote_enable | |
1126 #endif | |
1127 ) | |
1128 { | |
1129 UWORD8 i; | |
1130 UWORD16 swap_bit; // 16 bit wide to allow shift left. | |
1131 | |
1132 // Burst number within a block. | |
1133 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; | |
1134 | |
1135 // DL bitmap. | |
1136 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs = dl_bitmap; | |
1137 | |
1138 // UL bitmap. | |
1139 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs = ul_bitmap; | |
1140 | |
1141 // Swap I/Q management for DL. | |
1142 swap_bit = l1ps_swap_iq_dl(radio_freq); | |
1143 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= swap_bit << 15; | |
1144 | |
1145 // Swap I/Q management for UL. | |
1146 swap_bit = l1ps_swap_iq_ul(radio_freq); | |
1147 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; | |
1148 | |
1149 if(burst_nb == 0) | |
1150 { | |
1151 // Store USF table | |
1152 for(i=0;i<(8 - synchro_timeslot);i++) | |
1153 l1ps_dsp_com.pdsp_ndb_ptr->a_usf_gprs[i] = usf_table[i+synchro_timeslot]; | |
1154 | |
1155 // Automatic CS detection. | |
1156 for(i=0;i<8;i++) | |
1157 { | |
1158 l1ps_dsp_com.pdsp_ndb_ptr->a_ctrl_ched_gprs[i] = CS_AUTO_DETECT; | |
1159 | |
1160 // Select first UL polling buffer. | |
1161 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[i] = ul_buffer_index[i]; | |
1162 } | |
1163 | |
1164 #if !FF_L1_IT_DSP_USF | |
1165 // USF vote enable programming | |
1166 | |
1167 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
1168 // Multislot TX allowed and usf_vote_enable suported: programs usf_vote_enable | |
1169 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = usf_vote_enable; | |
1170 #else | |
1171 // Single slot TX only and usf_vote_enable not supported | |
1172 // Modify MAC mode | |
1173 if (usf_vote_enable) | |
1174 // USF vote enabled --> Set MAC mode to dynamic mode | |
1175 mac_mode = DYN_ALLOC; | |
1176 else | |
1177 // USF vote disabled --> Set MAC mode to fixed mode | |
1178 mac_mode = FIX_ALLOC_NO_HALF; | |
1179 #endif | |
1180 | |
1181 #endif // !FF_L1_IT_DSP_USF | |
1182 | |
1183 // MAC mode. | |
1184 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= ~(3 << B_MAC_MODE); | |
1185 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs |= mac_mode << B_MAC_MODE; | |
1186 } | |
1187 | |
1188 #if FF_L1_IT_DSP_USF | |
1189 if(burst_nb == 3) | |
1190 { | |
1191 // Program DSP to generate an interrupt once USF available if | |
1192 // required. Latched by DSP during Work3. | |
1193 if (dsp_usf_interrupt) | |
1194 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = (1 << B_USF_IT); | |
1195 else | |
1196 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = 0; | |
1197 } | |
1198 #endif | |
1199 | |
1200 // RIF receiver algorithm: select 156.25. | |
1201 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= 0xFFFF ^ (1 << B_RIF_RX_MODE); | |
1202 | |
1203 // d_fn | |
1204 // ---- | |
1205 // bit [0..7] -> b_fn_report, unused for GPRS | |
1206 // bit [8..15] -> b_fn_sid , FN%104 | |
1207 l1s_dsp_com.dsp_db_w_ptr->d_fn = ((l1s.next_time.fn_mod104)<<8); | |
1208 | |
1209 // Training sequence. | |
1210 // Rem: bcch_freq_ind is set within Hopping algo. | |
1211 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; | |
1212 | |
1213 } | |
1214 | |
1215 | |
1216 /*-------------------------------------------------------*/ | |
1217 /* l1pddsp_transfer_mslot_power() */ | |
1218 /*-------------------------------------------------------*/ | |
1219 /* Parameters : */ | |
1220 /* Return : */ | |
1221 /* Functionality : */ | |
1222 /*-------------------------------------------------------*/ | |
1223 void l1pddsp_transfer_mslot_power(UWORD8 *txpwr, | |
1224 UWORD16 radio_freq, | |
1225 UWORD8 ul_bitmap) | |
1226 { | |
1227 #define NO_TX 100 | |
1228 | |
1229 UWORD16 i; // 16 bit needed for shifting pupose. | |
1230 UWORD8 last_TX = NO_TX; | |
1231 UWORD8 txpwr_ramp_up; | |
1232 UWORD8 txpwr_ramp_down; | |
1233 UWORD8 cpt_TX = 0; | |
1234 UWORD8 ts_mask; | |
1235 WORD16 ts_conv; | |
1236 | |
1237 #if (REL99 && FF_PRF) | |
1238 UWORD8 number_uplink_timeslot = 0 ; // number of uplink timeslot for power reduction feature | |
1239 #endif | |
1240 | |
1241 | |
1242 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) | |
1243 UWORD16 pwr_data; | |
1244 UWORD16 d_ramp_idx; | |
1245 #endif | |
1246 | |
1247 //Locosto #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) | |
1248 | |
1249 // This function is called with an ul_bitmap which represents the abolute | |
1250 // position of any Tx bursts in this frame. This bitmap has already | |
1251 // absorbed any synchro change (in dl_tn), hence we need to do some | |
1252 // processing to recover the actual Tx timeslot number which is used | |
1253 // as an index into the txpwr array. | |
1254 // | |
1255 // Example : MS Class 8 with 4 Rx and 1 Tx : | |
1256 // | |
1257 // | |
1258 // dl_ts_alloc : 0x0f 0 0 0 0 R R R R | |
1259 // ul_ts_alloc : 0x02 0 0 0 0 0 0 T 0 | |
1260 // shift + combine : 0 0 0 0 R R R R 0 T | |
1261 // set dl_tn=4 : R R R R 0 T 0 0 | |
1262 // ul_bitmap : 0x04 0 0 0 0 0 1 0 0 | |
1263 // i : 5 | |
1264 // | |
1265 // Example : MS Class 8 with 1 Rx and 1 Tx on TS=7 | |
1266 // | |
1267 // dl_ts_alloc : 0x01 0 0 0 0 0 0 0 R | |
1268 // ul_ts_alloc : 0x01 0 0 0 0 0 0 0 T | |
1269 // shift + combine : 0 0 0 0 0 0 0 R 0 0 T | |
1270 // set dl_tn=7 : R 0 0 T 0 0 0 0 | |
1271 // ul_bitmap : 0x10 0 0 0 1 0 0 0 0 | |
1272 // i : 3 | |
1273 // | |
1274 // We recover the actual timeslot from the ul_bitmap by the following | |
1275 // method : | |
1276 // | |
1277 // ts = (i + dl_tn) - 3 | |
1278 // | |
1279 // Where i is the loopindex usd to detect "1" in the ul_bitmap. | |
1280 // This works for MS class 8 because (3 <= i <= 5) if the | |
1281 // multislot class is respected. | |
1282 | |
1283 #if (REL99 && FF_PRF)// power reduction feature | |
1284 for (i=0; i<8; i++) | |
1285 { | |
1286 // computed number of uplink timeslot in order to determine uplink power reduction | |
1287 ts_mask = (0x80>>i); | |
1288 if (ul_bitmap & ts_mask) | |
1289 number_uplink_timeslot++; | |
1290 } | |
1291 #endif | |
1292 | |
1293 | |
1294 ts_conv = l1a_l1s_com.dl_tn - 3; | |
1295 | |
1296 // Index of the programmed ramps | |
1297 d_ramp_idx = 0; | |
1298 | |
1299 for(i=0;i<8;i++) | |
1300 { | |
1301 // Program Transmit power and ramp for allocated timeslots. | |
1302 if(ul_bitmap & (0x80>>i)) | |
1303 { | |
1304 // Fixe transmit power. | |
1305 if(l1_config.tx_pwr_code == 0) | |
1306 { | |
1307 // Store Transmit power. | |
1308 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = l1_config.params.fixed_txpwr; | |
1309 | |
1310 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..]. | |
1311 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = | |
1312 ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
1313 | |
1314 // Store Ramp. | |
1315 #if (RF_FAM == 61) | |
1316 #if (DSP ==38) || (DSP == 39) | |
1317 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx++], | |
1318 0, /* not used */ | |
1319 0, /* not used */ | |
1320 1 /* arbitrary value for arfcn */ ); | |
1321 #endif | |
1322 #else | |
1323 #if (CODE_VERSION != SIMULATION) | |
1324 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx++], | |
1325 0, /* not used */ | |
1326 0, /* not used */ | |
1327 1 /* arbitrary value for arfcn */ ); | |
1328 #endif | |
1329 #endif | |
1330 } | |
1331 else | |
1332 { | |
1333 // count the number of TX windows | |
1334 cpt_TX ++; | |
1335 | |
1336 // Get power amplifier data. | |
1337 #if(REL99 && FF_PRF) | |
1338 pwr_data = Cust_get_pwr_data(txpwr[i+ts_conv], radio_freq, number_uplink_timeslot); | |
1339 #else | |
1340 pwr_data = Cust_get_pwr_data(txpwr[i+ts_conv], radio_freq); | |
1341 #endif | |
1342 | |
1343 | |
1344 // Store Transmit power. | |
1345 #if(RF_FAM == 61) | |
1346 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = (pwr_data); | |
1347 #else | |
1348 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = ((pwr_data << 6) | 0x12); | |
1349 #endif | |
1350 | |
1351 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..] for slot i. | |
1352 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); | |
1353 | |
1354 // Store Ramp. | |
1355 // ========== | |
1356 // for the 1st TX the RAMP is: RAMP_UP_TX1 / RAMP_DOWN_TX1 | |
1357 // for the 2nd TX the RAMP is: RAMP_UP_TX2 / RAMP_DOWN_TX1 | |
1358 // for the 3rd TX the RAMP is: RAMP_UP_TX3 / RAMP_DOWN_TX2 | |
1359 // (...) | |
1360 // for the (i)th TX the RAMP is: RAMP_UP_TX_(i) / RAMP_DOWN_TX_(i-1) | |
1361 // for the additionnal RAMP : xxxx / RAMP_DOWN_TX_last | |
1362 | |
1363 txpwr_ramp_up = txpwr[i+ts_conv]; // the ramp up is the current TX | |
1364 | |
1365 if(last_TX == NO_TX) // specific case of the first TX | |
1366 txpwr_ramp_down = txpwr[i+ts_conv]; // the ramp down is the current TX | |
1367 else | |
1368 txpwr_ramp_down = txpwr[last_TX+ts_conv]; // the ramp down is the previous TX | |
1369 | |
1370 #if(RF_FAM == 61) | |
1371 #if(DSP == 38) || (DSP == 39) | |
1372 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx++][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); | |
1373 #endif | |
1374 #else | |
1375 #if (CODE_VERSION != SIMULATION) | |
1376 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx++][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); | |
1377 #endif | |
1378 #endif | |
1379 } | |
1380 | |
1381 // memorize the last TX window | |
1382 last_TX = i; | |
1383 } | |
1384 else | |
1385 { | |
1386 // program an interrupt in the TS following | |
1387 // the last TX window and needed by the DSP | |
1388 | |
1389 // Is it the TS following a TX window ? | |
1390 if((i == last_TX+1) && (i<8)) | |
1391 { | |
1392 // program the interrupt | |
1393 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = (1 << B_MS_RULE); | |
1394 } | |
1395 } | |
1396 } | |
1397 | |
1398 // in a multi-TX case an additionnal ramp down must be set | |
1399 if(cpt_TX > 1) | |
1400 { | |
1401 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..] for slot i and set the interrupt | |
1402 if((last_TX+1) <= 7) | |
1403 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[last_TX+1] = ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_MS_RULE)); | |
1404 | |
1405 // Store Ramp. | |
1406 // ========== | |
1407 txpwr_ramp_up = txpwr[last_TX+ts_conv]; // this ramp up is unused (default: set to last_TX) | |
1408 txpwr_ramp_down = txpwr[last_TX+ts_conv]; // the ramp down is the last TX | |
1409 | |
1410 #if(RF_FAM == 61) | |
1411 #if(DSP ==38) || (DSP == 39) | |
1412 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); | |
1413 #endif | |
1414 #else | |
1415 #if (CODE_VERSION != SIMULATION) | |
1416 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); | |
1417 #endif | |
1418 #endif | |
1419 } | |
1420 // #endif Locosto | |
1421 } | |
1422 | |
1423 | |
1424 /*-------------------------------------------------------*/ | |
1425 /* l1pddsp_ul_ptcch_data() */ | |
1426 /*-------------------------------------------------------*/ | |
1427 /* Parameters : */ | |
1428 /* Return : */ | |
1429 /* Functionality : */ | |
1430 /*-------------------------------------------------------*/ | |
1431 void l1pddsp_ul_ptcch_data(UWORD8 cs_type, | |
1432 UWORD16 channel_request_data, | |
1433 UWORD8 bsic, | |
1434 UWORD16 radio_freq, | |
1435 UWORD8 timeslot_no) | |
1436 { | |
1437 UWORD16 swap_bit; // 16 bit wide to allow shift left. | |
1438 | |
1439 // UL on TS=timeslot_no. | |
1440 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> timeslot_no; | |
1441 | |
1442 // Swap I/Q management. | |
1443 swap_bit = l1ps_swap_iq_ul(radio_freq); | |
1444 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; | |
1445 | |
1446 // Set "b_ptcch_ul" to indicate PTCCH/UL to DSP. | |
1447 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= (1 << B_PTCCH_UL); | |
1448 | |
1449 // Store CS type. | |
1450 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[0] = cs_type; | |
1451 | |
1452 // Store UL data block. | |
1453 if(cs_type == CS_PAB8_TYPE) | |
1454 { | |
1455 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[1] = ((API)(bsic << 2)) | | |
1456 ((API)(channel_request_data) << 8); | |
1457 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[2] = 0; | |
1458 } | |
1459 else | |
1460 { | |
1461 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[1] = ((API)(channel_request_data) << 5); | |
1462 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[2] = ((API)(bsic << 10)); | |
1463 } | |
1464 } | |
1465 | |
1466 | |
1467 /*-------------------------------------------------------*/ | |
1468 /* l1pddsp_interf_meas_ctrl() */ | |
1469 /*-------------------------------------------------------*/ | |
1470 /* Parameters : */ | |
1471 /* Return : */ | |
1472 /* Functionality : */ | |
1473 void l1pddsp_interf_meas_ctrl(UWORD8 nb_meas_req) | |
1474 { | |
1475 // Interference measurement task set as a monitoring task within GSM interface. | |
1476 // 101 means 1 meas, 102 means 2 meas ... | |
1477 // Rem: swap I/Q is not managed for power measurements. | |
1478 l1s_dsp_com.dsp_db_w_ptr->d_task_md = INTERF_DSP_TASK + nb_meas_req; | |
1479 } | |
1480 | |
1481 | |
1482 /*-------------------------------------------------------*/ | |
1483 /* l1pddsp_transfer_meas_ctrl() */ | |
1484 /*-------------------------------------------------------*/ | |
1485 /* Parameters : */ | |
1486 /* Return : */ | |
1487 /* Functionality : */ | |
1488 /*-------------------------------------------------------*/ | |
1489 void l1pddsp_transfer_meas_ctrl(UWORD8 meas_position) | |
1490 { | |
1491 // Store measurement position. | |
1492 // Rem: This is a L1S filtered information giving the position of the meas. as a | |
1493 // bitmap. | |
1494 // Rem: swap I/Q is not managed for power measurements. | |
1495 l1ps_dsp_com.pdsp_db_w_ptr->d_task_pm_gprs = meas_position; | |
1496 } | |
1497 | |
1498 /*-------------------------------------------------------*/ | |
1499 /* l1pddsp_meas_ctrl() */ | |
1500 /*-------------------------------------------------------*/ | |
1501 /* Parameters : */ | |
1502 /* Return : */ | |
1503 /* Functionality : */ | |
1504 /*-------------------------------------------------------*/ | |
1505 void l1pddsp_meas_ctrl(UWORD8 nbmeas, UWORD8 pm_pos) | |
1506 { | |
1507 // Request Signal level measurement task to DSP. A bit map is passed | |
1508 // to DSP in order to specify the position of the measurement. | |
1509 // Note: MSB is TN = 0 and LSB is TN = 7. | |
1510 // Rem: swap I/Q is not managed for power measurements. | |
1511 // Note: currently a maximum of four Pm can be performed / TDMA. This would | |
1512 // be modified in a near futur. | |
1513 // Note: If a Rx is programmed i.e. pm_pos = 1, only a maximum | |
1514 // of 3 Pm is requested to DSP and position of the Pm are right shifted (Rx on TN = 0). | |
1515 // Remark: In packet Idle mode Rx are still on TN = 0. This implies three Pm | |
1516 // always after the Rx. | |
1517 l1ps_dsp_com.pdsp_db_w_ptr->d_task_pm_gprs = ((UWORD8) (0xff << (8 - nbmeas))) >> pm_pos; | |
1518 } | |
1519 | |
1520 /*-------------------------------------------------------*/ | |
1521 /* l1pddsp_meas_read() */ | |
1522 /*-------------------------------------------------------*/ | |
1523 /* Parameters : */ | |
1524 /* Return : */ | |
1525 /* Functionality : */ | |
1526 /*-------------------------------------------------------*/ | |
1527 void l1pddsp_meas_read(UWORD8 nbmeas, UWORD16 *a_pm) | |
1528 { | |
1529 UWORD8 i = 0; | |
1530 UWORD8 j; | |
1531 UWORD8 bit_mask = 0x80; | |
1532 | |
1533 // Looks for first PM position | |
1534 while ((i < 8) && (l1ps_dsp_com.pdsp_db_r_ptr->d_task_pm_gprs & bit_mask) == 0) | |
1535 { | |
1536 i++; | |
1537 bit_mask >>= 1; | |
1538 } | |
1539 | |
1540 // Read 'nbmeas' contiguous PM levels from the first PM position | |
1541 // Note: PM are always programmed on contiguous timeslots | |
1542 for (j = 0; ((j < nbmeas)&&(i < 8)); j++) | |
1543 { | |
1544 // Download PM from DSP/MCU memory interface | |
1545 a_pm[j] = ((l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[i] & 0xffff)); | |
1546 | |
1547 // Read next PM on following TN | |
1548 i++; | |
1549 } | |
1550 } | |
1551 | |
1552 /*-------------------------------------------------------*/ | |
1553 /* l1pddsp_load_bcchn_task() */ | |
1554 /*-------------------------------------------------------*/ | |
1555 /* Parameters : */ | |
1556 /* Return : */ | |
1557 /* Functionality : */ | |
1558 /*-------------------------------------------------------*/ | |
1559 void l1pddsp_load_bcchn_task(UWORD8 tsq,UWORD16 radio_freq ) | |
1560 { | |
1561 UWORD16 swap_bit = l1ps_swap_iq_dl(radio_freq); | |
1562 | |
1563 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NBN_DSP_TASK | (swap_bit << 15); // Load BCCHN task | |
1564 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; | |
1565 } | |
1566 #endif |