FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cfile/l1_pwmgr.c @ 129:419f638cf03b

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l1_pwmgr.c: l1s_sleep_manager(): logic apparently reconstructed, but the compiler's register allocation still does not match
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 14 May 2016 06:28:44 +0000
parents a2f9560c1cf1
children c4b922f2b593
comparison
equal deleted inserted replaced
128:a2f9560c1cf1 129:419f638cf03b
773 UWORD32 sleep_time = l1s.actual_time.fn_mod42432; 773 UWORD32 sleep_time = l1s.actual_time.fn_mod42432;
774 #else 774 #else
775 UWORD32 sleep_time = l1s.actual_time.fn; 775 UWORD32 sleep_time = l1s.actual_time.fn;
776 #endif 776 #endif
777 777
778 #if (GSM_IDLE_RAM != 0)
779 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
780 BOOL flag_traffic_controller_state = 0;
781 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
782
783 #if (AUDIO_TASK == 1)
784 gsm_idle_ram_ctl->l1s_full_exec = l1s.l1_audio_it_com;
785 #endif
786
787 if (gsm_idle_ram_ctl->l1s_full_exec == TRUE)
788 return;
789 #endif
790
791 if (l1_config.pwr_mngt == PWR_MNGT) 778 if (l1_config.pwr_mngt == PWR_MNGT)
792 { 779 {
793 // Power management is enabled 780 // Power management is enabled
794 WORD32 min_time, OSload, HWtimer,wake_up_time,min_time_gauging; 781 WORD32 min_time, HWtimer,wake_up_time,min_time_gauging;
795 UWORD32 sleep_mode; 782 UWORD32 sleep_mode;
796 WORD32 afc_fix; 783 WORD32 afc_fix;
797 UWORD32 uw32_store_next_time;
798 static UWORD32 previous_sleep = FRAME_STOP; 784 static UWORD32 previous_sleep = FRAME_STOP;
799 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1) 785 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
800 BOOL extended_page_mode_state = 0; //Store state of extended page mode 786 BOOL extended_page_mode_state = 0; //Store state of extended page mode
801 #endif 787 #endif
802 WORD32 time_from_last_wakeup=0; 788 WORD32 time_from_last_wakeup=0;
814 //================================================= 800 //=================================================
815 // check System (SIM, UART, LDC ..... ) 801 // check System (SIM, UART, LDC ..... )
816 //================================================= 802 //=================================================
817 sleep_mode = Cust_check_system(); 803 sleep_mode = Cust_check_system();
818 804
819 #if (GSM_IDLE_RAM != 0)
820 //=================================================
821 // check System (SIM, UART, LDC ..... )
822 //=================================================
823 gsm_idle_ram_ctl->sleep_mode = sleep_mode;
824 #endif
825
826 if (sleep_mode == DO_NOT_SLEEP) 805 if (sleep_mode == DO_NOT_SLEEP)
827 {
828 #if (GSM_IDLE_RAM != 0)
829 gsm_idle_ram_ctl->os_load = 0;
830 gsm_idle_ram_ctl->hw_timer = 0;
831 #endif // GSM_IDLE_RAM
832 return; 806 return;
833 }
834 807
835 #if (CODE_VERSION != SIMULATION) 808 #if (CODE_VERSION != SIMULATION)
836 //================================================= 809 //=================================================
837 // Protect System structures 810 // Protect System structures
838 // must be called BEFORE INT_DisableIRQ() while 811 // must be called BEFORE INT_DisableIRQ() while
843 // Disable IRQ 816 // Disable IRQ
844 //================================================= 817 //=================================================
845 INT_DisableIRQ(); 818 INT_DisableIRQ();
846 #endif // NOT SIMULATION 819 #endif // NOT SIMULATION
847 820
848 #if (OP_L1_STANDALONE == 0)
849 /*GC_Sleep(); OMAPS00134004*/
850 #endif
851 //================================================= 821 //=================================================
852 // check OS loading 822 // check OS loading
853 //================================================= 823 //=================================================
854 OSload = OS_get_inactivity_ticks(); 824 min_time = OS_get_inactivity_ticks();
855 #if 0 /* FreeCalypso TCS211 reconstruction */
856 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){
857 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD;
858 l1_pwmgr_debug.fail_ret_val = OSload;
859 }
860 #endif
861 825
862 //================================================= 826 //=================================================
863 // check HW Timers loading 827 // check HW Timers loading
864 //================================================= 828 //=================================================
865 HWtimer= l1s_get_HWTimers_ticks(); 829 HWtimer= l1s_get_HWTimers_ticks();
866 #if 0 /* FreeCalypso TCS211 reconstruction */
867 if (HWtimer == 0){
868 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_HWTIMER;
869 l1_pwmgr_debug.fail_ret_val = 0;
870 }
871 #endif
872
873 #if (GSM_IDLE_RAM != 0)
874 //=================================================
875 // check OS loading
876 //=================================================
877 gsm_idle_ram_ctl->os_load = OSload;
878
879 //=================================================
880 // check HW Timers loading
881 //=================================================
882 gsm_idle_ram_ctl->hw_timer = HWtimer;
883 #endif // GSM_IDLE_RAM
884
885 if ((OSload > 0) && (OSload <= MIN_SLEEP_TIME))
886 OSload =0;
887 830
888 //================================================= 831 //=================================================
889 // check next gauging task for Packet Idle 832 // check next gauging task for Packet Idle
890 //================================================= 833 //=================================================
891 #if L1_GPRS 834 #if L1_GPRS
892 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle(); 835 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle();
893 #else 836 #else
894 min_time_gauging = -1; // not used 837 min_time_gauging = -1; // not used
895 #endif 838 #endif
896 #if 0 /* FreeCalypso TCS211 reconstruction */
897 if (min_time_gauging == 0){
898 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_MINTIMEGAUGING;
899 l1_pwmgr_debug.fail_ret_val = 0;
900 }
901 #endif // NOT SIMULATION
902
903 839
904 #if (OP_BT == 1) 840 #if (OP_BT == 1)
905 hci_ll_status = hci_ll_ok_for_sleep(); 841 hci_ll_status = hci_ll_ok_for_sleep();
906 #endif 842 #endif
907 // check if immediate activity planned 843 // check if immediate activity planned
908 // 0 means immediate activity 844 // 0 means immediate activity
909 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM, 845 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM,
910 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames 846 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames
911 // if MS can go in deep sleep 847 // if MS can go in deep sleep
912 if ( !OSload 848 if ( !min_time
913 || !HWtimer 849 || !HWtimer
914 || !min_time_gauging 850 || !min_time_gauging
915 || ((sleep_mode != CLOCK_STOP) && ((why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (why_big_sleep == BIG_SLEEP_DUE_TO_SIM))) 851 || (sleep_mode != CLOCK_STOP)
916 #if (OP_BT == 1) 852 #if (OP_BT == 1)
917 || !hci_ll_status 853 || !hci_ll_status
918 #endif 854 #endif
919 ) 855 )
920 { 856 {
921 857
922
923
924 #if (OP_L1_STANDALONE == 0)
925 /*GC_Wakeup(); OMAPS00134004*/
926 #endif
927 858
928 #if (CODE_VERSION != SIMULATION) 859 #if (CODE_VERSION != SIMULATION)
929 OS_system_Unprotect(); 860 OS_system_Unprotect();
930 // free System structure 861 // free System structure
931 // Enable all IRQ 862 // Enable all IRQ
932 INT_EnableIRQ(); 863 INT_EnableIRQ();
933 // Wake up UART 864 // Wake up UART
934 #if (GSM_IDLE_RAM != 0)
935 // Traffic controller has to be enabled before calling SER_WakeUpUarts
936 // as this function can access the external RAM.
937 // Reset the flag that will indicates if an interrup will put the traffic
938 // controller ON during that time.
939 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
940 if (!READ_TRAFFIC_CONT_STATE)
941 {
942 flag_traffic_controller_state = 1;
943 CSMI_TrafficControllerOn();
944 }
945 #endif
946 865
947 SER_WakeUpUarts(); // Wake up Uarts 866 SER_WakeUpUarts(); // Wake up Uarts
948 867
949 #if (GSM_IDLE_RAM != 0) 868 #endif
950 // The traffic controller state shall be restored as it was before
951 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
952 // in between and activated the traffic controller.
953 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
954 {
955 CSMI_TrafficControllerOff();
956 }
957 flag_traffic_controller_state = 0;
958 #endif
959 #endif
960 #if 0 /* FreeCalypso TCS211 reconstruction */
961 l1_trace_fail_sleep(FAIL_SLEEP_OSTIMERGAUGE, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
962 #endif
963 return; 869 return;
964 } 870 }
965 //================================================= 871 //=================================================
966 // Select sleep duration .... 872 // Select sleep duration ....
967 //================================================= 873 //=================================================
968 // remember: -1 means no activity planned 874 // remember: -1 means no activity planned
969 min_time = OSload;
970 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31 875 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31
971 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task, 876 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task,
972 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF 877 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF
973 uw32_store_next_time = l1a_l1s_com.time_to_next_l1s_task; 878
974 879 if (min_time == -1) min_time = l1a_l1s_com.time_to_next_l1s_task;
975 if (min_time == -1) min_time = (WORD32)uw32_store_next_time; 880 else MIN(min_time, l1a_l1s_com.time_to_next_l1s_task)
976 //else MIN(min_time, (WORD32)l1a_l1s_com.time_to_next_l1s_task)
977 else
978 {
979 if(min_time > l1a_l1s_com.time_to_next_l1s_task) min_time = uw32_store_next_time & 0x7FFFFFFF;
980 //else min_time = min_time;
981 }
982 if (HWtimer != -1) MIN(min_time, HWtimer) 881 if (HWtimer != -1) MIN(min_time, HWtimer)
983 if (min_time_gauging != -1) MIN(min_time, min_time_gauging) 882 if (min_time_gauging != -1) MIN(min_time, min_time_gauging)
984 883
985 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3) 884 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
986 // to trace the Wake up source 885 // to trace the Wake up source
987 // depending of min_time choose the wakeup_type 886 // depending of min_time choose the wakeup_type
988 wakeup_type = WAKEUP_FOR_L1_TASK; 887 wakeup_type = WAKEUP_FOR_OS_TASK;
989 if (min_time == l1a_l1s_com.time_to_next_l1s_task) wakeup_type = WAKEUP_FOR_L1_TASK; 888 if (min_time == l1a_l1s_com.time_to_next_l1s_task) wakeup_type = WAKEUP_FOR_L1_TASK;
990 if (min_time == HWtimer) wakeup_type = WAKEUP_FOR_HW_TIMER_TASK; 889 if (min_time == HWtimer) wakeup_type = WAKEUP_FOR_HW_TIMER_TASK;
991 if (min_time == min_time_gauging) wakeup_type = WAKEUP_FOR_GAUGING_TASK; 890 if (min_time == min_time_gauging) wakeup_type = WAKEUP_FOR_GAUGING_TASK;
992 if (min_time == OSload) wakeup_type = WAKEUP_FOR_OS_TASK;
993 #endif 891 #endif
994 892
995 //================================================= 893 //=================================================
996 // Choose DEEP or BIG SLEEP 894 // Choose DEEP or BIG SLEEP
997 //================================================= 895 //=================================================
1013 l1s.pw_mgr.sleep_performed = CLOCK_STOP; 911 l1s.pw_mgr.sleep_performed = CLOCK_STOP;
1014 else 912 else
1015 { 913 {
1016 // BIG SLEEP is chosen : check the reason 914 // BIG SLEEP is chosen : check the reason
1017 l1s.pw_mgr.sleep_performed = FRAME_STOP; 915 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1018 if ((l1s.pw_mgr.enough_gaug != TRUE) && (l1a_l1s_com.mode != CS_MODE0)) 916 if (l1s.pw_mgr.enough_gaug != TRUE)
1019 why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING; 917 why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING;
1020 else 918 else
1021 why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES; 919 why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES;
1022 } 920 }
1023 } 921 }
1030 928
1031 929
1032 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7)) 930 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7))
1033 { 931 {
1034 #if (CODE_VERSION != SIMULATION) 932 #if (CODE_VERSION != SIMULATION)
1035 OS_system_Unprotect(); // free System structure 933 OS_system_Unprotect(); // free System structure
1036 INT_EnableIRQ(); // Enable all IRQ 934 INT_EnableIRQ(); // Enable all IRQ
1037 #if (GSM_IDLE_RAM != 0) 935
1038 // Traffic controller has to be enabled before calling SER_WakeUpUarts 936 SER_WakeUpUarts(); // Wake up Uarts
1039 // as this function can access the external RAM. 937
1040 // Reset the flag that will indicates if an interrup will put the traffic
1041 // controller ON during that time.
1042 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
1043 if (!READ_TRAFFIC_CONT_STATE)
1044 {
1045 flag_traffic_controller_state = 1;
1046 CSMI_TrafficControllerOn();
1047 }
1048 #endif
1049
1050
1051 SER_WakeUpUarts(); // Wake up Uarts
1052
1053
1054
1055 #if (GSM_IDLE_RAM != 0)
1056 // The traffic controller state shall be restored as it was before
1057 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1058 // in between and activated the traffic controller.
1059 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
1060 {
1061 CSMI_TrafficControllerOff();
1062 }
1063 flag_traffic_controller_state = 0;
1064 #endif
1065 #endif // NOT SIMULATION 938 #endif // NOT SIMULATION
1066 return; 939 return;
1067 } 940 }
1068 941
1069 // update previous sleep 942 // update previous sleep
1101 // If we have come in here during the inactive period of cell 974 // If we have come in here during the inactive period of cell
1102 // selection, then load the ULPD timers with default values 975 // selection, then load the ULPD timers with default values
1103 // (used when the MS lost the network: in this case the deep sleep may be used) 976 // (used when the MS lost the network: in this case the deep sleep may be used)
1104 if (l1a_l1s_com.mode == CS_MODE0) 977 if (l1a_l1s_com.mode == CS_MODE0)
1105 { 978 {
1106 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE*8,DEFAULT_32KHZ_VALUE); 979 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE, DEFAULT_32KHZ_VALUE);
1107 } 980 }
1108 } 981 }
1109 982
1110 983
1111 //============================================== 984 //==============================================
1112 // disable DPLL (do not provide clk to DSP & RIF (RIF)) 985 // disable DPLL (do not provide clk to DSP & RIF (RIF))
1113 //============================================== 986 //==============================================
1114 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)) 987 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1115 // disable DPLL (do not provide clk to DSP & RIF (Bridge)) 988 // disable DPLL (do not provide clk to DSP & RIF (Bridge))
1116 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS ; /* CLKM_BRIDGE_DIS removed by Ranga*/ 989 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS | CLKM_BRIDGE_DIS;
1117 #endif 990 #endif
1118 991
1119 //============================================== 992 //==============================================
1120 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB) 993 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
1121 //============================================== 994 //==============================================
1157 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0) 1030 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
1158 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 1031 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1159 { 1032 {
1160 // DEEP SLEEP -> need time to setup afc and rf 1033 // DEEP SLEEP -> need time to setup afc and rf
1161 wake_up_time = min_time - l1_config.params.setup_afc_and_rf; 1034 wake_up_time = min_time - l1_config.params.setup_afc_and_rf;
1162 #if (CODE_VERSION == NOT_SIMULATION)
1163 // Sleep one more TDMA - this is done as part of merging init and TPU control
1164 wake_up_time += 1;
1165 #endif
1166
1167 } 1035 }
1168 else 1036 else
1169 // BIG SLEEP 1037 // BIG SLEEP
1170 wake_up_time = min_time - 1; 1038 wake_up_time = min_time - 1;
1171 1039
1218 arm7_deep_sleep(); 1086 arm7_deep_sleep();
1219 #else // NO OP_WCP 1087 #else // NO OP_WCP
1220 #if (W_A_CALYPSO_BUG_01435 == 1) 1088 #if (W_A_CALYPSO_BUG_01435 == 1)
1221 f_arm_sleep_cmd(DEEP_SLEEP); 1089 f_arm_sleep_cmd(DEEP_SLEEP);
1222 #else 1090 #else
1223 //EMIF_SetConfReg ( 0, 0, 2 ,1 ,0);
1224 asm(" NOP");
1225 asm(" NOP");
1226 asm(" NOP");
1227 asm(" NOP");
1228 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode 1091 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode
1229 asm(" NOP");
1230 asm(" NOP");
1231 asm(" NOP");
1232 asm(" NOP");
1233 // set deep sleep mode in case it is not set back by hardware
1234 *((volatile UWORD16 *)CLKM_ARM_CLK) |= (CLKM_DEEP_SLEEP);
1235
1236 //EMIF_SetConfReg ( 0, 0, 2 ,0 ,0);
1237 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= 0xFFFF; // set deep sleep mode
1238 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // For Debug only
1239
1240
1241 #endif 1092 #endif
1242 #endif // OP_WCP 1093 #endif // OP_WCP
1243 } 1094 }
1244 else 1095 else
1245 { 1096 {
1378 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) 1229 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
1379 l1s_trace_mftab(); 1230 l1s_trace_mftab();
1380 #endif 1231 #endif
1381 #endif 1232 #endif
1382 } 1233 }
1383 int_id = 0;
1384 #endif 1234 #endif
1385 1235
1386 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) 1236 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1387 trace_info.sleep_performed = TRUE; 1237 trace_info.sleep_performed = TRUE;
1388 #endif 1238 #endif