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comparison chipsetsw/layer1/audio_cfile/l1audio_sync.c @ 271:473405ab23a3

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l1audio_sync.c: more enum fixes
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 13 Mar 2017 06:11:12 +0000
parents ac232fc44bfc
children 82a9407a75ce
comparison
equal deleted inserted replaced
270:ac232fc44bfc 271:473405ab23a3
1740 enum states 1740 enum states
1741 { 1741 {
1742 M0_INACTIVE = 0, 1742 M0_INACTIVE = 0,
1743 #if (L1_AUDIO_MCU_ONOFF == 1) 1743 #if (L1_AUDIO_MCU_ONOFF == 1)
1744 M0_WAIT_AUDIO_START = 1, 1744 M0_WAIT_AUDIO_START = 1,
1745 #endif
1746 M0_WAIT_DSP_START = 2, 1745 M0_WAIT_DSP_START = 2,
1747 M0_WAIT_COUNTER_EQUAL_0 = 3, 1746 M0_WAIT_COUNTER_EQUAL_0 = 3,
1748 M0_WAIT_DESCRIPTION_START = 4, 1747 M0_WAIT_DESCRIPTION_START = 4,
1749 M0_WAIT_END_MELO = 5 1748 M0_WAIT_END_MELO = 5
1749 #else
1750 M0_WAIT_DSP_START = 1,
1751 M0_WAIT_COUNTER_EQUAL_0 = 2,
1752 M0_WAIT_DESCRIPTION_START = 3,
1753 M0_WAIT_END_MELO = 4
1754 #endif
1750 }; 1755 };
1751 1756
1752 UWORD8 *state = &l1s.audio_state[L1S_MELODY0_STATE]; 1757 UWORD8 *state = &l1s.audio_state[L1S_MELODY0_STATE];
1753 xSignalHeaderRec *conf_msg; 1758 xSignalHeaderRec *conf_msg;
1754 UWORD8 i, load_size; 1759 UWORD8 i, load_size;
2070 enum states 2075 enum states
2071 { 2076 {
2072 M1_INACTIVE = 0, 2077 M1_INACTIVE = 0,
2073 #if (L1_AUDIO_MCU_ONOFF == 1) 2078 #if (L1_AUDIO_MCU_ONOFF == 1)
2074 M1_WAIT_AUDIO_START = 1, 2079 M1_WAIT_AUDIO_START = 1,
2075 #endif
2076 M1_WAIT_DSP_START = 2, 2080 M1_WAIT_DSP_START = 2,
2077 M1_WAIT_COUNTER_EQUAL_0 = 3, 2081 M1_WAIT_COUNTER_EQUAL_0 = 3,
2078 M1_WAIT_DESCRIPTION_START = 4, 2082 M1_WAIT_DESCRIPTION_START = 4,
2079 M1_WAIT_END_MELO = 5 2083 M1_WAIT_END_MELO = 5
2084 #else
2085 M1_WAIT_DSP_START = 1,
2086 M1_WAIT_COUNTER_EQUAL_0 = 2,
2087 M1_WAIT_DESCRIPTION_START = 3,
2088 M1_WAIT_END_MELO = 4
2089 #endif
2080 }; 2090 };
2081 2091
2082 UWORD8 *state = &l1s.audio_state[L1S_MELODY1_STATE]; 2092 UWORD8 *state = &l1s.audio_state[L1S_MELODY1_STATE];
2083 xSignalHeaderRec *conf_msg; 2093 xSignalHeaderRec *conf_msg;
2084 UWORD8 i, load_size; 2094 UWORD8 i, load_size;
2397 enum states 2407 enum states
2398 { 2408 {
2399 IDLE = 0, 2409 IDLE = 0,
2400 #if (L1_AUDIO_MCU_ONOFF == 1) 2410 #if (L1_AUDIO_MCU_ONOFF == 1)
2401 WAIT_AUDIO_ON = 1, 2411 WAIT_AUDIO_ON = 1,
2402 #endif
2403 WAIT_DSP_START = 2, 2412 WAIT_DSP_START = 2,
2404 WAIT_DSP_REQUEST = 3, 2413 WAIT_DSP_REQUEST = 3,
2405 WAIT_DSP_STOP = 4 2414 WAIT_DSP_STOP = 4
2415 #else
2416 WAIT_DSP_START = 1,
2417 WAIT_DSP_REQUEST = 2,
2418 WAIT_DSP_STOP = 3
2419 #endif
2406 }; 2420 };
2407 2421
2408 UWORD8 *state = &l1s.audio_state[L1S_VM_PLAY_STATE]; 2422 UWORD8 *state = &l1s.audio_state[L1S_VM_PLAY_STATE];
2409 xSignalHeaderRec *conf_msg; 2423 xSignalHeaderRec *conf_msg;
2410 UWORD16 sample_header; 2424 UWORD16 sample_header;
2637 enum states 2651 enum states
2638 { 2652 {
2639 IDLE = 0, 2653 IDLE = 0,
2640 #if (L1_AUDIO_MCU_ONOFF == 1) 2654 #if (L1_AUDIO_MCU_ONOFF == 1)
2641 WAIT_AUDIO_ON = 1, 2655 WAIT_AUDIO_ON = 1,
2642 #endif // L1_AUDIO_MCU_ONOFF
2643 WAIT_DSP_START = 2, 2656 WAIT_DSP_START = 2,
2644 WAIT_DSP_SAMPLE = 3, 2657 WAIT_DSP_SAMPLE = 3,
2645 WAIT_DSP_STOP = 4 2658 WAIT_DSP_STOP = 4
2659 #else
2660 WAIT_DSP_START = 1,
2661 WAIT_DSP_SAMPLE = 2,
2662 WAIT_DSP_STOP = 3
2663 #endif // L1_AUDIO_MCU_ONOFF
2646 }; 2664 };
2647 2665
2648 UWORD8 *state = &l1s.audio_state[L1S_VM_RECORD_STATE]; 2666 UWORD8 *state = &l1s.audio_state[L1S_VM_RECORD_STATE];
2649 xSignalHeaderRec *conf_msg; 2667 xSignalHeaderRec *conf_msg;
2650 UWORD8 size; 2668 UWORD8 size;
2875 enum states 2893 enum states
2876 { 2894 {
2877 IDLE = 0, 2895 IDLE = 0,
2878 #if (L1_AUDIO_MCU_ONOFF == 1) 2896 #if (L1_AUDIO_MCU_ONOFF == 1)
2879 WAIT_AUDIO_ON = 1, 2897 WAIT_AUDIO_ON = 1,
2880 #endif
2881 WAIT_DEDIC_SPEECH_MODE = 2, 2898 WAIT_DEDIC_SPEECH_MODE = 2,
2882 WAIT_TONE_UL_START = 3, 2899 WAIT_TONE_UL_START = 3,
2883 WAIT_TONE_UL_STOP = 4 2900 WAIT_TONE_UL_STOP = 4
2901 #else
2902 WAIT_DEDIC_SPEECH_MODE = 1,
2903 WAIT_TONE_UL_START = 2,
2904 WAIT_TONE_UL_STOP = 3
2905 #endif
2884 }; 2906 };
2885 2907
2886 UWORD8 *state = &l1s.audio_state[L1S_TONE_UL_STATE]; 2908 UWORD8 *state = &l1s.audio_state[L1S_TONE_UL_STATE];
2887 2909
2888 switch(*state) 2910 switch(*state)
3392 enum states 3414 enum states
3393 { 3415 {
3394 IDLE = 0, 3416 IDLE = 0,
3395 #if (L1_AUDIO_MCU_ONOFF == 1) 3417 #if (L1_AUDIO_MCU_ONOFF == 1)
3396 WAIT_AUDIO_ON = 1, 3418 WAIT_AUDIO_ON = 1,
3397 #endif
3398 WAIT_DSP_START = 2, 3419 WAIT_DSP_START = 2,
3399 WAIT_DSP_REQUEST = 3, 3420 WAIT_DSP_REQUEST = 3,
3400 WAIT_DSP_STOP = 4 3421 WAIT_DSP_STOP = 4
3422 #else
3423 WAIT_DSP_START = 1,
3424 WAIT_DSP_REQUEST = 2,
3425 WAIT_DSP_STOP = 3
3426 #endif
3401 }; 3427 };
3402 3428
3403 UWORD8 *state = &l1s.audio_state[L1S_VM_AMR_PLAY_STATE]; 3429 UWORD8 *state = &l1s.audio_state[L1S_VM_AMR_PLAY_STATE];
3404 xSignalHeaderRec *conf_msg; 3430 xSignalHeaderRec *conf_msg;
3405 UWORD8 sample_header; 3431 UWORD8 sample_header;
3698 enum states 3724 enum states
3699 { 3725 {
3700 IDLE = 0, 3726 IDLE = 0,
3701 #if (L1_AUDIO_MCU_ONOFF == 1) 3727 #if (L1_AUDIO_MCU_ONOFF == 1)
3702 WAIT_AUDIO_ON = 1, 3728 WAIT_AUDIO_ON = 1,
3703 #endif
3704 WAIT_DSP_START = 2, 3729 WAIT_DSP_START = 2,
3705 WAIT_DSP_SAMPLE = 3, 3730 WAIT_DSP_SAMPLE = 3,
3706 WAIT_DSP_STOP = 4 3731 WAIT_DSP_STOP = 4
3732 #else
3733 WAIT_DSP_START = 1,
3734 WAIT_DSP_SAMPLE = 2,
3735 WAIT_DSP_STOP = 3
3736 #endif
3707 }; 3737 };
3708 3738
3709 UWORD8 *state = &l1s.audio_state[L1S_VM_AMR_RECORD_STATE]; 3739 UWORD8 *state = &l1s.audio_state[L1S_VM_AMR_RECORD_STATE];
3710 xSignalHeaderRec *conf_msg; 3740 xSignalHeaderRec *conf_msg;
3711 UWORD8 sample_header; 3741 UWORD8 sample_header;