FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cust0/l1_rf12.c @ 202:47ac87c0bc1b

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l1_cust.c & l1_rf12.c: s/ANALOG/ANLG_FAM/
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 08 Jun 2016 05:25:23 +0000
parents 87fffabe4aec
children 5dbf46894dab
comparison
equal deleted inserted replaced
201:fc26218d598a 202:47ac87c0bc1b
1841 }; 1841 };
1842 1842
1843 /*------------------------------------------*/ 1843 /*------------------------------------------*/
1844 /* ABB Initialization words 1844 /* ABB Initialization words
1845 /*------------------------------------------*/ 1845 /*------------------------------------------*/
1846 #if (ANALOG == 1) 1846 #if (ANLG_FAM == 1)
1847 UWORD16 abb[ABB_TABLE_SIZE] = 1847 UWORD16 abb[ABB_TABLE_SIZE] =
1848 { 1848 {
1849 C_AFCCTLADD, // Value at reset 1849 C_AFCCTLADD, // Value at reset
1850 C_VBUR, // Uplink gain amp 0dB, Sidetone gain to mute 1850 C_VBUR, // Uplink gain amp 0dB, Sidetone gain to mute
1851 C_VBDR, // Downlink gain amp 0dB, Volume control 0 dB 1851 C_VBDR, // Downlink gain amp 0dB, Volume control 0 dB
1856 C_DAI_ON_OFF, // value at reset 1856 C_DAI_ON_OFF, // value at reset
1857 C_AUXDAC, // value at reset 1857 C_AUXDAC, // value at reset
1858 C_VBCR, // VULSWITCH=0, VDLAUX=1, VDLEAR=1 1858 C_VBCR, // VULSWITCH=0, VDLAUX=1, VDLEAR=1
1859 C_APCDEL // value at reset 1859 C_APCDEL // value at reset
1860 }; 1860 };
1861 #elif (ANALOG == 2) 1861 #elif (ANLG_FAM == 2)
1862 UWORD16 abb[ABB_TABLE_SIZE] = 1862 UWORD16 abb[ABB_TABLE_SIZE] =
1863 { 1863 {
1864 C_AFCCTLADD, 1864 C_AFCCTLADD,
1865 C_VBUR, 1865 C_VBUR,
1866 C_VBDR, 1866 C_VBDR,
1875 C_VBCR2, 1875 C_VBCR2,
1876 C_APCDEL, 1876 C_APCDEL,
1877 C_APCDEL2 1877 C_APCDEL2
1878 }; 1878 };
1879 1879
1880 #elif (ANALOG == 3) 1880 #elif (ANLG_FAM == 3)
1881 UWORD16 abb[ABB_TABLE_SIZE] = 1881 UWORD16 abb[ABB_TABLE_SIZE] =
1882 { 1882 {
1883 C_AFCCTLADD, 1883 C_AFCCTLADD,
1884 C_VBUR, 1884 C_VBUR,
1885 C_VBDR, 1885 C_VBDR,