FreeCalypso > hg > tcs211-l1-reconst
comparison chipsetsw/drivers/drv_core/inth/niq.c @ 0:509db1a7b7b8
initial import: leo2moko-r1
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Mon, 01 Jun 2015 03:24:05 +0000 |
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1 /****************************************************************************** | |
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION | |
3 | |
4 Property of Texas Instruments -- For Unrestricted Internal Use Only | |
5 Unauthorized reproduction and/or distribution is strictly prohibited. This | |
6 product is protected under copyright law and trade secret law as an | |
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All | |
8 rights reserved. | |
9 | |
10 | |
11 Filename : niq.c | |
12 | |
13 Description : Nucleus IQ initializations | |
14 | |
15 Project : Drivers | |
16 | |
17 Author : proussel@ti.com Patrick Roussel. | |
18 | |
19 Version number : 1.16 | |
20 | |
21 Date : 05/23/03 | |
22 | |
23 Previous delta : 12/19/00 14:22:24 | |
24 | |
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.niq.c | |
26 | |
27 Sccs Id (SID) : '@(#) niq.c 1.8 01/30/01 10:22:21 ' | |
28 *******************************************************************************/ | |
29 | |
30 #include "l1sw.cfg" | |
31 | |
32 #if (OP_L1_STANDALONE == 0) | |
33 #include "debug.cfg" | |
34 #endif | |
35 #include "chipset.cfg" | |
36 #include "rf.cfg" | |
37 | |
38 #if (OP_L1_STANDALONE == 0) | |
39 #include "main/sys_types.h" | |
40 #else | |
41 #include "sys_types.h" | |
42 #endif | |
43 #include "memif/mem.h" | |
44 #include "rhea/rhea_arm.h" | |
45 #if (CHIPSET != 12) | |
46 #include "inth.h" | |
47 #endif | |
48 #include "iq.h" | |
49 | |
50 | |
51 #if (CHIPSET != 12) | |
52 extern SYS_FUNC irqHandlers[IQ_NUM_INT]; | |
53 | |
54 /*--------------------------------------------------------------*/ | |
55 /* IQ_Prty[IQ_NUM_INT] */ | |
56 /*--------------------------------------------------------------*/ | |
57 /* Parameters : none */ | |
58 /* Return : none */ | |
59 /* Functionality : IRQ priorities 0xFF means interrupt is masked*/ | |
60 /*--------------------------------------------------------------*/ | |
61 | |
62 #if (CHIPSET == 4) | |
63 unsigned char IQ_Prty[IQ_NUM_INT] = | |
64 { | |
65 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
66 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, | |
67 | |
68 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
69 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03, | |
70 | |
71 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 | |
72 0x07, 0xFF, 0x02, 0x03 | |
73 | |
74 }; | |
75 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) | |
76 unsigned char IQ_Prty[IQ_NUM_INT] = | |
77 { | |
78 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
79 #if (RF_FAM==35) | |
80 0x01, 0x02, 0x02, 0x0F, 0x00, 0x04, 0x07, 0x02, | |
81 #else | |
82 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, | |
83 #endif | |
84 | |
85 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
86 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03, | |
87 | |
88 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23 | |
89 #if (OP_L1_STANDALONE == 0) | |
90 0x07, 0xFF, 0x02, 0x03, 0x0F, 0xFF, 0xFF, 0xFF, | |
91 #else | |
92 0x07, 0xFF, 0x02, 0x03, 0xFF, 0xFF, 0xFF, 0xFF, | |
93 #endif | |
94 | |
95 // AIRQ24 | |
96 0xFF | |
97 | |
98 }; | |
99 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) | |
100 unsigned char IQ_Prty[IQ_NUM_INT] = | |
101 { | |
102 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
103 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, | |
104 | |
105 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
106 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03, | |
107 | |
108 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 | |
109 0x07, 0xFF, 0x02, 0x03, 0xFF | |
110 | |
111 }; | |
112 | |
113 #else | |
114 unsigned char IQ_Prty[IQ_NUM_INT] = | |
115 { | |
116 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
117 0x01, 0x02, 0x02, 0xFF, 0x00, 0x04, 0x07, 0x02, | |
118 | |
119 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
120 0x01, 0x03, 0x03, 0x00, 0x08, 0x05, 0x06, 0x03 | |
121 | |
122 }; | |
123 #endif | |
124 | |
125 | |
126 /*--------------------------------------------------------------*/ | |
127 /* IQ_LEVEL[IQ_NUM_INT] */ | |
128 /*--------------------------------------------------------------*/ | |
129 /* Parameters : none */ | |
130 /* Return : none */ | |
131 /* Functionality : IRQ sensitivity */ | |
132 /* 1: falling edge 0: low level (default) */ | |
133 /*--------------------------------------------------------------*/ | |
134 | |
135 #if (CHIPSET == 4) | |
136 unsigned char IQ_LEVEL[IQ_NUM_INT] = | |
137 { | |
138 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
139 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, | |
140 | |
141 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
142 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01, | |
143 | |
144 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 | |
145 0x01, 0x01, 0x00, 0x00 | |
146 | |
147 }; | |
148 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) | |
149 unsigned char IQ_LEVEL[IQ_NUM_INT] = | |
150 { | |
151 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
152 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, | |
153 | |
154 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
155 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01, | |
156 | |
157 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23 | |
158 #if (OP_L1_STANDALONE == 0) | |
159 0x01, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, | |
160 #else | |
161 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
162 #endif | |
163 | |
164 // AIRQ24 | |
165 0x00 | |
166 | |
167 }; | |
168 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) | |
169 unsigned char IQ_LEVEL[IQ_NUM_INT] = | |
170 { | |
171 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
172 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, | |
173 | |
174 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
175 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01, | |
176 | |
177 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 | |
178 0x01, 0x01, 0x00, 0x00, 0x00 | |
179 | |
180 }; | |
181 | |
182 #else | |
183 unsigned char IQ_LEVEL[IQ_NUM_INT] = | |
184 { | |
185 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
186 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, | |
187 | |
188 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
189 0x00, 0x01, 0x00, 0x01, 0x01, 0x01, 0x00, 0x01 | |
190 | |
191 }; | |
192 #endif | |
193 | |
194 | |
195 /*--------------------------------------------------------------*/ | |
196 /* IQ_FIQ_nIRQ[IQ_NUM_INT] */ | |
197 /*--------------------------------------------------------------*/ | |
198 /* Parameters : none */ | |
199 /* Return : none */ | |
200 /* Functionality : IRQ sensitivity */ | |
201 /* 0: falling edge 1: low level (default) */ | |
202 /*--------------------------------------------------------------*/ | |
203 | |
204 #if (CHIPSET == 4) | |
205 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = | |
206 { | |
207 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
208 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, | |
209 | |
210 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
211 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, | |
212 | |
213 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 | |
214 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ | |
215 | |
216 }; | |
217 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9)) | |
218 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = | |
219 { | |
220 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
221 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, | |
222 | |
223 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
224 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, | |
225 | |
226 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23 | |
227 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, | |
228 | |
229 // AIRQ24 | |
230 INTH_IRQ | |
231 | |
232 }; | |
233 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) | |
234 unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = | |
235 { | |
236 // AIRQ0 AIRQ1 AIRQ2 AIRQ3 AIRQ4 AIRQ5 AIRQ6 AIRQ7 | |
237 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, | |
238 | |
239 // AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA LEAD | |
240 INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, | |
241 | |
242 // AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 | |
243 INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ | |
244 | |
245 }; | |
246 | |
247 #endif | |
248 #endif /* (CHIPSET != 12)*/ | |
249 | |
250 /*--------------------------------------------------------------*/ | |
251 /* IQ_GetBuild */ | |
252 /*--------------------------------------------------------------*/ | |
253 /* Parameters : none */ | |
254 /* Return : Return library build number */ | |
255 /* Functionality : */ | |
256 /*--------------------------------------------------------------*/ | |
257 | |
258 unsigned IQ_GetBuild(void) | |
259 { | |
260 return(IQ_BUILD); | |
261 } | |
262 | |
263 #if (CHIPSET != 12) | |
264 /*--------------------------------------------------------------*/ | |
265 /* IQ_SetupInterrupts */ | |
266 /*--------------------------------------------------------------*/ | |
267 /* Parameters : none */ | |
268 /* Return : none */ | |
269 /* Functionality : Set IRQ interrupt levels and unmask */ | |
270 /*--------------------------------------------------------------*/ | |
271 | |
272 void IQ_SetupInterrupts(void) | |
273 { | |
274 int i; | |
275 char prty; | |
276 | |
277 /* Setup all interrupts to IRQ with different levels */ | |
278 for (i=INTH_TIMER;i<=IQ_NUM_INT;i++ ) | |
279 { | |
280 prty = IQ_Prty[i]; | |
281 if (prty != 0xFF) | |
282 { | |
283 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11)) | |
284 INTH_InitLevel(i, IQ_FIQ_nIRQ[i], prty, IQ_LEVEL[i]); | |
285 #else | |
286 INTH_InitLevel(i, INTH_IRQ, prty, IQ_LEVEL[i]); | |
287 #endif | |
288 } | |
289 INTH_DISABLEONEIT(i); | |
290 } | |
291 } | |
292 | |
293 /*--------------------------------------------------------------*/ | |
294 /* IQ_InitWaitState */ | |
295 /*--------------------------------------------------------------*/ | |
296 /* Parameters :rom, ram, spy, lcd, jtag */ | |
297 /* Return : none */ | |
298 /* Functionality : Init wait states */ | |
299 /*--------------------------------------------------------------*/ | |
300 | |
301 void IQ_InitWaitState(unsigned short rom, unsigned short ram, unsigned short spy, unsigned short lcd, unsigned short jtag) | |
302 { | |
303 volatile char ws; | |
304 | |
305 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS0; | |
306 ws &= ~WS_MASK; | |
307 ws |= rom; | |
308 * (volatile SYS_UWORD16 *) MEM_REG_nCS0 = ws; | |
309 | |
310 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS1; | |
311 ws &= ~WS_MASK; | |
312 ws |= ram; | |
313 * (volatile SYS_UWORD16 *) MEM_REG_nCS1 = ws; | |
314 | |
315 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS2; | |
316 ws &= ~WS_MASK; | |
317 ws |= spy; | |
318 * (volatile SYS_UWORD16 *) MEM_REG_nCS2 = ws; | |
319 | |
320 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS4; | |
321 ws &= ~WS_MASK; | |
322 ws |= lcd; | |
323 * (volatile SYS_UWORD16 *) MEM_REG_nCS4 = ws; | |
324 | |
325 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11)) | |
326 ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS5; | |
327 ws &= ~WS_MASK; | |
328 ws |= jtag; | |
329 * (volatile SYS_UWORD16 *) MEM_REG_nCS5 = ws; | |
330 #endif | |
331 | |
332 } | |
333 | |
334 void IQ_Unmask(unsigned irqNum) | |
335 { | |
336 INTH_ENABLEONEIT(irqNum); | |
337 } | |
338 | |
339 void IQ_Mask(unsigned irqNum) | |
340 { | |
341 INTH_DISABLEONEIT(irqNum); | |
342 } | |
343 | |
344 void IQ_MaskAll(void) | |
345 { | |
346 INTH_DISABLEALLIT; | |
347 } | |
348 | |
349 | |
350 #endif /* (CHIPSET != 12)*/ | |
351 | |
352 #if (OP_L1_STANDALONE == 0) | |
353 #if (CHIPSET == 12) | |
354 /* | |
355 * IQ_MaskAll is being used by TI Berlin's alr.lib and therefore needs to be | |
356 * patched for Calypso+. | |
357 */ | |
358 void IQ_MaskAll(void) | |
359 { | |
360 #include "sys_inth.h" | |
361 | |
362 F_INTH_DISABLE_ALL_IT; | |
363 } | |
364 #endif /* CHIPSET == 12 */ | |
365 #endif /* OP_L1_STANDALONE == 0 */ | |
366 | |
367 /* | |
368 * IQ_GetJtagId | |
369 * | |
370 * JTAG part identifier | |
371 */ | |
372 SYS_UWORD16 IQ_GetJtagId(void) | |
373 { | |
374 unsigned short v; | |
375 | |
376 v = *( (volatile unsigned short *) (MEM_JTAGID_PART)); | |
377 return(v); | |
378 } | |
379 | |
380 | |
381 | |
382 /* | |
383 * IQ_GetDeviceVersion | |
384 * | |
385 * Read from CLKM module | |
386 */ | |
387 SYS_UWORD16 IQ_GetDeviceVersion(void) | |
388 { | |
389 SYS_UWORD16 v; | |
390 | |
391 v = *( (volatile SYS_WORD16 *) (MEM_JTAGID_VER)); | |
392 return(v); | |
393 } | |
394 | |
395 | |
396 //// !!!! TO BE REMOVED IN NEXT CONDAT RELEASE >2.55 | |
397 /* | |
398 * IQ_GetDeviceVersion | |
399 * | |
400 * Read from CLKM module | |
401 */ | |
402 SYS_UWORD16 IQ_GetPoleStarVersion(void) | |
403 { | |
404 SYS_UWORD16 v; | |
405 | |
406 v = *( (volatile SYS_UWORD16 *) (MEM_JTAGID_VER)); | |
407 return(v); | |
408 } | |
409 | |
410 | |
411 | |
412 /* | |
413 * IQ_RamBasedLead | |
414 * | |
415 * Returns TRUE if the LEAD has RAM and needs to be downloaded | |
416 * | |
417 */ | |
418 | |
419 SYS_BOOL IQ_RamBasedLead(void) | |
420 { | |
421 unsigned short id; | |
422 | |
423 id = IQ_GetJtagId(); | |
424 | |
425 #if (CHIPSET != 7) | |
426 return ((id == SATURN || id == HERCRAM || id == 0xB2AC) ? 1 : 0); | |
427 #else | |
428 // Calypso G2 rev. A and Samson share the same JTAG ID | |
429 return (0); | |
430 #endif | |
431 } | |
432 | |
433 /* | |
434 * IQ_Power | |
435 * | |
436 * Switch-on or off the board | |
437 * | |
438 * Parameters : BOOL power : 1 to power-on (maintain power) | |
439 * 0 to power-off | |
440 * | |
441 * See A-Sample board specification | |
442 */ | |
443 void IQ_Power(SYS_UWORD8 power) | |
444 { | |
445 // This is only implemented for the A-Sample | |
446 } | |
447 | |
448 /* | |
449 * IQ_GetRevision | |
450 * | |
451 * Silicon revision - Read from JTAG version code | |
452 */ | |
453 SYS_UWORD16 IQ_GetRevision(void) | |
454 { | |
455 unsigned short v; | |
456 | |
457 v = *( (volatile unsigned short *) (MEM_JTAGID_VER)); | |
458 return(v); | |
459 } | |
460 | |
461 #if (OP_L1_STANDALONE == 0) | |
462 #if (TI_PROFILER == 1) | |
463 /* | |
464 * IQ_InitLevel | |
465 * | |
466 * Parameters : interrupt, FIQ_nIRQ, priority, edge | |
467 * Return : none | |
468 * Functionality : initialize Interrupt Level Registers | |
469 */ | |
470 | |
471 void IQ_InitLevel ( SYS_UWORD16 inputInt, | |
472 SYS_UWORD16 FIQ_nIRQ, | |
473 SYS_UWORD16 priority, | |
474 SYS_UWORD16 edge ) | |
475 { | |
476 volatile SYS_UWORD16 *inthLevelReg = (SYS_UWORD16 *) INTH_EXT_REG; | |
477 | |
478 inthLevelReg = inthLevelReg + inputInt; | |
479 | |
480 *inthLevelReg = (FIQ_nIRQ | (priority << 6) | (edge << 1)); | |
481 } | |
482 | |
483 #endif /* TI_PROFILER == 1 */ | |
484 #endif /* OP_L1_STANDALONE == 0 */ |