FreeCalypso > hg > tcs211-l1-reconst
comparison chipsetsw/layer1/include/l1_confg.h @ 0:509db1a7b7b8
initial import: leo2moko-r1
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Mon, 01 Jun 2015 03:24:05 +0000 |
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-1:000000000000 | 0:509db1a7b7b8 |
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1 /************* Revision Controle System Header ************* | |
2 * GSM Layer 1 software | |
3 * L1_CONFG.H | |
4 * | |
5 * Filename l1_confg.h | |
6 * Copyright 2003 (C) Texas Instruments | |
7 * | |
8 ************* Revision Controle System Header *************/ | |
9 | |
10 #ifndef __L1_CONFG_H__ | |
11 #define __L1_CONFG_H__ | |
12 | |
13 #ifndef _WINDOWS | |
14 #include "l1sw.cfg" // Configuration Software | |
15 #include "board.cfg" | |
16 #include "chipset.cfg" | |
17 #include "rf.cfg" | |
18 #include "swconfig.cfg" | |
19 #include "sys.cfg" | |
20 #endif | |
21 | |
22 // Traces... | |
23 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART | |
24 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack | |
25 // TRACE_TYPE == 1 -> L1/L3 interface trace | |
26 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011... | |
27 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace | |
28 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack | |
29 // TRACE_TYPE == 5 -> trace for full simulation | |
30 // TRACE_TYPE == 6 -> CPU load trace for hisr | |
31 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on | |
32 // UART at 38400 bps => | |
33 // format : <hisr cpu value in microseconds> <frame number> | |
34 | |
35 // Code PB reported workaround | |
36 //------------------------------ | |
37 | |
38 | |
39 // Code Version possible choices | |
40 //------------------------------ | |
41 #define SIMULATION 1 | |
42 #define NOT_SIMULATION 2 | |
43 | |
44 // RCL functions Version possible choices | |
45 //------------------------------ | |
46 #define POLL_FORCED 0 | |
47 #define RLC_SCENARIO 1 | |
48 #define MODEM_FLOW 2 | |
49 | |
50 // possible choices for UART trace output | |
51 //------------------------------ | |
52 #define MODEM_UART 0 | |
53 #define IRDA_UART 1 | |
54 #if (CHIPSET == 12) | |
55 #define MODEM2_UART 2 | |
56 #endif | |
57 | |
58 //============ | |
59 // CODE CHOICE | |
60 //============ | |
61 #if (OP_L1_STANDALONE==0) | |
62 #define CODE_VERSION NOT_SIMULATION | |
63 #else // OP_L1_STANDALONE | |
64 #ifdef WIN32 | |
65 #define CODE_VERSION SIMULATION | |
66 #else // WIN32 | |
67 #define CODE_VERSION NOT_SIMULATION | |
68 #endif // WIN32 | |
69 #endif // OP_L1_STANDALONE | |
70 | |
71 //--------------------------------------------------------------------------------- | |
72 // Test with full simulation. | |
73 //--------------------------------------------------------------------------------- | |
74 #if (CODE_VERSION == SIMULATION) | |
75 | |
76 // Test Scenari... | |
77 #define SCENARIO_FILE 1 // Test Scenario comes from input files. | |
78 #define SCENARIO_MEM 0 // Test Scenario comes from RAM. | |
79 | |
80 // Traces... | |
81 #undef TRACE_TYPE | |
82 #define TRACE_TYPE 5 | |
83 #define LOGFILE_TRACE 1 // trace in an output logfile | |
84 #define FLOWCHART 0 // Message sequence/flow chart trace. | |
85 #define NUCLEUS_TRACE 0 // Nucleus error trace | |
86 #define EOTD_TRACE 1 // EOTD log trace | |
87 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error | |
88 | |
89 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible. | |
90 | |
91 // Control algorithms... | |
92 #define AFC_ALGO 1 // AFC algorithm. | |
93 #define TOA_ALGO 1 // TOA algorithm. | |
94 #define AGC_ALGO 1 // AGC algorithm. | |
95 #define TA_ALGO 0 // TA (Timing Advance) algorithm. | |
96 #undef VCXO_ALGO | |
97 #define VCXO_ALGO 0 // VCXO algo | |
98 #undef DCO_ALGO | |
99 #define DCO_ALGO 0 // DCO algo (TIDE) | |
100 #undef ORDER2_TX_TEMP_CAL | |
101 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection | |
102 | |
103 | |
104 #define FACCH_TEST 0 // FACCH test enabled. | |
105 | |
106 #define ADC_TIMER_ON 0 // Timer for ADC measurements | |
107 #define AFC_ON 1 // Enable of the Omega AFC module | |
108 | |
109 #define AUDIO_TASK 1 // Enable the L1 audio features | |
110 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1) | |
111 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1) | |
112 | |
113 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) | |
114 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401 | |
115 #define TTY_SYNC_MCU_2 1 // | |
116 #define L1_GTT_FIFO_TEST_ATOMIC 0 // | |
117 #define NEW_WKA_PATCH 0 | |
118 #define OPTIMISED 1 | |
119 | |
120 #define L1_RECOVERY 0 // L1 recovery | |
121 | |
122 #undef L1_GPRS | |
123 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities | |
124 | |
125 #undef AMR | |
126 #define AMR 1 // AMR version 1.0 supported | |
127 | |
128 #undef L1_12NEIGH | |
129 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells | |
130 | |
131 #undef L1_GTT | |
132 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation | |
133 | |
134 #undef OP_L1_STANDALONE | |
135 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone | |
136 | |
137 #undef OP_RIV_AUDIO | |
138 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio | |
139 | |
140 #undef OP_WCP | |
141 #define OP_WCP 0 // No WCP integration | |
142 //--------------------------------------------------------------------------------- | |
143 // Test with H/W platform. | |
144 //--------------------------------------------------------------------------------- | |
145 #elif (CODE_VERSION == NOT_SIMULATION) | |
146 | |
147 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1) | |
148 // Work around about Calypso RevA: the bus is floating (Cf PB01435) | |
149 // (corrected with Calypso ReV B and Calypso C035) | |
150 #if (CHIPSET == 7) | |
151 #define W_A_CALYPSO_BUG_01435 1 | |
152 #else | |
153 #define W_A_CALYPSO_BUG_01435 0 | |
154 #endif | |
155 | |
156 | |
157 // for AMR thresolds definition CQ22226 | |
158 #define AMR_THRESHOLDS_WORKAROUND 1 | |
159 | |
160 #if (L1_GTT==1) | |
161 #define TTY_SYNC_MCU 1 | |
162 #define TTY_SYNC_MCU_2 1 | |
163 #define L1_GTT_FIFO_TEST_ATOMIC 0 | |
164 #define NEW_WKA_PATCH 0 | |
165 #define OPTIMISED 1 | |
166 #else | |
167 #define TTY_SYNC_MCU_2 0 | |
168 #define L1_GTT_FIFO_TEST_ATOMIC 0 | |
169 #define TTY_SYNC_MCU 0 | |
170 #define NEW_WKA_PATCH 0 | |
171 #define OPTIMISED 0 | |
172 | |
173 #endif | |
174 | |
175 // Traces... | |
176 #define NUCLEUS_TRACE 0 // Nucleus error trace | |
177 #define FLOWCHART 0 // Message sequence/flow chart trace. | |
178 #define LOGFILE_TRACE 0 // trace in an output logfile | |
179 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error | |
180 | |
181 // Test Scenari... | |
182 #define SCENARIO_FILE 0 // Test Scenario comes from input files. | |
183 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM. | |
184 | |
185 #if (OP_L1_STANDALONE == 1) | |
186 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible. | |
187 #else | |
188 #define L2_L3_SIMUL 0 | |
189 #endif | |
190 | |
191 // Control algorithms... | |
192 #define AFC_ALGO 1 // AFC algorithm. | |
193 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!! | |
194 #define TOA_ALGO 1 // TOA algorithm. | |
195 #define AGC_ALGO 1 // AGC algorithm. | |
196 #define TA_ALGO 1 // TA (Timing Advance) algorithm. | |
197 | |
198 #define FACCH_TEST 0 // FACCH test enabled. | |
199 | |
200 #define ADC_TIMER_ON 0 // Timer for ADC measurements | |
201 #define AFC_ON 1 // Enable of the Omega AFC module | |
202 | |
203 #define AUDIO_TASK 1 // Enable the L1 audio features | |
204 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1) | |
205 #if (OP_L1_STANDALONE == 1) | |
206 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1) | |
207 #else | |
208 #define AUDIO_L1_STANDALONE 0 | |
209 #endif | |
210 | |
211 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1) | |
212 | |
213 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management | |
214 | |
215 #define L1_RECOVERY 1 // L1 recovery | |
216 | |
217 | |
218 #if (L1_GPRS == 1) | |
219 #define RLC_VERSION RLC_SCENARIO | |
220 #if (RLC_VERSION == RLC_SCENARIO) | |
221 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO | |
222 // output stat on CRC error blocks | |
223 // The user must enter the cs type and | |
224 // the number of frames desired. | |
225 #else | |
226 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it | |
227 #endif | |
228 | |
229 #if (OP_L1_STANDALONE == 1) | |
230 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks | |
231 // activated by a layer 3 message (BG_TASK_START (<task number>)) | |
232 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>)) | |
233 // Warning : Works only with DSP>=31 | |
234 #else | |
235 #define DSP_BACKGROUND_TASKS 0 | |
236 #endif | |
237 | |
238 #else | |
239 #define DSP_BACKGROUND_TASKS 0 | |
240 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it | |
241 #endif | |
242 #endif | |
243 | |
244 // Audio tasks selection | |
245 //----------------------- | |
246 | |
247 #if (AUDIO_TASK == 1) | |
248 #define KEYBEEP 1 // Enable keybeep feature | |
249 #define TONE 1 // Enable tone feature | |
250 // Temporary modification for protocol stack compatibility - GSMLITE will be removed | |
251 #if (OP_L1_STANDALONE == 1) | |
252 #define GSMLITE 1 | |
253 #endif | |
254 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE)) | |
255 #define MELODY_E1 1 // Enable melody format E1 feature | |
256 #define VOICE_MEMO 1 // Enable voice memorization feature | |
257 | |
258 #define FIR 1 // Enable FIR feature | |
259 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) | |
260 #define AUDIO_MODE 1 // Enable Audio mode feature | |
261 #else | |
262 #define AUDIO_MODE 0 // Disable Audio mode feature | |
263 #endif | |
264 #else | |
265 #define MELODY_E1 0 // Disable melody format E1 feature | |
266 #define VOICE_MEMO 0 // Disable voice memorization feature | |
267 #if (MELODY_E2) | |
268 #define FIR 1 // Enable FIR feature | |
269 #else | |
270 #define FIR 0 // Disable FIR feature | |
271 #endif | |
272 | |
273 #define AUDIO_MODE 0 // Disable Audio mode feature | |
274 #endif | |
275 // Define CPORT for ESample only | |
276 #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36))) | |
277 #define L1_CPORT 1 // Enable cport feature | |
278 #else | |
279 #define L1_CPORT 0 // Disable cport feature | |
280 #endif | |
281 | |
282 #else | |
283 #define KEYBEEP 0 // Enable keybeep feature | |
284 #define TONE 0 // Enable tone feature | |
285 #define MELODY_E1 0 // Enable melody format E1 feature | |
286 #define VOICE_MEMO 0 // Enable voice memorization feature | |
287 | |
288 #define FIR 0 // Enable FIR feature | |
289 #define AUDIO_MODE 0 // Enable Audio mode feature | |
290 #define L1_CPORT 0 // Enable cport feature | |
291 #endif | |
292 | |
293 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2 | |
294 #if (OP_RIV_AUDIO == 1) | |
295 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available) | |
296 #endif | |
297 | |
298 | |
299 // Vocoder selections | |
300 //------------------- | |
301 | |
302 #define FR 1 // Full Rate | |
303 #define FR_HR 2 // Full Rate + Half Rate | |
304 #define FR_EFR 3 // Full Rate + Enhanced Full Rate | |
305 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate | |
306 | |
307 // Standard (frequency plan) selections | |
308 //------------------------------------- | |
309 | |
310 #define GSM 1 // GSM900. | |
311 #define GSM_E 2 // GSM900 Extended. | |
312 #define PCS1900 3 // PCS1900. | |
313 #define DCS1800 4 // DCS1800. | |
314 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands) | |
315 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands) | |
316 #define GSM850 7 // GSM850 Band | |
317 #define DUAL_US 8 // PCS1900 + GSM850 | |
318 | |
319 /*------------------------------------*/ | |
320 /* Power Management */ | |
321 /*------------------------------------*/ | |
322 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1 | |
323 | |
324 | |
325 /*---------------------------------------------------------------------------*/ | |
326 /* DSP configurations */ | |
327 /* ------------------ */ | |
328 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */ | |
329 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */ | |
330 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */ | |
331 /* 0 (821) | x | | | | 39Mhz | x | | | | 1 */ | |
332 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */ | |
333 /* 1 (830) | x | | | | 39Mhz | (1) | | x | | 1 */ | |
334 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */ | |
335 /* 2 (912) | x | x | | | 58.5Mhz | x | | | | 2 */ | |
336 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */ | |
337 /* 3 (10xx) | x | | x | x | 65Mhz | x | | | x | 3 */ | |
338 /* ----------+---+---+---+----+---------+------+-------+----|---+---------- */ | |
339 /* 4 (11xx) | x | x | x | x | 65Mhz | x | x (3)| | x | 3 */ | |
340 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */ | |
341 /* 5 (830) | x | | | | 39Mhz | x | | | | 1 */ | |
342 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */ | |
343 /* 6 (11xx) | x | x | x | x | 65Mhz | x | x (3)| |(2)| 3 */ | |
344 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */ | |
345 /* */ | |
346 /*(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is*/ | |
347 /* not corrected. */ | |
348 /* */ | |
349 /*(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP */ | |
350 /* interface which support AEC, therefore AEC is defined as 1. */ | |
351 /* */ | |
352 /*(3) Pole112 include RIF DL correction. No patch is needed if this one only */ | |
353 /* include RIF/DL problem. */ | |
354 /* */ | |
355 /*---------------------------------------------------------------------------*/ | |
356 #if (DSP == 16 || DSP == 17) | |
357 | |
358 /* #define CLKMOD1 0x414e // ... | |
359 #define CLKMOD2 0x414e // ...65 Mips | |
360 #define CLKSTART 0x29 // ...65 Mips */ | |
361 | |
362 #define CLKMOD1 0x4006 // ... | |
363 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
364 #define CLKSTART 0x29 // ...65 Mips | |
365 | |
366 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle | |
367 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips | |
368 #define CLKSTART 0x25 // ...39 Mips */ | |
369 | |
370 #define VOC FR_HR_EFR // FR + HR + EFR. | |
371 #define DATA14_4 1 // No 14.4 data allowed. | |
372 #define AEC 1 // AEC/NS supported. | |
373 #define MAP 3 | |
374 #define DSP_START 0x2000 | |
375 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
376 | |
377 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task. | |
378 | |
379 /* DSP debug trace configuration */ | |
380 /*-------------------------------*/ | |
381 #if (MELODY_E2) | |
382 // In case of the melody E2 the DSP trace must be disable because the | |
383 // melody instrument waves are overlayed with DSP trace buffer | |
384 | |
385 // DSP debug trace API buufer config | |
386 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
387 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. | |
388 #else | |
389 // DSP debug trace API buufer config | |
390 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
391 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. | |
392 #endif | |
393 | |
394 #elif (DSP == 30) // First GPRS. | |
395 #define CLKMOD1 0x4006 // ... | |
396 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
397 #define CLKSTART 0x29 // ...65 Mips | |
398 | |
399 #define VOC FR_HR_EFR // FR + HR + EFR. | |
400 #define DATA14_4 1 // No 14.4 data allowed. | |
401 #define AEC 1 // AEC/NS not supported. | |
402 #define MAP 3 | |
403 #define DSP_START 0x1F81 | |
404 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
405 #define ULYSSE 0 | |
406 | |
407 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task. | |
408 #elif (DSP == 31) // ROM Code GPRS G0. | |
409 #define CLKMOD1 0x4006 // ... | |
410 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
411 #define CLKSTART 0x29 // ...65 Mips | |
412 | |
413 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). | |
414 #define DATA14_4 1 // 14.4 data allowed. | |
415 #define AEC 1 // AEC/NS not supported. | |
416 #define MAP 3 | |
417 | |
418 #define DSP_START 0x8763 | |
419 | |
420 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer | |
421 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer | |
422 | |
423 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
424 #define ULYSSE 0 | |
425 | |
426 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task. | |
427 #elif (DSP == 32) // ROM Code GPRS G1. | |
428 #define CLKMOD1 0x4006 // ... | |
429 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
430 #define CLKSTART 0x29 // ...65 Mips | |
431 | |
432 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). | |
433 #define DATA14_4 1 // 14.4 data allowed. | |
434 #define AEC 1 // AEC/NS not supported. | |
435 #define MAP 3 | |
436 | |
437 #define DSP_START 0x8763 | |
438 | |
439 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer | |
440 | |
441 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
442 #define ULYSSE 0 | |
443 | |
444 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task. | |
445 #elif (DSP == 33) // ROM Code GPRS. | |
446 #define CLKMOD1 0x4006 // ... | |
447 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
448 #define CLKSTART 0x29 // ...65 Mips | |
449 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips | |
450 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). | |
451 #define AEC 1 // AEC/NS not supported. | |
452 #if (OP_RIV_AUDIO == 0) | |
453 #define L1_NEW_AEC 1 | |
454 #else | |
455 // Available but not yet tuned with Riviera AUDIO | |
456 #define L1_NEW_AEC 0 | |
457 #endif | |
458 #if ((L1_NEW_AEC) && (!AEC)) | |
459 // First undef the flag to avoid warnings at compilation time | |
460 #undef AEC | |
461 #define AEC 1 | |
462 #endif | |
463 | |
464 #define MAP 3 | |
465 | |
466 #define DSP_START 0x7000 | |
467 | |
468 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer | |
469 | |
470 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
471 #define ULYSSE 0 | |
472 | |
473 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. | |
474 | |
475 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) | |
476 | |
477 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep | |
478 | |
479 // management. | |
480 | |
481 // DSP_IDLE3 is not supported in simulation | |
482 | |
483 #else | |
484 #define W_A_DSP_IDLE3 0 | |
485 #endif | |
486 | |
487 // DSP software work-around config | |
488 // bit0 - Work-around to support CRTG. | |
489 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. | |
490 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. | |
491 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. | |
492 | |
493 #if (ANLG_FAM == 1) // OMEGA / NAUSICA | |
494 #define C_DSP_SW_WORK_AROUND 0x0006 | |
495 | |
496 #elif (ANLG_FAM == 2) // IOTA | |
497 #define C_DSP_SW_WORK_AROUND 0x000E | |
498 | |
499 #elif (ANLG_FAM == 3) // SYREN | |
500 #define C_DSP_SW_WORK_AROUND 0x000E | |
501 | |
502 #endif | |
503 | |
504 /* DSP debug trace configuration */ | |
505 /*-------------------------------*/ | |
506 #if (MELODY_E2) | |
507 // In case of the melody E2 the DSP trace must be disable because the | |
508 // melody instrument waves are overlayed with DSP trace buffer | |
509 | |
510 // DSP debug trace API buufer config | |
511 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
512 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. | |
513 | |
514 // DSP debug trace type config | |
515 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
516 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
517 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. | |
518 | |
519 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
520 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability | |
521 // Currently not supported ! | |
522 #endif | |
523 #else | |
524 // DSP debug trace API buufer config | |
525 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
526 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. | |
527 | |
528 // DSP debug trace type config | |
529 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
530 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
531 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. | |
532 | |
533 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
534 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) | |
535 #endif | |
536 #endif | |
537 /* d_error_status */ | |
538 /*-------------------------------*/ | |
539 | |
540 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
541 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) | |
542 | |
543 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 | |
544 #define DSP_DEBUG_GSM_MASK 0x0000 | |
545 #define DSP_DEBUG_GPRS_MASK 0x0f3d | |
546 #endif | |
547 | |
548 #if DCO_ALGO | |
549 // DCO type of scheduling | |
550 #define C_CN_DCO_PARAM 0xA248 | |
551 #endif | |
552 | |
553 #elif (DSP == 34) // ROM Code GPRS AMR. | |
554 #define CLKMOD1 0x4006 // ... | |
555 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
556 #define CLKSTART 0x29 // ...65 Mips | |
557 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips | |
558 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). | |
559 #define AEC 1 // AEC/NS not supported. | |
560 #if (OP_RIV_AUDIO == 0) | |
561 #define L1_NEW_AEC 1 | |
562 #else | |
563 // Available but not yet tuned with Riviera AUDIO | |
564 #define L1_NEW_AEC 0 | |
565 #endif | |
566 #if ((L1_NEW_AEC) && (!AEC)) | |
567 // First undef the flag to avoid warnings at compilation time | |
568 #undef AEC | |
569 #define AEC 1 | |
570 #endif | |
571 #define MAP 3 | |
572 | |
573 #define DSP_START 0x7000 | |
574 | |
575 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer | |
576 | |
577 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
578 #define ULYSSE 0 | |
579 | |
580 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. | |
581 | |
582 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) | |
583 | |
584 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep | |
585 | |
586 // management. | |
587 | |
588 // DSP_IDLE3 is not supported in simulation | |
589 | |
590 #else | |
591 #define W_A_DSP_IDLE3 0 | |
592 #endif | |
593 | |
594 // DSP software work-around config | |
595 // bit0 - Work-around to support CRTG. | |
596 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. | |
597 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. | |
598 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. | |
599 #if (ANLG_FAM == 1) // OMEGA / NAUSICA | |
600 #define C_DSP_SW_WORK_AROUND 0x0006 | |
601 | |
602 #elif (ANLG_FAM == 2) // IOTA | |
603 #define C_DSP_SW_WORK_AROUND 0x000E | |
604 | |
605 #elif (ANLG_FAM == 3) // SYREN | |
606 #define C_DSP_SW_WORK_AROUND 0x000E | |
607 | |
608 #endif | |
609 | |
610 /* DSP debug trace configuration */ | |
611 /*-------------------------------*/ | |
612 #if (MELODY_E2) | |
613 // In case of the melody E2 the DSP trace must be disable because the | |
614 // melody instrument waves are overlayed with DSP trace buffer | |
615 | |
616 // DSP debug trace API buufer config | |
617 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
618 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. | |
619 | |
620 // DSP debug trace type config | |
621 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
622 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
623 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. | |
624 | |
625 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
626 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability | |
627 // Currently not supported ! | |
628 #endif | |
629 #else | |
630 // DSP debug trace API buufer config | |
631 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
632 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. | |
633 | |
634 // DSP debug trace type config | |
635 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
636 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
637 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. | |
638 | |
639 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
640 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) | |
641 #endif | |
642 | |
643 // AMR trace | |
644 #define C_AMR_TRACE_ID 55 | |
645 | |
646 #endif | |
647 /* d_error_status */ | |
648 /*-------------------------------*/ | |
649 | |
650 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
651 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) | |
652 | |
653 // masks to apply on d_error_status bit field | |
654 #define DSP_DEBUG_GSM_MASK 0x0000 | |
655 #define DSP_DEBUG_GPRS_MASK 0x0f3d | |
656 #endif | |
657 | |
658 #elif (DSP == 35) // ROM Code GPRS AMR. | |
659 #define CLKMOD1 0x4006 // ... | |
660 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
661 #define CLKSTART 0x29 // ...65 Mips | |
662 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips | |
663 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). | |
664 #define AEC 1 // AEC/NS not supported. | |
665 #if (OP_RIV_AUDIO == 0) | |
666 #define L1_NEW_AEC 1 | |
667 #else | |
668 // Available but not yet tuned with Riviera AUDIO | |
669 #define L1_NEW_AEC 0 | |
670 #endif | |
671 #if ((L1_NEW_AEC) && (!AEC)) | |
672 // First undef the flag to avoid warnings at compilation time | |
673 #undef AEC | |
674 #define AEC 1 | |
675 #endif | |
676 #define MAP 3 | |
677 | |
678 #define FF_L1_TCH_VOCODER_CONTROL 1 | |
679 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 | |
680 | |
681 #define DSP_START 0x7000 | |
682 | |
683 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer | |
684 | |
685 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
686 #define ULYSSE 0 | |
687 | |
688 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. | |
689 | |
690 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) | |
691 | |
692 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep | |
693 | |
694 // management. | |
695 | |
696 // DSP_IDLE3 is not supported in simulation | |
697 | |
698 #else | |
699 #define W_A_DSP_IDLE3 0 | |
700 #endif | |
701 | |
702 // DSP software work-around config | |
703 // bit0 - Work-around to support CRTG. | |
704 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. | |
705 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. | |
706 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. | |
707 #if (ANLG_FAM == 1) // OMEGA / NAUSICA | |
708 #define C_DSP_SW_WORK_AROUND 0x0006 | |
709 | |
710 #elif (ANLG_FAM == 2) // IOTA | |
711 #define C_DSP_SW_WORK_AROUND 0x000E | |
712 | |
713 #elif (ANLG_FAM == 3) // SYREN | |
714 #define C_DSP_SW_WORK_AROUND 0x000E | |
715 | |
716 #endif | |
717 | |
718 /* DSP debug trace configuration */ | |
719 /*-------------------------------*/ | |
720 #if (MELODY_E2) | |
721 // In case of the melody E2 the DSP trace must be disable because the | |
722 // melody instrument waves are overlayed with DSP trace buffer | |
723 | |
724 // DSP debug trace API buufer config | |
725 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
726 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. | |
727 | |
728 // DSP debug trace type config | |
729 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
730 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
731 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. | |
732 | |
733 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
734 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability | |
735 // Currently not supported ! | |
736 #endif | |
737 #else | |
738 // DSP debug trace API buufer config | |
739 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
740 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. | |
741 | |
742 // DSP debug trace type config | |
743 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
744 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
745 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst. | |
746 | |
747 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
748 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) | |
749 #endif | |
750 | |
751 // AMR trace | |
752 #define C_AMR_TRACE_ID 55 | |
753 | |
754 #endif | |
755 /* d_error_status */ | |
756 /*-------------------------------*/ | |
757 | |
758 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
759 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) | |
760 | |
761 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 | |
762 #define DSP_DEBUG_GSM_MASK 0x08BD | |
763 #define DSP_DEBUG_GPRS_MASK 0x0f3d | |
764 #endif | |
765 #elif (DSP == 36) // ROM Code GPRS AMR. | |
766 #define CLKMOD1 0x4006 // ... | |
767 #define CLKMOD2 0x4116 // ...65 Mips pll free | |
768 #define CLKSTART 0x29 // ...65 Mips | |
769 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips | |
770 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs). | |
771 #define AEC 1 // AEC/NS not supported. | |
772 #if (OP_RIV_AUDIO == 0) | |
773 #define L1_NEW_AEC 1 | |
774 #else | |
775 // Available but not yet tuned with Riviera AUDIO | |
776 #define L1_NEW_AEC 0 | |
777 #endif | |
778 #if ((L1_NEW_AEC) && (!AEC)) | |
779 // First undef the flag to avoid warnings at compilation time | |
780 #undef AEC | |
781 #define AEC 1 | |
782 #endif | |
783 #define MAP 3 | |
784 #undef L1_AMR_NSYNC | |
785 #define L1_AMR_NSYNC 1 | |
786 #define FF_L1_TCH_VOCODER_CONTROL 1 | |
787 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1 | |
788 | |
789 #define DSP_START 0x7000 | |
790 | |
791 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer | |
792 | |
793 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH | |
794 #define ULYSSE 0 | |
795 | |
796 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task. | |
797 | |
798 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION)) | |
799 | |
800 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep | |
801 | |
802 // management. | |
803 | |
804 // DSP_IDLE3 is not supported in simulation | |
805 | |
806 #else | |
807 #define W_A_DSP_IDLE3 0 | |
808 #endif | |
809 | |
810 // DSP software work-around config | |
811 // bit0 - Work-around to support CRTG. | |
812 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. | |
813 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. | |
814 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. | |
815 #if (ANLG_FAM == 1) // OMEGA / NAUSICA | |
816 #define C_DSP_SW_WORK_AROUND 0x0006 | |
817 | |
818 #elif (ANLG_FAM == 2) // IOTA | |
819 #define C_DSP_SW_WORK_AROUND 0x000E | |
820 | |
821 #elif (ANLG_FAM == 3) // SYREN | |
822 #define C_DSP_SW_WORK_AROUND 0x000E | |
823 #endif | |
824 | |
825 // This workaround should be enabled only for H2-sample on full build config | |
826 #if (OP_L1_STANDALONE==1) | |
827 #define RAZ_VULSWITCH_REGAUDIO 0 | |
828 #endif | |
829 | |
830 /* DSP debug trace configuration */ | |
831 /*-------------------------------*/ | |
832 #if (MELODY_E2) | |
833 // In case of the melody E2 the DSP trace must be disable because the | |
834 // melody instrument waves are overlayed with DSP trace buffer | |
835 | |
836 // DSP debug trace API buufer config | |
837 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
838 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. | |
839 | |
840 // DSP debug trace type config | |
841 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
842 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
843 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. | |
844 | |
845 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
846 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability | |
847 // Currently not supported ! | |
848 #endif | |
849 #else | |
850 // DSP debug trace API buufer config | |
851 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. | |
852 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer. | |
853 | |
854 // DSP debug trace type config | |
855 // |<-------------- Features -------------->|<---------- Levels ----------->| | |
856 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR] | |
857 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header. | |
858 | |
859 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
860 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090) | |
861 #endif | |
862 | |
863 // AMR trace | |
864 #define C_AMR_TRACE_ID 55 | |
865 | |
866 #endif | |
867 /* d_error_status */ | |
868 /*-------------------------------*/ | |
869 | |
870 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4)) | |
871 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090) | |
872 | |
873 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062 | |
874 #define DSP_DEBUG_GSM_MASK 0x08BD | |
875 #define DSP_DEBUG_GPRS_MASK 0x0f3d | |
876 #endif | |
877 #endif // DSP | |
878 | |
879 /*------------------------------------*/ | |
880 /* Default value */ | |
881 /*------------------------------------*/ | |
882 #ifndef W_A_DSP1 | |
883 #define W_A_DSP1 0 | |
884 #endif | |
885 | |
886 #ifndef DATA14_4 | |
887 #define DATA14_4 0 | |
888 #endif | |
889 | |
890 #ifndef W_A_ITFORCE | |
891 #define W_A_ITFORCE 0 | |
892 #endif | |
893 | |
894 #ifndef W_A_DSP_IDLE3 | |
895 #define W_A_DSP_IDLE3 0 | |
896 #endif | |
897 | |
898 #ifndef L1_NEW_AEC | |
899 #define L1_NEW_AEC 0 | |
900 #endif | |
901 | |
902 #ifndef DSP_DEBUG_TRACE_ENABLE | |
903 #define DSP_DEBUG_TRACE_ENABLE 0 | |
904 #endif | |
905 | |
906 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT | |
907 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0 | |
908 #endif | |
909 | |
910 #ifndef D_ERROR_STATUS_TRACE_ENABLE | |
911 #define D_ERROR_STATUS_TRACE_ENABLE 0 | |
912 #endif | |
913 | |
914 #ifndef L1_GTT | |
915 #define L1_GTT 0 | |
916 #define TTY_SYNC_MCU 0 | |
917 #define TTY_SYNC_MCU_2 0 | |
918 #define L1_GTT_FIFO_TEST_ATOMIC 0 | |
919 #define NEW_WKA_PATCH 0 | |
920 #define OPTIMISED 0 | |
921 #endif | |
922 | |
923 #ifndef L1_AMR_NSYNC | |
924 #define L1_AMR_NSYNC 0 | |
925 #endif | |
926 | |
927 #ifndef FF_L1_TCH_VOCODER_CONTROL | |
928 #define FF_L1_TCH_VOCODER_CONTROL 0 | |
929 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0 | |
930 #endif | |
931 | |
932 /*------------------------------------*/ | |
933 /* Download */ | |
934 /*------------------------------------*/ | |
935 | |
936 | |
937 /* Possible values for the download status */ | |
938 | |
939 #define LEAD_READY 1 | |
940 #define BLOCK_READY 2 | |
941 #define PROGRAM_DONE 3 | |
942 #define PAGE_SELECTION 4 | |
943 | |
944 | |
945 /************************************/ | |
946 /* Options of compilation... */ | |
947 /************************************/ | |
948 | |
949 // Possible choice of hardware plateform. | |
950 #define GEMINI 1 // GEMINI chip (rom dsp code) | |
951 #define POLESTAR 2 // POLESTAR chip (no rom) | |
952 | |
953 // Possible choice for DSP software setup. | |
954 #define NO_DWNLD 0 | |
955 #define PATCH_DWNLD 1 | |
956 #define DSP_DWNLD 2 | |
957 #define PATCH_DSP_DWNLD 3 | |
958 | |
959 // MAC-S status reporting to Layer 1 | |
960 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1 | |
961 | |
962 | |
963 // Possible choice for dll_dcch_downlink interface (with FN or without FN) | |
964 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */ | |
965 | |
966 //--------------------------------------------------------------------------------- | |
967 | |
968 // Neighbor Cell RXLEV indication | |
969 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION)) | |
970 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1 | |
971 #else | |
972 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0 | |
973 #endif | |
974 | |
975 #endif /* __L1_CONFG_H__ */ |