FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cust0/l1_rf12.c @ 203:5dbf46894dab

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l1_rf12.c: ABB init constant renaming between MV100 and TCS211
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 08 Jun 2016 05:31:00 +0000
parents 47ac87c0bc1b
children 2d691e51d678
comparison
equal deleted inserted replaced
202:47ac87c0bc1b 203:5dbf46894dab
1845 /*------------------------------------------*/ 1845 /*------------------------------------------*/
1846 #if (ANLG_FAM == 1) 1846 #if (ANLG_FAM == 1)
1847 UWORD16 abb[ABB_TABLE_SIZE] = 1847 UWORD16 abb[ABB_TABLE_SIZE] =
1848 { 1848 {
1849 C_AFCCTLADD, // Value at reset 1849 C_AFCCTLADD, // Value at reset
1850 C_VBUR, // Uplink gain amp 0dB, Sidetone gain to mute 1850 C_VBUCTRL, // Uplink gain amp 0dB, Sidetone gain to mute
1851 C_VBDR, // Downlink gain amp 0dB, Volume control 0 dB 1851 C_VBDCTRL, // Downlink gain amp 0dB, Volume control 0 dB
1852 C_BBCTL, // value at reset 1852 C_BBCTRL, // value at reset
1853 C_APCOFF, // value at reset 1853 C_APCOFF, // value at reset
1854 C_BULIOFF, // value at reset 1854 C_BULIOFF, // value at reset
1855 C_BULQOFF, // value at reset 1855 C_BULQOFF, // value at reset
1856 C_DAI_ON_OFF, // value at reset 1856 C_DAI_ON_OFF, // value at reset
1857 C_AUXDAC, // value at reset 1857 C_AUXDAC, // value at reset
1858 C_VBCR, // VULSWITCH=0, VDLAUX=1, VDLEAR=1 1858 C_VBCTRL, // VULSWITCH=0, VDLAUX=1, VDLEAR=1
1859 C_APCDEL // value at reset 1859 C_APCDEL1 // value at reset
1860 }; 1860 };
1861 #elif (ANLG_FAM == 2) 1861 #elif (ANLG_FAM == 2)
1862 UWORD16 abb[ABB_TABLE_SIZE] = 1862 UWORD16 abb[ABB_TABLE_SIZE] =
1863 { 1863 {
1864 C_AFCCTLADD, 1864 C_AFCCTLADD,
1865 C_VBUR, 1865 C_VBUCTRL,
1866 C_VBDR, 1866 C_VBDCTRL,
1867 C_BBCTL, 1867 C_BBCTRL,
1868 C_BULGCAL, 1868 C_BULGCAL,
1869 C_APCOFF, 1869 C_APCOFF,
1870 C_BULIOFF, 1870 C_BULIOFF,
1871 C_BULQOFF, 1871 C_BULQOFF,
1872 C_DAI_ON_OFF, 1872 C_DAI_ON_OFF,
1873 C_AUXDAC, 1873 C_AUXDAC,
1874 C_VBCR, 1874 C_VBCTRL1,
1875 C_VBCR2, 1875 C_VBCTRL2,
1876 C_APCDEL, 1876 C_APCDEL1,
1877 C_APCDEL2 1877 C_APCDEL2
1878 }; 1878 };
1879 1879
1880 #elif (ANLG_FAM == 3) 1880 #elif (ANLG_FAM == 3)
1881 UWORD16 abb[ABB_TABLE_SIZE] = 1881 UWORD16 abb[ABB_TABLE_SIZE] =
1882 { 1882 {
1883 C_AFCCTLADD, 1883 C_AFCCTLADD,
1884 C_VBUR, 1884 C_VBUCTRL,
1885 C_VBDR, 1885 C_VBDCTRL,
1886 C_BBCTL, 1886 C_BBCTRL,
1887 C_BULGCAL, 1887 C_BULGCAL,
1888 C_APCOFF, 1888 C_APCOFF,
1889 C_BULIOFF, 1889 C_BULIOFF,
1890 C_BULQOFF, 1890 C_BULQOFF,
1891 C_DAI_ON_OFF, 1891 C_DAI_ON_OFF,
1892 C_AUXDAC, 1892 C_AUXDAC,
1893 C_VBCR, 1893 C_VBCTRL1,
1894 C_VBCR2, 1894 C_VBCTRL2,
1895 C_APCDEL, 1895 C_APCDEL1,
1896 C_APCDEL2, 1896 C_APCDEL2,
1897 C_VBPOP, 1897 C_VBPOP,
1898 C_VAUDINITD, 1898 C_VAUDINITD,
1899 C_VAUDCR, 1899 C_VAUDCR,
1900 C_VAUOCR, 1900 C_VAUOCR,