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comparison chipsetsw/layer1/cfile/l1_pwmgr.c @ 123:63137aa0ad1f

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l1_pwmgr.c: passes compilation (but link fails)
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Thu, 12 May 2016 02:18:21 +0000
parents 9360d1f31c00
children 190c68fa5689
comparison
equal deleted inserted replaced
122:9360d1f31c00 123:63137aa0ad1f
5 * Filename l1_pwmgr.c 5 * Filename l1_pwmgr.c
6 * Copyright 2003 (C) Texas Instruments 6 * Copyright 2003 (C) Texas Instruments
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9 9
10 // pinghua add these programe code section to put some sleep code into internal ram.
11 /*
12 * FreeCalypso: the Leonardo binary object version puts all of l1_pwmgr
13 * into the regular run-from-flash text section, so we'll do the same
14 * for now.
15 */
16 #if 0
17 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf")
18 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf")
19 #pragma CODE_SECTION(audio_madc_sleep,".emifconf")
20 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf")
21 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf")
22 #pragma CODE_SECTION(DBB_Wakeup_DS,".emifconf")
23 #pragma CODE_SECTION(l1ctl_pgm_clk32,".emifconf")
24 #pragma CODE_SECTION(l1ctl_gauging,".emifconf")
25 #pragma CODE_SECTION(GAUGING_Handler,".emifconf")
26 #pragma CODE_SECTION(l1s_get_HWTimers_ticks,".emifconf")
27 #pragma CODE_SECTION(l1s_adapt_traffic_controller,".emifconf")
28 #pragma CODE_SECTION(l1s_wakeup,".emifconf")
29 #pragma CODE_SECTION(l1s_wakeup_adjust,".emifconf")
30 #pragma CODE_SECTION(l1s_compute_wakeup_ticks,".emifconf")
31 #pragma CODE_SECTION(l1s_recover_Frame,".emifconf")
32 #pragma CODE_SECTION(l1s_recover_HWTimers,".emifconf")
33 #pragma CODE_SECTION(l1s_get_next_gauging_in_Packet_Idle,".emifconf")
34 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf")
35 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf")
36 #pragma CODE_SECTION(l1s_gauging_task,".emifconf")
37 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf")
38 // 2-03-2007 pinghua added end
39 #endif
40
41 #define L1_PWMGR_C 10 #define L1_PWMGR_C
42 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START 11 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
43
44 //sajal added .....................................
45 #if (CODE_VERSION == SIMULATION)
46 //#include "l1_pwmgr.h"
47 //omaps00090550 #303 warning removal typedef unsigned char UWORD_8;
48
49 // typedef volatile unsigned short REG_UWORD16; //omaps00090550
50 // #define REG16(A) (*(REG_UWORD16*)(A)) //omaps00090550
51 // typedef volatile unsigned short REGISTER_UWORD16; //omaps00090550
52
53 #define MAP_ULPD_REG 0xFFFE2000 //ULPD registers start address (CS4)
54 #define ULPD_SETUP_CLK13_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 14))
55 #define ULPD_SETUP_SLICER_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 15))
56 #define ULPD_SETUP_VTCXO_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 16))
57
58 #define MAP_CLKM_REG 0xFFFFFD00 //CLOCKM registers start address (CS31)
59 #define CLKM_CNTL_CLK_OFFSET 0x02
60 #define CLKM_CNTL_CLK_REG REG16 (MAP_CLKM_REG + CLKM_CNTL_CLK_OFFSET)
61
62 #define EMIF_CONFIG_PWD_POS 0
63 #define EMIF_CONFIG_PDE_POS 1
64 #define EMIF_CONFIG_PREFETCH_POS 3
65 #define EMIF_CONFIG_FLUSH_PREFETCH_POS 5
66 #define EMIF_CONFIG_WP_POS 6
67
68 #define EMIF_CONFIG REG16(EMIF_CONFIG_BASE_ADDR+EMIF_CONFIG_REG_OFFSET)
69 #define EMIF_CONFIG_BASE_ADDR 0xFFFFFB00 //External Memory inter registers address (CS31) (NEW)
70 #define EMIF_CONFIG_REG_OFFSET 0x02 // Emif configuration register
71
72 #endif
73 //sajal added till here......
74
75
76 12
77 #include "timer/timer2.h" 13 #include "timer/timer2.h"
78 #include "armio/armio.h" 14 #include "armio/armio.h"
79 15
80 //omaps00090550 #include "l1_macro.h" 16 //omaps00090550 #include "l1_macro.h"
416 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15) 352 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15)
417 extern T_DRP_REGS_STR *drp_regs; 353 extern T_DRP_REGS_STR *drp_regs;
418 #endif 354 #endif
419 355
420 #if L1_GPRS 356 #if L1_GPRS
421 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void); 357 WORD32 l1s_get_next_gauging_in_Packet_Idle(void);
422 #endif 358 #endif
423 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END 359 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
424 360
425 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled 361 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
426 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise 362 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise
1526 #endif 1462 #endif
1527 } 1463 }
1528 } 1464 }
1529 #endif 1465 #endif
1530 1466
1467 UWORD32 last_wakeup;
1468 UWORD8 wakeup_type; // Type of the interrupt
1469 UWORD8 why_big_sleep; // Type of the big sleep
1470
1471 extern UWORD16 int_id;
1531 1472
1532 // l1s_sleep_manager() 1473 // l1s_sleep_manager()
1533 // Description: 1474 // Description:
1534 // evaluate the loading of the system 1475 // evaluate the loading of the system
1535 // - SIM, UART, LCD .... 1476 // - SIM, UART, LCD ....
1589 #if (OP_BT == 1) 1530 #if (OP_BT == 1)
1590 WORD32 hci_ll_status; 1531 WORD32 hci_ll_status;
1591 #endif 1532 #endif
1592 1533
1593 // init for trace and debug 1534 // init for trace and debug
1594 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED; 1535 why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED;
1595 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_UNDEFINED; 1536 wakeup_type = WAKEUP_FOR_UNDEFINED;
1596 1537
1597 #if (CHIPSET != 15) 1538 #if (CHIPSET != 15)
1598 time_from_last_wakeup = (sleep_time - l1s.pw_mgr.wakeup_time + 42432) % 42432; 1539 time_from_last_wakeup = (sleep_time - last_wakeup + 42432) % 42432;
1599 #endif 1540 #endif
1600 1541
1601 1542
1602 #if (CODE_VERSION != SIMULATION) 1543 #if (CODE_VERSION != SIMULATION)
1603 //================================================= 1544 //=================================================
1715 // if MS can go in deep sleep 1656 // if MS can go in deep sleep
1716 if ( !OSload 1657 if ( !OSload
1717 || !HWtimer 1658 || !HWtimer
1718 || !min_time_gauging 1659 || !min_time_gauging
1719 #if (CHIPSET != 15) 1660 #if (CHIPSET != 15)
1720 || ((sleep_mode != CLOCK_STOP) && ((l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_SIM))) 1661 || ((sleep_mode != CLOCK_STOP) && ((why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (why_big_sleep == BIG_SLEEP_DUE_TO_SIM)))
1721 #endif 1662 #endif
1722 #if (OP_BT == 1) 1663 #if (OP_BT == 1)
1723 || !hci_ll_status 1664 || !hci_ll_status
1724 #endif 1665 #endif
1725 ) 1666 )
1793 if (min_time_gauging != -1) MIN(min_time, min_time_gauging) 1734 if (min_time_gauging != -1) MIN(min_time, min_time_gauging)
1794 1735
1795 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3) 1736 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
1796 // to trace the Wake up source 1737 // to trace the Wake up source
1797 // depending of min_time choose the wakeup_type 1738 // depending of min_time choose the wakeup_type
1798 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK; 1739 wakeup_type = WAKEUP_FOR_L1_TASK;
1799 if (min_time == l1a_l1s_com.time_to_next_l1s_task) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK; 1740 if (min_time == l1a_l1s_com.time_to_next_l1s_task) wakeup_type = WAKEUP_FOR_L1_TASK;
1800 if (min_time == HWtimer) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_HW_TIMER_TASK; 1741 if (min_time == HWtimer) wakeup_type = WAKEUP_FOR_HW_TIMER_TASK;
1801 if (min_time == min_time_gauging) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_GAUGING_TASK; 1742 if (min_time == min_time_gauging) wakeup_type = WAKEUP_FOR_GAUGING_TASK;
1802 if (min_time == OSload) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_OS_TASK; 1743 if (min_time == OSload) wakeup_type = WAKEUP_FOR_OS_TASK;
1803 #endif 1744 #endif
1804 1745
1805 //================================================= 1746 //=================================================
1806 // Choose DEEP or BIG SLEEP 1747 // Choose DEEP or BIG SLEEP
1807 //================================================= 1748 //=================================================
1824 else 1765 else
1825 { 1766 {
1826 // BIG SLEEP is chosen : check the reason 1767 // BIG SLEEP is chosen : check the reason
1827 l1s.pw_mgr.sleep_performed = FRAME_STOP; 1768 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1828 if ((l1s.pw_mgr.enough_gaug != TRUE) && (l1a_l1s_com.mode != CS_MODE0)) 1769 if ((l1s.pw_mgr.enough_gaug != TRUE) && (l1a_l1s_com.mode != CS_MODE0))
1829 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING; 1770 why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING;
1830 else 1771 else
1831 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES; 1772 why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES;
1832 } 1773 }
1833 } 1774 }
1834 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP) 1775 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP)
1835 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE; 1776 why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE;
1836 1777
1837 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) || 1778 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) ||
1838 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) ) 1779 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) )
1839 l1s.pw_mgr.sleep_performed = FRAME_STOP; 1780 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1840 1781
2112 //================================================= 2053 //=================================================
2113 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0) 2054 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
2114 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 2055 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2115 { 2056 {
2116 // DEEP SLEEP -> need time to setup afc and rf 2057 // DEEP SLEEP -> need time to setup afc and rf
2117 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration; 2058 wake_up_time = min_time - l1_config.params.setup_afc_and_rf;
2118 #if (CODE_VERSION == NOT_SIMULATION) 2059 #if (CODE_VERSION == NOT_SIMULATION)
2119 // Sleep one more TDMA - this is done as part of merging init and TPU control 2060 // Sleep one more TDMA - this is done as part of merging init and TPU control
2120 wake_up_time += 1; 2061 wake_up_time += 1;
2121 #endif 2062 #endif
2122 2063
2261 (drp_regs->CKM_OCPCLKL) |= (0x1); 2202 (drp_regs->CKM_OCPCLKL) |= (0x1);
2262 asm(" NOP"); 2203 asm(" NOP");
2263 asm(" NOP"); 2204 asm(" NOP");
2264 #endif 2205 #endif
2265 2206
2266 l1s.pw_mgr.wakeup_time = l1s.actual_time.fn_mod42432; 2207 last_wakeup = l1s.actual_time.fn_mod42432;
2267 2208
2268 if (l1s.pw_mgr.wakeup_time == sleep_time) 2209 if (last_wakeup == sleep_time)
2269 // sleep duration == 0 -> wakeup in the same frame as sleep 2210 // sleep duration == 0 -> wakeup in the same frame as sleep
2270 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0; 2211 wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0;
2271 2212
2272 #if (GSM_IDLE_RAM != 0) 2213 #if (GSM_IDLE_RAM != 0)
2273 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending 2214 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending
2274 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration); 2215 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration);
2275 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration); 2216 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration);
2379 2320
2380 #if (TRACE_TYPE != 0) 2321 #if (TRACE_TYPE != 0)
2381 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity 2322 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity
2382 { 2323 {
2383 #if (GSM_IDLE_RAM == 0) 2324 #if (GSM_IDLE_RAM == 0)
2384 l1_trace_sleep(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id); 2325 l1_trace_sleep(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep);
2385 #else 2326 #else
2386 l1_trace_sleep_intram(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id); 2327 l1_trace_sleep_intram(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep);
2387 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) 2328 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
2388 l1s_trace_mftab(); 2329 l1s_trace_mftab();
2389 #endif 2330 #endif
2390 #endif 2331 #endif
2391 } 2332 }
2392 l1s.pw_mgr.wake_up_int_id = 0; 2333 int_id = 0;
2393 #endif 2334 #endif
2394 2335
2395 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) 2336 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
2396 trace_info.sleep_performed = TRUE; 2337 trace_info.sleep_performed = TRUE;
2397 #endif 2338 #endif
2477 #else 2418 #else
2478 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int. 2419 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int.
2479 #endif 2420 #endif
2480 2421
2481 #if (CHIPSET == 12) || (CHIPSET == 15) 2422 #if (CHIPSET == 12) || (CHIPSET == 15)
2482 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up 2423 int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
2483 if ( l1s.pw_mgr.wake_up_int_id >= 256 ) 2424 if ( int_id >= 256 )
2484 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100; 2425 int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100;
2485 #else 2426 #else
2486 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up 2427 int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
2487 if ( l1s.pw_mgr.wake_up_int_id >= 256 ) 2428 if ( int_id >= 256 )
2488 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100; 2429 int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100;
2489 #endif 2430 #endif
2490 2431
2491 // clear pending IQ_FRAME it and unmask it 2432 // clear pending IQ_FRAME it and unmask it
2492 #if (CHIPSET == 12) || (CHIPSET == 15) 2433 #if (CHIPSET == 12) || (CHIPSET == 15)
2493 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT); 2434 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
2567 /***************************************************/ 2508 /***************************************************/
2568 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks(); 2509 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks();
2569 2510
2570 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3) 2511 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
2571 if ((l1s.pw_mgr.frame_adjust == TRUE)) 2512 if ((l1s.pw_mgr.frame_adjust == TRUE))
2572 l1s.pw_mgr.wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT; 2513 wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT;
2573 #endif 2514 #endif
2574 2515
2575 2516
2576 /* Fix Frame */ 2517 /* Fix Frame */
2577 2518
2687 { 2628 {
2688 // read sleeping planned value in TPU INIT register 2629 // read sleeping planned value in TPU INIT register
2689 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT; 2630 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT;
2690 // INTH is different from the ULPD interrupt -> aynchronous wakeup 2631 // INTH is different from the ULPD interrupt -> aynchronous wakeup
2691 #if (CHIPSET == 12) || (CHIPSET == 15) 2632 #if (CHIPSET == 12) || (CHIPSET == 15)
2692 if (l1s.pw_mgr.wake_up_int_id != C_INTH_TGSM_IT) 2633 if (int_id != C_INTH_TGSM_IT)
2693 #else 2634 #else
2694 if (l1s.pw_mgr.wake_up_int_id != IQ_TGSM) 2635 if (int_id != IQ_TGSM)
2695 #endif 2636 #endif
2696 { 2637 {
2697 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0; 2638 wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0;
2698 // RESET IT_ULPD in ULPD module 2639 // RESET IT_ULPD in ULPD module
2699 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register 2640 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register
2700 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM; 2641 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
2701 #if (CHIPSET == 12) || (CHIPSET == 15) 2642 #if (CHIPSET == 12) || (CHIPSET == 15)
2702 // RESET IQ_TGSM (IT_ULPD) in IT register 2643 // RESET IQ_TGSM (IT_ULPD) in IT register
2703 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT); 2644 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
2704 // RESET IQ_FRAME in IT register 2645 // RESET IQ_FRAME in IT register
2705 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT); 2646 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
2706 l1s.pw_mgr.wake_up_int_id = C_INTH_TGSM_IT; 2647 int_id = C_INTH_TGSM_IT;
2707 #else 2648 #else
2708 // RESET IQ_TGSM (IT_ULPD) in IT register 2649 // RESET IQ_TGSM (IT_ULPD) in IT register
2709 INTH_RESETONEIT(IQ_TGSM); 2650 INTH_RESETONEIT(IQ_TGSM);
2710 // RESET IQ_FRAME in IT register 2651 // RESET IQ_FRAME in IT register
2711 INTH_RESETONEIT(IQ_FRAME); 2652 INTH_RESETONEIT(IQ_FRAME);
2712 l1s.pw_mgr.wake_up_int_id = IQ_TGSM; 2653 int_id = IQ_TGSM;
2713 #endif 2654 #endif
2714 return(FALSE); 2655 return(FALSE);
2715 } 2656 }
2716 else 2657 else
2717 return(FALSE); 2658 return(FALSE);
2927 /* ------------ */ 2868 /* ------------ */
2928 /* return the nbr of frames before the next gauging */ 2869 /* return the nbr of frames before the next gauging */
2929 /* return -1 means no activity planned */ 2870 /* return -1 means no activity planned */
2930 /*-------------------------------------------------------*/ 2871 /*-------------------------------------------------------*/
2931 #if L1_GPRS 2872 #if L1_GPRS
2932 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void) 2873 UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle
2874
2875 WORD32 l1s_get_next_gauging_in_Packet_Idle(void)
2933 { 2876 {
2934 WORD32 next_gauging; 2877 WORD32 next_gauging;
2935 2878
2936 // gauging performed with Normal Paging (we are in Idle mode) 2879 // gauging performed with Normal Paging (we are in Idle mode)
2937 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED) 2880 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
2938 return ((UWORD32)(-1)); // no activity planned //omaps00090550 2881 return (-1); // no activity planned
2939 2882
2940 // we are not in Packet Idle Mode 2883 // we are not in Packet Idle Mode
2941 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED) 2884 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED)
2942 return ((UWORD32)(-1)); // no activity planned //omaps00090550 2885 return (-1); // no activity planned
2943 2886
2944 next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn ; 2887 next_gauging = next_gauging_scheduled_for_PNP - l1s.actual_time.fn ;
2945 if (next_gauging < 0) 2888 if (next_gauging < 0)
2946 next_gauging+=MAX_FN; 2889 next_gauging+=MAX_FN;
2947 2890
2948 if (next_gauging <= MIN_SLEEP_TIME) 2891 if (next_gauging <= MIN_SLEEP_TIME)
2949 return(0); 2892 return(0);
2963 BOOL l1s_gauging_decision_with_PNP(void) 2906 BOOL l1s_gauging_decision_with_PNP(void)
2964 { 2907 {
2965 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615) 2908 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615)
2966 WORD32 time_to_next_gauging=0; //changed to WORD32- sajal 2909 WORD32 time_to_next_gauging=0; //changed to WORD32- sajal
2967 // It's time to perform the next gauging 2910 // It's time to perform the next gauging
2968 time_to_next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn; 2911 time_to_next_gauging = next_gauging_scheduled_for_PNP - l1s.actual_time.fn;
2969 if (time_to_next_gauging < 0) 2912 if (time_to_next_gauging < 0)
2970 { 2913 {
2971 time_to_next_gauging += MAX_FN; 2914 time_to_next_gauging += MAX_FN;
2972 } 2915 }
2973 2916
2974 if( (time_to_next_gauging == 0) || (time_to_next_gauging > TWO_SECONDS_IN_FRAME)) 2917 if( (time_to_next_gauging == 0) || (time_to_next_gauging > TWO_SECONDS_IN_FRAME))
2975 { 2918 {
2976 2919
2977 l1s.next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME; 2920 next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME;
2978 if (l1s.next_gauging_scheduled_for_PNP >= MAX_FN) l1s.next_gauging_scheduled_for_PNP -= MAX_FN; 2921 if (next_gauging_scheduled_for_PNP >= MAX_FN) next_gauging_scheduled_for_PNP -= MAX_FN;
2979 return (TRUE); 2922 return (TRUE);
2980 } 2923 }
2981 2924
2982 return (FALSE); // do not perform gauging 2925 return (FALSE); // do not perform gauging
2983 } 2926 }
3001 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag. 2944 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag.
3002 2945
3003 // A gauging session is needed : start gauging session with this paging bloc ! 2946 // A gauging session is needed : start gauging session with this paging bloc !
3004 2947
3005 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging 2948 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
3006 #if 0 2949 // FreeCalypso TCS211 reconstruction: Nina's change reverted
2950 #if 1
3007 if (l1s.pw_mgr.enough_gaug != TRUE) 2951 if (l1s.pw_mgr.enough_gaug != TRUE)
3008 time_to_gaug = 0; 2952 time_to_gaug = 0;
3009 #else 2953 #else
3010 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1)) 2954 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1))
3011 { 2955 {