FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cfile/l1_pwmgr.c @ 122:9360d1f31c00

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l1_pwmgr.c: import of sensible changes from freecalypso-sw/gsm-fw version
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Wed, 11 May 2016 23:57:47 +0000
parents 282e78e6e772
children 63137aa0ad1f
comparison
equal deleted inserted replaced
121:282e78e6e772 122:9360d1f31c00
4 * 4 *
5 * Filename l1_pwmgr.c 5 * Filename l1_pwmgr.c
6 * Copyright 2003 (C) Texas Instruments 6 * Copyright 2003 (C) Texas Instruments
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9
9 // pinghua add these programe code section to put some sleep code into internal ram. 10 // pinghua add these programe code section to put some sleep code into internal ram.
11 /*
12 * FreeCalypso: the Leonardo binary object version puts all of l1_pwmgr
13 * into the regular run-from-flash text section, so we'll do the same
14 * for now.
15 */
16 #if 0
10 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf") 17 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf")
11 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf") 18 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf")
12 #pragma CODE_SECTION(audio_madc_sleep,".emifconf") 19 #pragma CODE_SECTION(audio_madc_sleep,".emifconf")
13 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf") 20 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf")
14 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf") 21 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf")
27 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf") 34 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf")
28 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf") 35 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf")
29 #pragma CODE_SECTION(l1s_gauging_task,".emifconf") 36 #pragma CODE_SECTION(l1s_gauging_task,".emifconf")
30 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf") 37 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf")
31 // 2-03-2007 pinghua added end 38 // 2-03-2007 pinghua added end
39 #endif
40
32 #define L1_PWMGR_C 41 #define L1_PWMGR_C
33 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START 42 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
34 43
35 //sajal added ..................................... 44 //sajal added .....................................
36 #if (CODE_VERSION == SIMULATION) 45 #if (CODE_VERSION == SIMULATION)
204 #include "l1_msgty.h" 213 #include "l1_msgty.h"
205 #include "l1_proto.h" 214 #include "l1_proto.h"
206 #include "l1_trace.h" 215 #include "l1_trace.h"
207 #include "timer/timer.h" 216 #include "timer/timer.h"
208 217
218 #include "l1_pwmgr.h"
209 219
210 #if (CHIPSET == 12) || (CHIPSET == 15) 220 #if (CHIPSET == 12) || (CHIPSET == 15)
211 #include "timer/timer_sec.h" 221 #include "timer/timer_sec.h"
212 #include "inth/sys_inth.h" 222 #include "inth/sys_inth.h"
213 223
358 #else 368 #else
359 #include "csmi/csmi.h" 369 #include "csmi/csmi.h"
360 #endif 370 #endif
361 #endif 371 #endif
362 372
373 #if (CHIPSET == 15)
363 #include "drp_api.h" 374 #include "drp_api.h"
375 #endif
364 376
365 #endif // NO SIMULATION 377 #endif // NO SIMULATION
366 378
367 #if (CODE_VERSION != SIMULATION) 379 #if (CODE_VERSION != SIMULATION)
368 // for PTOOL compatibility 380 // for PTOOL compatibility
399 411
400 #if (GSM_IDLE_RAM != 0) 412 #if (GSM_IDLE_RAM != 0)
401 extern void l1s_trace_mftab(void); 413 extern void l1s_trace_mftab(void);
402 #endif 414 #endif
403 415
404 #if (CODE_VERSION != SIMULATION) 416 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15)
405 extern T_DRP_REGS_STR *drp_regs; 417 extern T_DRP_REGS_STR *drp_regs;
406 #endif 418 #endif
407 419
408 #if L1_GPRS 420 #if L1_GPRS
409 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void); 421 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void);
455 #endif // NOT SIMULATION 467 #endif // NOT SIMULATION
456 468
457 #if(CHIPSET == 15) 469 #if(CHIPSET == 15)
458 470
459 /************************************************************/ 471 /************************************************************/
460 /* Configure EMIF for optimal consumption */ 472 /* Configure EMIF for optimal consumption */
461 /************************************************************/ 473 /************************************************************/
462 474
463 475
464 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en) 476 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en)
465 { 477 {
1537 #else 1549 #else
1538 UWORD32 sleep_time = l1s.actual_time.fn; 1550 UWORD32 sleep_time = l1s.actual_time.fn;
1539 #endif 1551 #endif
1540 1552
1541 #if(CHIPSET == 15) 1553 #if(CHIPSET == 15)
1542 Uint8 sleep_status; 1554 Uint8 sleep_status;
1543 #endif 1555 #endif
1544 1556
1545 #if (GSM_IDLE_RAM != 0) 1557 #if (GSM_IDLE_RAM != 0)
1546 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl; 1558 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
1547 BOOL flag_traffic_controller_state = 0; 1559 BOOL flag_traffic_controller_state = 0;
1623 { 1635 {
1624 OS_system_Unprotect(); 1636 OS_system_Unprotect();
1625 // free System structure 1637 // free System structure
1626 // Enable all IRQ 1638 // Enable all IRQ
1627 //l1_pwmgr_irq_dis_flag = 0; 1639 //l1_pwmgr_irq_dis_flag = 0;
1628 #if (CODE_VERSION!=SIMULATION) 1640 #if (CODE_VERSION!=SIMULATION)
1629 INT_EnableIRQ(); 1641 INT_EnableIRQ();
1630 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); 1642 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1631 #endif 1643 #endif
1632 #if (GSM_IDLE_RAM != 0) 1644 #if (GSM_IDLE_RAM != 0)
1633 gsm_idle_ram_ctl->os_load = 0; 1645 gsm_idle_ram_ctl->os_load = 0;
1634 gsm_idle_ram_ctl->hw_timer = 0; 1646 gsm_idle_ram_ctl->hw_timer = 0;
1635 #endif // GSM_IDLE_RAM 1647 #endif // GSM_IDLE_RAM
1636 return; 1648 return;
1642 #endif 1654 #endif
1643 //================================================= 1655 //=================================================
1644 // check OS loading 1656 // check OS loading
1645 //================================================= 1657 //=================================================
1646 OSload = OS_get_inactivity_ticks(); 1658 OSload = OS_get_inactivity_ticks();
1647 #if (CODE_VERSION!=SIMULATION) 1659 #if (CODE_VERSION!=SIMULATION)
1648 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){ 1660 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){
1649 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD; 1661 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD;
1650 l1_pwmgr_debug.fail_ret_val = OSload; 1662 l1_pwmgr_debug.fail_ret_val = OSload;
1651 } 1663 }
1652 #endif //NOT SIMULATION 1664 #endif //NOT SIMULATION
1653 1665
1654 //================================================= 1666 //=================================================
1655 // check HW Timers loading 1667 // check HW Timers loading
1656 //================================================= 1668 //=================================================
1657 HWtimer= l1s_get_HWTimers_ticks(); 1669 HWtimer= l1s_get_HWTimers_ticks();
1714 { 1726 {
1715 1727
1716 1728
1717 1729
1718 #if (OP_L1_STANDALONE == 0) 1730 #if (OP_L1_STANDALONE == 0)
1719 /*GC_Wakeup(); OMAPS00134004*/ 1731 /*GC_Wakeup(); OMAPS00134004*/
1720 #endif 1732 #endif
1721 1733
1722 #if (CODE_VERSION != SIMULATION) 1734 #if (CODE_VERSION != SIMULATION)
1723 OS_system_Unprotect(); 1735 OS_system_Unprotect();
1724 // free System structure 1736 // free System structure
1739 #endif 1751 #endif
1740 1752
1741 #if (CHIPSET != 15) 1753 #if (CHIPSET != 15)
1742 SER_WakeUpUarts(); // Wake up Uarts 1754 SER_WakeUpUarts(); // Wake up Uarts
1743 #else 1755 #else
1744 // To be checked if this needs a change 1756 // To be checked if this needs a change
1745 #endif 1757 #endif
1746 1758
1747 #if (GSM_IDLE_RAM != 0) 1759 #if (GSM_IDLE_RAM != 0)
1748 // The traffic controller state shall be restored as it was before 1760 // The traffic controller state shall be restored as it was before
1749 // calling SER_WakeUpUarts. Do not disable it if an interrup occured 1761 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1804 #if (CHIPSET == 12) || (CHIPSET == 15) 1816 #if (CHIPSET == 12) || (CHIPSET == 15)
1805 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) && 1817 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
1806 !CLKM_READ_nIDLE3) 1818 !CLKM_READ_nIDLE3)
1807 #else 1819 #else
1808 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) 1820 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0))
1809 #endif 1821 #endif
1810 #endif 1822 #endif
1811 l1s.pw_mgr.sleep_performed = CLOCK_STOP; 1823 l1s.pw_mgr.sleep_performed = CLOCK_STOP;
1812 else 1824 else
1813 { 1825 {
1814 // BIG SLEEP is chosen : check the reason 1826 // BIG SLEEP is chosen : check the reason
1943 1955
1944 #endif // NOT SIMULATION 1956 #endif // NOT SIMULATION
1945 if(!sleep_status) 1957 if(!sleep_status)
1946 { 1958 {
1947 1959
1948 #if (OP_L1_STANDALONE == 0) 1960 #if (OP_L1_STANDALONE == 0)
1949 /*GC_Wakeup(); OMAPS00134004*/ 1961 /*GC_Wakeup(); OMAPS00134004*/
1950 #endif 1962 #endif
1951 1963
1952 #if (CODE_VERSION != SIMULATION) 1964 #if (CODE_VERSION != SIMULATION)
1953 OS_system_Unprotect(); 1965 OS_system_Unprotect();
1954 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); 1966 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1955 #endif // NOT SIMULATION 1967 #endif // NOT SIMULATION
1990 #if (CODE_VERSION != SIMULATION) 2002 #if (CODE_VERSION != SIMULATION)
1991 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 2003 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1992 { 2004 {
1993 // ==== STop RF and TPU..... =================== 2005 // ==== STop RF and TPU..... ===================
1994 2006
1995 //L1_trace_string("Proceeding to Deep Sleep\n"); 2007 //L1_trace_string("Proceeding to Deep Sleep\n");
1996 2008
1997 2009
1998 l1dmacro_RF_sleep(); 2010 l1dmacro_RF_sleep();
1999 2011
2000 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET | 2012 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET |
2056 2068
2057 //============================================== 2069 //==============================================
2058 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB) 2070 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
2059 //============================================== 2071 //==============================================
2060 #if (ANLG_FAM != 11) 2072 #if (ANLG_FAM != 11)
2061 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc,l1s.pw_mgr.afc_bypass_mode); 2073 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc);
2062 #else 2074 #else
2063 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS 2075 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS
2064 #endif 2076 #endif
2065 2077
2066 #if (OP_BT == 1) 2078 #if (OP_BT == 1)
2068 #endif 2080 #endif
2069 //================================================= 2081 //=================================================
2070 // STop SPI ..... 2082 // STop SPI .....
2071 //================================================= 2083 //=================================================
2072 2084
2073 #if(CHIPSET != 15) 2085 #if(CHIPSET != 15)
2074 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED 2086 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
2075 #endif 2087 #endif
2076 #endif // NOT SIMULATION 2088 #endif // NOT SIMULATION
2077 2089
2078 2090
2079 //================================================= 2091 //=================================================
2080 // CQ19599: For Calypso+ chipset, extended page mode 2092 // CQ19599: For Calypso+ chipset, extended page mode
2101 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0) 2113 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
2102 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 2114 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2103 { 2115 {
2104 // DEEP SLEEP -> need time to setup afc and rf 2116 // DEEP SLEEP -> need time to setup afc and rf
2105 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration; 2117 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration;
2106 #if (CODE_VERSION == NOT_SIMULATION) 2118 #if (CODE_VERSION == NOT_SIMULATION)
2107 // Sleep one more TDMA - this is done as part of merging init and TPU control 2119 // Sleep one more TDMA - this is done as part of merging init and TPU control
2108 wake_up_time += 1; 2120 wake_up_time += 1;
2109 #endif 2121 #endif
2110 2122
2111 } 2123 }
2112 else 2124 else
2113 // BIG SLEEP 2125 // BIG SLEEP
2114 wake_up_time = min_time - 1; 2126 wake_up_time = min_time - 1;
2191 2203
2192 //========================================================== 2204 //==========================================================
2193 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized 2205 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized
2194 //========================================================== 2206 //==========================================================
2195 2207
2196 #if(CHIPSET != 15) 2208 #if(CHIPSET != 15)
2197 UWORD16 clocks_stopped; //OMAPS90550- new 2209 UWORD16 clocks_stopped; //OMAPS90550- new
2198 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status); 2210 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
2199 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT) 2211 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
2200 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN); 2212 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN);
2201 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT) 2213 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
2202 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001); 2214 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001);
2203 #else 2215 #else
2204 // Nothing to be done as it is taken care by Locosto_Configure_BS 2216 // Nothing to be done as it is taken care by Locosto_Configure_BS
2205 #endif 2217 #endif
2206 2218
2207 #if (W_A_CALYPSO_BUG_01435 == 1) 2219 #if (W_A_CALYPSO_BUG_01435 == 1)
2208 f_arm_sleep_cmd(BIG_SLEEP); 2220 f_arm_sleep_cmd(BIG_SLEEP);
2209 #else 2221 #else
2210 2222
2235 #if (GSM_IDLE_RAM_DEBUG == 1) 2247 #if (GSM_IDLE_RAM_DEBUG == 1)
2236 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1 2248 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1
2237 #endif 2249 #endif
2238 2250
2239 2251
2240 l1s_wakeup(); 2252 l1s_wakeup();
2241 2253
2242 #if (CHIPSET == 15) 2254 #if (CHIPSET == 15)
2243 // The following command writes '1' into CKM_OCPCLK register in DRP; 2255 // The following command writes '1' into CKM_OCPCLK register in DRP;
2244 // This is done after the DPLL is up 2256 // This is done after the DPLL is up
2245 // CKM_OCPCLK (R/W) = Address 0xFFFF040C 2257 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
2246 // Bit 0: 0 ?OCP clock is the DCXO clock. 2258 // Bit 0: 0 ?OCP clock is the DCXO clock.
2247 // 1 ?OCP clock is the divided DSP clock 2259 // 1 ?OCP clock is the divided DSP clock
2275 //================================================= 2287 //=================================================
2276 #if (CODE_VERSION != SIMULATION) 2288 #if (CODE_VERSION != SIMULATION)
2277 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 2289 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2278 { 2290 {
2279 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN; 2291 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN;
2280 UWORD8 local_sleep_status; 2292 UWORD8 local_sleep_status;
2281 2293
2282 2294
2283 #if (CHIPSET == 15) 2295 #if (CHIPSET == 15)
2284 2296
2285 DBB_Wakeup_DS(); 2297 DBB_Wakeup_DS();
2325 #endif 2337 #endif
2326 2338
2327 //================================================= 2339 //=================================================
2328 //if CLOCK_STOP or FRAME-STOP : ReStart SPI 2340 //if CLOCK_STOP or FRAME-STOP : ReStart SPI
2329 //================================================= 2341 //=================================================
2330 #if(CHIPSET != 15) 2342 #if(CHIPSET != 15)
2331 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED 2343 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
2332 #endif 2344 #endif
2333 2345
2334 //================================================= 2346 //=================================================
2335 // Wake up ABB 2347 // Wake up ABB
2336 //================================================= 2348 //=================================================
2337 #if (ANLG_FAM != 11) 2349 #if (ANLG_FAM != 11)
2338 ABB_wakeup(l1s.pw_mgr.sleep_performed,l1s.afc,l1s.pw_mgr.afc_bypass_mode); 2350 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc);
2339 #else 2351 #else
2340 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS 2352 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS
2341 #endif 2353 #endif
2342 2354
2343 #if (OP_BT == 1) 2355 #if (OP_BT == 1)
2354 f_memif_extended_page_mode_enable(); 2366 f_memif_extended_page_mode_enable();
2355 #endif 2367 #endif
2356 2368
2357 #if (OP_L1_STANDALONE == 0) 2369 #if (OP_L1_STANDALONE == 0)
2358 /*GC_Wakeup(); OMAPS00134004*/ 2370 /*GC_Wakeup(); OMAPS00134004*/
2359 #endif 2371 #endif
2360 2372
2361 #if (CODE_VERSION != SIMULATION) 2373 #if (CODE_VERSION != SIMULATION)
2362 //================================================= 2374 //=================================================
2363 // enable IRQ 2375 // enable IRQ
2364 //================================================= 2376 //=================================================
2422 2434
2423 2435
2424 #if (CHIPSET != 15) 2436 #if (CHIPSET != 15)
2425 SER_WakeUpUarts(); // Wake up Uarts 2437 SER_WakeUpUarts(); // Wake up Uarts
2426 #else 2438 #else
2427 // To be checked if this needs a change 2439 // To be checked if this needs a change
2428 #endif 2440 #endif
2429 2441
2430 2442
2431 #if (GSM_IDLE_RAM != 0) 2443 #if (GSM_IDLE_RAM != 0)
2432 // The traffic controller state shall be restored as it was before 2444 // The traffic controller state shall be restored as it was before
3123 #endif 3135 #endif
3124 #endif 3136 #endif
3125 #endif 3137 #endif
3126 3138
3127 // DSP programmation ....... 3139 // DSP programmation .......
3128 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 3140 #if (DSP >= 33)
3129 #if (CHIPSET==4) 3141 #if (CHIPSET==4)
3130 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB; 3142 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB;
3131 #endif 3143 #endif
3132 #else 3144 #else
3133 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP 3145 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP
3174 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS); 3186 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS);
3175 #endif 3187 #endif
3176 #endif 3188 #endif
3177 3189
3178 // DSP programmation : free IDLE modes... 3190 // DSP programmation : free IDLE modes...
3179 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 3191 #if (DSP >= 33)
3180 #if (CHIPSET==4) 3192 #if (CHIPSET==4)
3181 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB; 3193 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB;
3182 #endif 3194 #endif
3183 #else 3195 #else
3184 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1; 3196 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1;