FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cfile/l1_init.c @ 109:a038d8cd9647

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l1_init.c: fixes from the freecalypso-sw/gsm-fw version, doesn't compile yet
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Fri, 08 Apr 2016 04:42:08 +0000
parents 0b78e29313b4
children 86b36d9f4b42
comparison
equal deleted inserted replaced
108:0b78e29313b4 109:a038d8cd9647
199 #if (ANLG_FAM == 11) 199 #if (ANLG_FAM == 11)
200 #include "bspTwl3029_I2c.h" 200 #include "bspTwl3029_I2c.h"
201 #include "bspTwl3029_Aud_Map.h" 201 #include "bspTwl3029_Aud_Map.h"
202 #include "bspTwl3029_Madc.h" 202 #include "bspTwl3029_Madc.h"
203 #endif 203 #endif
204
205 #if (RF_FAM == 61)
204 //OMAPS148175 206 //OMAPS148175
205 #include "l1_drp_if.h" 207 #include "l1_drp_if.h"
206 #include "drp_main.h" 208 #include "drp_main.h"
207 // 209 #endif
210
208 #if (ANLG_FAM == 11) 211 #if (ANLG_FAM == 11)
209 #if (L1_MADC_ON == 1) 212 #if (L1_MADC_ON == 1)
210 extern BspTwl3029_MadcResults l1_madc_results; 213 extern BspTwl3029_MadcResults l1_madc_results;
211 extern void l1a_madc_callback(void); 214 extern void l1a_madc_callback(void);
212 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC 215 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
237 #endif // L1_GPRS 240 #endif // L1_GPRS
238 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38)|| (DSP == 39))&& (CODE_VERSION != SIMULATION)) 241 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38)|| (DSP == 39))&& (CODE_VERSION != SIMULATION))
239 extern void l1_api_dump(void); 242 extern void l1_api_dump(void);
240 #endif 243 #endif
241 244
242 #if (TRACE_TYPE==3) 245 #if (TRACE_TYPE==3)
243 void reset_stats(); 246 void reset_stats();
244 #endif // TRACE_TYPE 247 #endif // TRACE_TYPE
245 248
246 #if (L1_GTT == 1) 249 #if (L1_GTT == 1)
247 extern void l1gtt_initialize_var(void); 250 extern void l1gtt_initialize_var(void);
255 extern void l1midi_initialize_var(void); 258 extern void l1midi_initialize_var(void);
256 #endif 259 #endif
257 //ADDED FOR AAC 260 //ADDED FOR AAC
258 #if (L1_AAC == 1) 261 #if (L1_AAC == 1)
259 extern void l1aac_initialize_var(void); 262 extern void l1aac_initialize_var(void);
260 #endif
261
262 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
263 extern void L1_trace_string(char *s);
264 #endif 263 #endif
265 264
266 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7)) 265 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
267 extern void L1_trace_string(char *s); 266 extern void L1_trace_string(char *s);
268 #endif 267 #endif
354 // Reset DSP page bit and DSP enable bit... 353 // Reset DSP page bit and DSP enable bit...
355 //==================================================== 354 //====================================================
356 355
357 (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL; 356 (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL;
358 357
359 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 358 #if (DSP >= 33)
360 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page; 359 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
361 #else 360 #else
362 l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page; 361 l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
363 #endif 362 #endif
364 363
412 #else 411 #else
413 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny 412 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny
414 413
415 #endif 414 #endif
416 415
417 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 416 #if (DSP >= 33)
418 // Initialize V42b variables 417 // Initialize V42b variables
419 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0; 418 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0;
420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0; 419 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0;
421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0; 420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0;
422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0; 421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0;
447 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER; 446 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER;
448 447
449 // Initialize the poll response buffer to "no poll request" 448 // Initialize the poll response buffer to "no poll request"
450 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE; 449 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE;
451 #else // L1_GPRS 450 #else // L1_GPRS
452 #if ((DSP == 31) || (DSP == 32) || (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)) 451 #if (DSP >= 31)
453 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER; 452 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER;
454 #endif 453 #endif
455 #endif // L1_GPRS 454 #endif // L1_GPRS
456 455
457 // Set EOTD bit if required 456 // Set EOTD bit if required
473 #if ((DSP == 17)||(DSP == 32)) 472 #if ((DSP == 17)||(DSP == 32))
474 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON; 473 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
475 #endif // DSP 474 #endif // DSP
476 #endif // DCO_ALGO 475 #endif // DCO_ALGO
477 476
478 #if ((DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38)) || (DSP == 39) 477 #if (DSP >= 34)
479 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0; 478 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0;
480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0; 479 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0;
481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0; 480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0;
482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0; 481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0;
483 #endif 482 #endif
484 483
485 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 484 #if (DSP >= 35)
486 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS 485 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS
487 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS 486 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS
488 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS 487 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS
489 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS 488 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS
490 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS 489 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS
520 #else 519 #else
521 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0; 520 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0;
522 #endif 521 #endif
523 522
524 #if (CHIPSET == 12) || (CHIPSET == 15) 523 #if (CHIPSET == 12) || (CHIPSET == 15)
525 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 524 #if (DSP >= 35)
526 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0; 525 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0;
527 #endif 526 #endif
528 #endif 527 #endif
529 528
530 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto 529 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto
584 583
585 #endif // DSP == 38 584 #endif // DSP == 38
586 585
587 // Intialize the AFC 586 // Intialize the AFC
588 #if (DSP == 38) || (DSP == 39) 587 #if (DSP == 38) || (DSP == 39)
589 #if (CODE_VERSION != SIMULATION) 588 #if (CODE_VERSION != SIMULATION)
590 l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS; 589 l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS;
591 #endif 590 #endif
592 #endif 591
593 592 #if (L1_DRP_IQ_SCALING == 1)
594 #if (L1_DRP_IQ_SCALING == 1)
595 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1; 593 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1;
596 #else 594 #else
597 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0; 595 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0;
596 #endif
598 #endif 597 #endif
599 598
600 } 599 }
601 600
602 /*-------------------------------------------------------*/ 601 /*-------------------------------------------------------*/
700 699
701 //Locosto This funciton would change drastically due to Triton introduction and instead of SPI we have i2c 700 //Locosto This funciton would change drastically due to Triton introduction and instead of SPI we have i2c
702 void l1_abb_power_on(void) 701 void l1_abb_power_on(void)
703 { 702 {
704 #if (CODE_VERSION != SIMULATION) 703 #if (CODE_VERSION != SIMULATION)
705 #if (CHIPSET == 12) 704 #if (CHIPSET != 15)
706 T_SPI_DEV *Abb; 705 T_SPI_DEV *Abb;
707 T_SPI_DEV init_spi_device; 706 T_SPI_DEV init_spi_device;
708 UWORD16 Abb_Status; 707 UWORD16 Abb_Status;
709 T_NDB_MCU_DSP * dsp_ndb_ptr; 708 T_NDB_MCU_DSP * dsp_ndb_ptr;
710 709
776 dsp_ndb_ptr->d_vbctrl = l1_config.params.vbctrl; // VULSWITCH=0, VDLAUX=1, VDLEAR=1. 775 dsp_ndb_ptr->d_vbctrl = l1_config.params.vbctrl; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
777 776
778 // APCDEL1 will be initialized on rach only .... 777 // APCDEL1 will be initialized on rach only ....
779 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1; 778 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
780 779
781 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) 780 #if (DSP >= 33)
782 // To increase the robustness the IOTA register are reseted to 0 781 // To increase the robustness the IOTA register are reseted to 0
783 // if OMEGA, NAUSICA is used 782 // if OMEGA, NAUSICA is used
784 dsp_ndb_ptr->d_bulgcal = 0x0000; 783 dsp_ndb_ptr->d_bulgcal = 0x0000;
785 dsp_ndb_ptr->d_vbctrl2 = 0x0000; 784 dsp_ndb_ptr->d_vbctrl2 = 0x0000;
786 dsp_ndb_ptr->d_apcdel2 = 0x0000; 785 dsp_ndb_ptr->d_apcdel2 = 0x0000;
947 l1s.pw_mgr.sleep_duration = 0; 946 l1s.pw_mgr.sleep_duration = 0;
948 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP; 947 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP;
949 l1s.pw_mgr.modules_status = 0; // all clocks ON 948 l1s.pw_mgr.modules_status = 0; // all clocks ON
950 l1s.pw_mgr.paging_scheduled = FALSE; 949 l1s.pw_mgr.paging_scheduled = FALSE;
951 950
951 #if 0 /* not present in TCS211 */
952 // variable for afc bypass mode 952 // variable for afc bypass mode
953 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE; 953 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE;
954 #endif
954 955
955 // 32 Khz gauging .... 956 // 32 Khz gauging ....
956 l1s.pw_mgr.gaug_count = 0; 957 l1s.pw_mgr.gaug_count = 0;
957 l1s.pw_mgr.enough_gaug = FALSE; 958 l1s.pw_mgr.enough_gaug = FALSE;
958 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging 959 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging