FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cfile/l1_pwmgr.c @ 128:a2f9560c1cf1

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l1_pwmgr.c: began de-LoCosto-fication of l1s_sleep_manager()
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Fri, 13 May 2016 19:18:35 +0000
parents 633cc67bebbc
children 419f638cf03b
comparison
equal deleted inserted replaced
127:633cc67bebbc 128:a2f9560c1cf1
282 LF = LF +l1s.pw_mgr.histo[ind][0]; \ 282 LF = LF +l1s.pw_mgr.histo[ind][0]; \
283 HF = HF +l1s.pw_mgr.histo[ind][1]; \ 283 HF = HF +l1s.pw_mgr.histo[ind][1]; \
284 } 284 }
285 285
286 286
287 #if (CODE_VERSION!=SIMULATION) 287 #if 0 /* FreeCalypso TCS211 reconstruction */
288 T_PWMGR_DEBUG l1_pwmgr_debug; 288 T_PWMGR_DEBUG l1_pwmgr_debug;
289 #endif // NOT SIMULATION 289 #endif
290 290
291 291
292 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */ 292 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */
293 293
294 294
773 UWORD32 sleep_time = l1s.actual_time.fn_mod42432; 773 UWORD32 sleep_time = l1s.actual_time.fn_mod42432;
774 #else 774 #else
775 UWORD32 sleep_time = l1s.actual_time.fn; 775 UWORD32 sleep_time = l1s.actual_time.fn;
776 #endif 776 #endif
777 777
778 #if(CHIPSET == 15)
779 Uint8 sleep_status;
780 #endif
781
782 #if (GSM_IDLE_RAM != 0) 778 #if (GSM_IDLE_RAM != 0)
783 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl; 779 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
784 BOOL flag_traffic_controller_state = 0; 780 BOOL flag_traffic_controller_state = 0;
785 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl); 781 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
786 782
795 if (l1_config.pwr_mngt == PWR_MNGT) 791 if (l1_config.pwr_mngt == PWR_MNGT)
796 { 792 {
797 // Power management is enabled 793 // Power management is enabled
798 WORD32 min_time, OSload, HWtimer,wake_up_time,min_time_gauging; 794 WORD32 min_time, OSload, HWtimer,wake_up_time,min_time_gauging;
799 UWORD32 sleep_mode; 795 UWORD32 sleep_mode;
800 #if (ANLG_FAM != 11)
801 WORD32 afc_fix; 796 WORD32 afc_fix;
802 #endif
803 UWORD32 uw32_store_next_time; 797 UWORD32 uw32_store_next_time;
804 #if (CHIPSET != 15)
805 static UWORD32 previous_sleep = FRAME_STOP; 798 static UWORD32 previous_sleep = FRAME_STOP;
806 #endif
807 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1) 799 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
808 BOOL extended_page_mode_state = 0; //Store state of extended page mode 800 BOOL extended_page_mode_state = 0; //Store state of extended page mode
809 #endif 801 #endif
810 #if (CHIPSET != 15)
811 WORD32 time_from_last_wakeup=0; 802 WORD32 time_from_last_wakeup=0;
812 #endif
813 803
814 #if (OP_BT == 1) 804 #if (OP_BT == 1)
815 WORD32 hci_ll_status; 805 WORD32 hci_ll_status;
816 #endif 806 #endif
817 807
818 // init for trace and debug 808 // init for trace and debug
819 why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED; 809 why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED;
820 wakeup_type = WAKEUP_FOR_UNDEFINED; 810 wakeup_type = WAKEUP_FOR_UNDEFINED;
821 811
822 #if (CHIPSET != 15)
823 time_from_last_wakeup = (sleep_time - last_wakeup + 42432) % 42432; 812 time_from_last_wakeup = (sleep_time - last_wakeup + 42432) % 42432;
824 #endif 813
825 814 //=================================================
815 // check System (SIM, UART, LDC ..... )
816 //=================================================
817 sleep_mode = Cust_check_system();
818
819 #if (GSM_IDLE_RAM != 0)
820 //=================================================
821 // check System (SIM, UART, LDC ..... )
822 //=================================================
823 gsm_idle_ram_ctl->sleep_mode = sleep_mode;
824 #endif
825
826 if (sleep_mode == DO_NOT_SLEEP)
827 {
828 #if (GSM_IDLE_RAM != 0)
829 gsm_idle_ram_ctl->os_load = 0;
830 gsm_idle_ram_ctl->hw_timer = 0;
831 #endif // GSM_IDLE_RAM
832 return;
833 }
826 834
827 #if (CODE_VERSION != SIMULATION) 835 #if (CODE_VERSION != SIMULATION)
828 //================================================= 836 //=================================================
829 // Protect System structures 837 // Protect System structures
830 // must be called BEFORE INT_DisableIRQ() while 838 // must be called BEFORE INT_DisableIRQ() while
834 //================================================= 842 //=================================================
835 // Disable IRQ 843 // Disable IRQ
836 //================================================= 844 //=================================================
837 INT_DisableIRQ(); 845 INT_DisableIRQ();
838 #endif // NOT SIMULATION 846 #endif // NOT SIMULATION
839 //=================================================
840 // check System (SIM, UART, LDC ..... )
841 //=================================================
842 #if (CHIPSET == 15)
843 #if (WCP_PROF == 0)
844 sleep_mode = Check_Peripheral_App(); /* For Locosto */
845 #else
846 sleep_mode = DO_NOT_SLEEP; //Check_Peripheral_App(); /* For Locosto */
847 #endif
848 #else
849 sleep_mode = Cust_check_system();
850 #endif
851
852 #if (GSM_IDLE_RAM != 0)
853 //=================================================
854 // check System (SIM, UART, LDC ..... )
855 //=================================================
856 gsm_idle_ram_ctl->sleep_mode = sleep_mode;
857 #endif
858
859 if (sleep_mode == DO_NOT_SLEEP)
860 {
861 OS_system_Unprotect();
862 // free System structure
863 // Enable all IRQ
864 //l1_pwmgr_irq_dis_flag = 0;
865 #if (CODE_VERSION!=SIMULATION)
866 INT_EnableIRQ();
867 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
868 #endif
869 #if (GSM_IDLE_RAM != 0)
870 gsm_idle_ram_ctl->os_load = 0;
871 gsm_idle_ram_ctl->hw_timer = 0;
872 #endif // GSM_IDLE_RAM
873 return;
874 }
875
876 847
877 #if (OP_L1_STANDALONE == 0) 848 #if (OP_L1_STANDALONE == 0)
878 /*GC_Sleep(); OMAPS00134004*/ 849 /*GC_Sleep(); OMAPS00134004*/
879 #endif 850 #endif
880 //================================================= 851 //=================================================
881 // check OS loading 852 // check OS loading
882 //================================================= 853 //=================================================
883 OSload = OS_get_inactivity_ticks(); 854 OSload = OS_get_inactivity_ticks();
884 #if (CODE_VERSION!=SIMULATION) 855 #if 0 /* FreeCalypso TCS211 reconstruction */
885 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){ 856 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){
886 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD; 857 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD;
887 l1_pwmgr_debug.fail_ret_val = OSload; 858 l1_pwmgr_debug.fail_ret_val = OSload;
888 } 859 }
889 #endif //NOT SIMULATION 860 #endif
890 861
891 //================================================= 862 //=================================================
892 // check HW Timers loading 863 // check HW Timers loading
893 //================================================= 864 //=================================================
894 HWtimer= l1s_get_HWTimers_ticks(); 865 HWtimer= l1s_get_HWTimers_ticks();
895 #if (CODE_VERSION!=SIMULATION) 866 #if 0 /* FreeCalypso TCS211 reconstruction */
896 if (HWtimer == 0){ 867 if (HWtimer == 0){
897 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_HWTIMER; 868 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_HWTIMER;
898 l1_pwmgr_debug.fail_ret_val = 0; 869 l1_pwmgr_debug.fail_ret_val = 0;
899 } 870 }
900 #endif //NOT SIMULATION 871 #endif
901 872
902 #if (GSM_IDLE_RAM != 0) 873 #if (GSM_IDLE_RAM != 0)
903 //================================================= 874 //=================================================
904 // check OS loading 875 // check OS loading
905 //================================================= 876 //=================================================
920 #if L1_GPRS 891 #if L1_GPRS
921 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle(); 892 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle();
922 #else 893 #else
923 min_time_gauging = -1; // not used 894 min_time_gauging = -1; // not used
924 #endif 895 #endif
925 #if (CODE_VERSION!=SIMULATION) 896 #if 0 /* FreeCalypso TCS211 reconstruction */
926 if (min_time_gauging == 0){ 897 if (min_time_gauging == 0){
927 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_MINTIMEGAUGING; 898 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_MINTIMEGAUGING;
928 l1_pwmgr_debug.fail_ret_val = 0; 899 l1_pwmgr_debug.fail_ret_val = 0;
929 } 900 }
930 #endif // NOT SIMULATION 901 #endif // NOT SIMULATION
931 902
932 903
933 #if (OP_BT == 1) 904 #if (OP_BT == 1)
934 hci_ll_status = hci_ll_ok_for_sleep(); 905 hci_ll_status = hci_ll_ok_for_sleep();
939 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames 910 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames
940 // if MS can go in deep sleep 911 // if MS can go in deep sleep
941 if ( !OSload 912 if ( !OSload
942 || !HWtimer 913 || !HWtimer
943 || !min_time_gauging 914 || !min_time_gauging
944 #if (CHIPSET != 15)
945 || ((sleep_mode != CLOCK_STOP) && ((why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (why_big_sleep == BIG_SLEEP_DUE_TO_SIM))) 915 || ((sleep_mode != CLOCK_STOP) && ((why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (why_big_sleep == BIG_SLEEP_DUE_TO_SIM)))
946 #endif
947 #if (OP_BT == 1) 916 #if (OP_BT == 1)
948 || !hci_ll_status 917 || !hci_ll_status
949 #endif 918 #endif
950 ) 919 )
951 { 920 {
973 flag_traffic_controller_state = 1; 942 flag_traffic_controller_state = 1;
974 CSMI_TrafficControllerOn(); 943 CSMI_TrafficControllerOn();
975 } 944 }
976 #endif 945 #endif
977 946
978 #if (CHIPSET != 15)
979 SER_WakeUpUarts(); // Wake up Uarts 947 SER_WakeUpUarts(); // Wake up Uarts
980 #else
981 // To be checked if this needs a change
982 #endif
983 948
984 #if (GSM_IDLE_RAM != 0) 949 #if (GSM_IDLE_RAM != 0)
985 // The traffic controller state shall be restored as it was before 950 // The traffic controller state shall be restored as it was before
986 // calling SER_WakeUpUarts. Do not disable it if an interrup occured 951 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
987 // in between and activated the traffic controller. 952 // in between and activated the traffic controller.
990 CSMI_TrafficControllerOff(); 955 CSMI_TrafficControllerOff();
991 } 956 }
992 flag_traffic_controller_state = 0; 957 flag_traffic_controller_state = 0;
993 #endif 958 #endif
994 #endif 959 #endif
995 #if (CODE_VERSION!=SIMULATION) 960 #if 0 /* FreeCalypso TCS211 reconstruction */
996 l1_trace_fail_sleep(FAIL_SLEEP_OSTIMERGAUGE, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val); 961 l1_trace_fail_sleep(FAIL_SLEEP_OSTIMERGAUGE, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
997 #endif 962 #endif
998 return; 963 return;
999 } 964 }
1000 //================================================= 965 //=================================================
1062 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) || 1027 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) ||
1063 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) ) 1028 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) )
1064 l1s.pw_mgr.sleep_performed = FRAME_STOP; 1029 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1065 1030
1066 1031
1067
1068 #if (CHIPSET != 15)
1069 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7)) 1032 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7))
1070 { 1033 {
1071 #if (CODE_VERSION != SIMULATION) 1034 #if (CODE_VERSION != SIMULATION)
1072 OS_system_Unprotect(); // free System structure 1035 OS_system_Unprotect(); // free System structure
1073 INT_EnableIRQ(); // Enable all IRQ 1036 INT_EnableIRQ(); // Enable all IRQ
1100 flag_traffic_controller_state = 0; 1063 flag_traffic_controller_state = 0;
1101 #endif 1064 #endif
1102 #endif // NOT SIMULATION 1065 #endif // NOT SIMULATION
1103 return; 1066 return;
1104 } 1067 }
1105 #else // CHIPSET == 15 1068
1106
1107
1108
1109 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP)
1110 {
1111
1112 #if (CODE_VERSION != SIMULATION)
1113 UWORD8 local_sleep_status;
1114
1115
1116 local_sleep_status = Peripheral_interface[UART_ID](SLEEP_CMD);
1117 sleep_status = local_sleep_status;
1118 if(local_sleep_status == 0)
1119 {
1120 l1_pwmgr_debug.fail_id = UART_ID;
1121 l1_pwmgr_debug.fail_ret_val = sleep_status;
1122 }
1123
1124 OS_system_Unprotect();
1125 local_sleep_status = Peripheral_interface[MADC_AS_ID](SLEEP_CMD); /* Call MADC & Stereo Sleep before I2C */
1126 OS_system_protect();
1127 sleep_status &= local_sleep_status;
1128 if(local_sleep_status == 0)
1129 {
1130 l1_pwmgr_debug.fail_id = MADC_AS_ID;
1131 l1_pwmgr_debug.fail_ret_val = sleep_status;
1132 }
1133
1134 local_sleep_status = Peripheral_interface[USB_ID](SLEEP_CMD);
1135 sleep_status &= local_sleep_status;
1136 if(local_sleep_status == 0)
1137 {
1138 l1_pwmgr_debug.fail_id = USB_ID;
1139 l1_pwmgr_debug.fail_ret_val = sleep_status;
1140 }
1141
1142 local_sleep_status = Peripheral_interface[USIM_ID](SLEEP_CMD);
1143 sleep_status &= local_sleep_status;
1144 if(local_sleep_status == 0)
1145 {
1146 l1_pwmgr_debug.fail_id = USIM_ID;
1147 l1_pwmgr_debug.fail_ret_val = sleep_status;
1148 }
1149
1150 local_sleep_status = Peripheral_interface[I2C_ID](SLEEP_CMD);
1151 sleep_status &= local_sleep_status;
1152 if(local_sleep_status == 0)
1153 {
1154 l1_pwmgr_debug.fail_id = I2C_ID;
1155 l1_pwmgr_debug.fail_ret_val = sleep_status;
1156 }
1157
1158 local_sleep_status = Peripheral_interface[LCD_ID](SLEEP_CMD);
1159 sleep_status &= local_sleep_status;
1160 if(local_sleep_status == 0)
1161 {
1162 l1_pwmgr_debug.fail_id = LCD_ID;
1163 l1_pwmgr_debug.fail_ret_val = sleep_status;
1164 }
1165
1166 local_sleep_status = Peripheral_interface[CAMERA_ID](SLEEP_CMD);
1167 sleep_status &= local_sleep_status;
1168 if(local_sleep_status == 0)
1169 {
1170 l1_pwmgr_debug.fail_id = CAMERA_ID;
1171 l1_pwmgr_debug.fail_ret_val = sleep_status;
1172 }
1173 local_sleep_status = Peripheral_interface[BCI_ID](SLEEP_CMD);
1174 sleep_status &= local_sleep_status;
1175 if(local_sleep_status == 0)
1176 {
1177 l1_pwmgr_debug.fail_id = BCI_ID;
1178 l1_pwmgr_debug.fail_ret_val = sleep_status;
1179 }
1180
1181 #endif // NOT SIMULATION
1182 if(!sleep_status)
1183 {
1184
1185 #if (OP_L1_STANDALONE == 0)
1186 /*GC_Wakeup(); OMAPS00134004*/
1187 #endif
1188
1189 #if (CODE_VERSION != SIMULATION)
1190 OS_system_Unprotect();
1191 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1192 #endif // NOT SIMULATION
1193 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550
1194 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD); //OMAPS00090550
1195 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD); //OMAPS00090550
1196 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550
1197 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550
1198 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550
1199 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550
1200 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger interface//OMAPS00090550
1201 INT_EnableIRQ();
1202 return;
1203 }
1204 }
1205
1206 #endif // CHIPSET == 15
1207
1208 #if (CHIPSET != 15)
1209 // update previous sleep 1069 // update previous sleep
1210 previous_sleep = l1s.pw_mgr.sleep_performed; 1070 previous_sleep = l1s.pw_mgr.sleep_performed;
1211 #endif
1212 1071
1213 1072
1214 #if (CODE_VERSION != SIMULATION) 1073 #if (CODE_VERSION != SIMULATION)
1215 1074
1216 #if (CHIPSET == 12) || (CHIPSET == 15) 1075 #if (CHIPSET == 12) || (CHIPSET == 15)
1244 // (used when the MS lost the network: in this case the deep sleep may be used) 1103 // (used when the MS lost the network: in this case the deep sleep may be used)
1245 if (l1a_l1s_com.mode == CS_MODE0) 1104 if (l1a_l1s_com.mode == CS_MODE0)
1246 { 1105 {
1247 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE*8,DEFAULT_32KHZ_VALUE); 1106 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE*8,DEFAULT_32KHZ_VALUE);
1248 } 1107 }
1249
1250 #if (CHIPSET == 15)
1251
1252
1253 /* These APIs are to be provided by BSP */
1254 // Disable_APC_BG();
1255 gpio_sleep(); //LCD_Floating Pin Fix
1256 DBB_Configure_DS();
1257
1258 //gpio_sleep(); //LCD_Floating Pin Fix
1259
1260 #endif
1261
1262
1263 } 1108 }
1264 #if (CHIPSET == 15)
1265 else
1266 {
1267 //DBB_Configure_BS(); // Not used
1268 }
1269 #endif
1270
1271
1272 #if (CHIPSET == 15)
1273 // The following command writes '0' into CKM_OCPCLK register in DRP;
1274 // This is done before disabling DPLL
1275 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
1276 // Bit 0: 0 ?OCP clock is the DCXO clock.
1277 // 1 ?OCP clock is the divided DSP clock
1278 // Bit 31:1 Not Used
1279 (drp_regs->CKM_OCPCLKL) &= (~(0x1));
1280 asm(" NOP");
1281 asm(" NOP");
1282 #endif
1283
1284 1109
1285 1110
1286 //============================================== 1111 //==============================================
1287 // disable DPLL (do not provide clk to DSP & RIF (RIF)) 1112 // disable DPLL (do not provide clk to DSP & RIF (RIF))
1288 //============================================== 1113 //==============================================
1292 #endif 1117 #endif
1293 1118
1294 //============================================== 1119 //==============================================
1295 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB) 1120 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
1296 //============================================== 1121 //==============================================
1297 #if (ANLG_FAM != 11)
1298 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc); 1122 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc);
1299 #else
1300 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS
1301 #endif
1302 1123
1303 #if (OP_BT == 1) 1124 #if (OP_BT == 1)
1304 hci_ll_go_to_sleep(); 1125 hci_ll_go_to_sleep();
1305 #endif 1126 #endif
1306 //================================================= 1127 //=================================================
1307 // STop SPI ..... 1128 // STop SPI .....
1308 //================================================= 1129 //=================================================
1309 1130
1310 #if(CHIPSET != 15) 1131 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
1311 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
1312 #endif
1313 #endif // NOT SIMULATION 1132 #endif // NOT SIMULATION
1314 1133
1315 1134
1316 //================================================= 1135 //=================================================
1317 // CQ19599: For Calypso+ chipset, extended page mode 1136 // CQ19599: For Calypso+ chipset, extended page mode
1428 1247
1429 //========================================================== 1248 //==========================================================
1430 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized 1249 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized
1431 //========================================================== 1250 //==========================================================
1432 1251
1433 #if(CHIPSET != 15) 1252 UWORD16 clocks_stopped; //OMAPS90550- new
1434 UWORD16 clocks_stopped; //OMAPS90550- new
1435 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status); 1253 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
1436 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT) 1254 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
1437 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN); 1255 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN);
1438 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT) 1256 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
1439 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001); 1257 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001);
1440 #else
1441 // Nothing to be done as it is taken care by Locosto_Configure_BS
1442 #endif
1443 1258
1444 #if (W_A_CALYPSO_BUG_01435 == 1) 1259 #if (W_A_CALYPSO_BUG_01435 == 1)
1445 f_arm_sleep_cmd(BIG_SLEEP); 1260 f_arm_sleep_cmd(BIG_SLEEP);
1446 #else 1261 #else
1447 1262
1472 #if (GSM_IDLE_RAM_DEBUG == 1) 1287 #if (GSM_IDLE_RAM_DEBUG == 1)
1473 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1 1288 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1
1474 #endif 1289 #endif
1475 1290
1476 1291
1477 l1s_wakeup(); 1292 l1s_wakeup();
1478
1479 #if (CHIPSET == 15)
1480 // The following command writes '1' into CKM_OCPCLK register in DRP;
1481 // This is done after the DPLL is up
1482 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
1483 // Bit 0: 0 ?OCP clock is the DCXO clock.
1484 // 1 ?OCP clock is the divided DSP clock
1485 // Bit 31:1 Not Used
1486 (drp_regs->CKM_OCPCLKL) |= (0x1);
1487 asm(" NOP");
1488 asm(" NOP");
1489 #endif
1490 1293
1491 last_wakeup = l1s.actual_time.fn_mod42432; 1294 last_wakeup = l1s.actual_time.fn_mod42432;
1492 1295
1493 if (last_wakeup == sleep_time) 1296 if (last_wakeup == sleep_time)
1494 // sleep duration == 0 -> wakeup in the same frame as sleep 1297 // sleep duration == 0 -> wakeup in the same frame as sleep
1514 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP ) 1317 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1515 { 1318 {
1516 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN; 1319 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN;
1517 UWORD8 local_sleep_status; 1320 UWORD8 local_sleep_status;
1518 1321
1519
1520 #if (CHIPSET == 15)
1521
1522 DBB_Wakeup_DS();
1523
1524 gpio_wakeup(); //LCD_Floating Pin Fix
1525
1526 /* These APIs to be provided by BSP */
1527 //Enable_APC_BG();
1528 //BT_Wakeup();
1529 //IRDA_Wakeup();
1530 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550
1531 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD);//OMAPS00090550
1532 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD);//OMAPS00090550
1533 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550
1534 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550
1535 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550
1536
1537 OS_system_Unprotect();
1538 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550
1539 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger//OMAPS00090550
1540 OS_system_protect();
1541 //added for OMAPS00090550 warning removal
1542 if(local_sleep_status == 0)
1543 {
1544 l1_pwmgr_debug.fail_ret_val = local_sleep_status;
1545 }
1546 //upto this OMAPS00090550
1547
1548
1549 #endif
1550 l1dmacro_RF_wakeup(); 1322 l1dmacro_RF_wakeup();
1551 1323
1552 } 1324 }
1553 1325
1554 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) 1326 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
1562 #endif 1334 #endif
1563 1335
1564 //================================================= 1336 //=================================================
1565 //if CLOCK_STOP or FRAME-STOP : ReStart SPI 1337 //if CLOCK_STOP or FRAME-STOP : ReStart SPI
1566 //================================================= 1338 //=================================================
1567 #if(CHIPSET != 15) 1339 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
1568 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
1569 #endif
1570 1340
1571 //================================================= 1341 //=================================================
1572 // Wake up ABB 1342 // Wake up ABB
1573 //================================================= 1343 //=================================================
1574 #if (ANLG_FAM != 11)
1575 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc); 1344 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc);
1576 #else
1577 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS
1578 #endif
1579 1345
1580 #if (OP_BT == 1) 1346 #if (OP_BT == 1)
1581 hci_ll_wake_up(); 1347 hci_ll_wake_up();
1582 #endif 1348 #endif
1583 #endif //CODE VERSION 1349 #endif //CODE VERSION
1655 CSMI_TrafficControllerOn(); 1421 CSMI_TrafficControllerOn();
1656 } 1422 }
1657 #endif 1423 #endif
1658 1424
1659 1425
1660
1661 #if (CHIPSET != 15)
1662 SER_WakeUpUarts(); // Wake up Uarts 1426 SER_WakeUpUarts(); // Wake up Uarts
1663 #else
1664 // To be checked if this needs a change
1665 #endif
1666 1427
1667 1428
1668 #if (GSM_IDLE_RAM != 0) 1429 #if (GSM_IDLE_RAM != 0)
1669 // The traffic controller state shall be restored as it was before 1430 // The traffic controller state shall be restored as it was before
1670 // calling SER_WakeUpUarts. Do not disable it if an interrup occured 1431 // calling SER_WakeUpUarts. Do not disable it if an interrup occured