FreeCalypso > hg > tcs211-l1-reconst
comparison chipsetsw/layer1/cfile/l1_func.c @ 100:ba58ce852caf
l1_func.c: initial import of LoCosto source
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Thu, 07 Apr 2016 19:16:48 +0000 |
parents | 6814a6bced4f |
children | a103d40accc2 |
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99:3d214116a5ba | 100:ba58ce852caf |
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1 /* dummy C source file */ | 1 /************* Revision Controle System Header ************* |
2 * GSM Layer 1 software | |
3 * L1_FUNC.C | |
4 * | |
5 * Filename l1_func.c | |
6 * Copyright 2003 (C) Texas Instruments | |
7 * | |
8 ************* Revision Controle System Header *************/ | |
9 | |
10 #define L1_FUNC_C | |
11 | |
12 #include "l1_macro.h" | |
13 #include "l1_confg.h" | |
14 | |
15 #if (CODE_VERSION == SIMULATION) | |
16 #include <string.h> | |
17 #include "l1_types.h" | |
18 #include "sys_types.h" | |
19 #include "l1_const.h" | |
20 #include "l1_time.h" | |
21 #include "l1_signa.h" | |
22 #if TESTMODE | |
23 #include "l1tm_defty.h" | |
24 #endif | |
25 #if (AUDIO_TASK == 1) | |
26 #include "l1audio_const.h" | |
27 #include "l1audio_cust.h" | |
28 #include "l1audio_defty.h" | |
29 #endif | |
30 #if (L1_GTT == 1) | |
31 #include "l1gtt_const.h" | |
32 #include "l1gtt_defty.h" | |
33 #endif | |
34 #if (L1_MP3 == 1) | |
35 #include "l1mp3_defty.h" | |
36 #endif | |
37 #if (L1_MIDI == 1) | |
38 #include "l1midi_defty.h" | |
39 #endif | |
40 //ADDED FOR AAC | |
41 #if (L1_AAC == 1) | |
42 #include "l1aac_defty.h" | |
43 #endif | |
44 #include "l1_defty.h" | |
45 #include "cust_os.h" | |
46 #include "l1_msgty.h" | |
47 #include "l1_varex.h" | |
48 #include "l1_proto.h" | |
49 #include "l1_mftab.h" | |
50 #include "l1_tabs.h" | |
51 #include "l1_ver.h" | |
52 | |
53 #if L1_GPRS | |
54 #include "l1p_cons.h" | |
55 #include "l1p_msgt.h" | |
56 #include "l1p_deft.h" | |
57 #include "l1p_vare.h" | |
58 #include "l1p_tabs.h" | |
59 #include "l1p_macr.h" | |
60 #endif | |
61 | |
62 #include "l1_rf2.h" | |
63 #include <stdio.h> | |
64 #include "sim_cfg.h" | |
65 #include "sim_cons.h" | |
66 #include "sim_def.h" | |
67 #include "sim_var.h" | |
68 | |
69 #else | |
70 | |
71 #include <string.h> | |
72 #include "l1_types.h" | |
73 #include "sys_types.h" | |
74 #include "l1_const.h" | |
75 #include "l1_rf61.h" | |
76 #include "l1_time.h" | |
77 #include "l1_signa.h" | |
78 | |
79 #if TESTMODE | |
80 #include "l1tm_defty.h" | |
81 #endif | |
82 #if (AUDIO_TASK == 1) | |
83 #include "l1audio_const.h" | |
84 #include "l1audio_cust.h" | |
85 #include "l1audio_defty.h" | |
86 #endif | |
87 #if (L1_GTT == 1) | |
88 #include "l1gtt_const.h" | |
89 #include "l1gtt_defty.h" | |
90 #endif | |
91 #if (L1_MP3 == 1) | |
92 #include "l1mp3_defty.h" | |
93 #endif | |
94 #if (L1_MIDI == 1) | |
95 #include "l1midi_defty.h" | |
96 #endif | |
97 //ADDED FOR AAC | |
98 #if (L1_AAC == 1) | |
99 #include "l1aac_defty.h" | |
100 #endif | |
101 #include "l1_defty.h" | |
102 #include "cust_os.h" | |
103 #include "l1_msgty.h" | |
104 #include "l1_varex.h" | |
105 #include "l1_proto.h" | |
106 #include "l1_mftab.h" | |
107 #include "l1_tabs.h" | |
108 #include "l1_ver.h" | |
109 #include "tpudrv.h" | |
110 | |
111 #include "mem.h" | |
112 #include "inth.h" | |
113 #include "clkm.h" | |
114 #include "rhea_arm.h" | |
115 #include "dma.h" | |
116 #include "ulpd.h" | |
117 #include "leadapi.h" | |
118 | |
119 #if (OP_L1_STANDALONE) | |
120 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
121 (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) | |
122 #include "dynamic_clock.h" | |
123 #endif | |
124 #endif | |
125 | |
126 | |
127 #if L1_GPRS | |
128 #include "l1p_cons.h" | |
129 #include "l1p_msgt.h" | |
130 #include "l1p_deft.h" | |
131 #include "l1p_vare.h" | |
132 #include "l1p_tabs.h" | |
133 #include "l1p_macr.h" | |
134 #endif | |
135 | |
136 #endif | |
137 #include "l1_trace.h" | |
138 | |
139 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7)) | |
140 extern void L1_trace_string(char *s); | |
141 #endif | |
142 | |
143 | |
144 #if (CODE_VERSION != SIMULATION) | |
145 | |
146 /* DSP patch */ | |
147 #if (DWNLD == NO_DWNLD) | |
148 const UWORD8 patch_array[1]; | |
149 const UWORD8 DspCode_array[1] ; | |
150 const UWORD8 DspData_array[1]; | |
151 #elif (DWNLD == PATCH_DWNLD) | |
152 extern const UWORD8 patch_array[] ; | |
153 const UWORD8 DspCode_array[1] ; | |
154 const UWORD8 DspData_array[1]; | |
155 #elif (DWNLD == DSP_DWNLD) | |
156 const UWORD8 patch_array[1] ; | |
157 extern const UWORD8 DspCode_array[] ; | |
158 extern const UWORD8 DspData_array[]; | |
159 #else | |
160 extern const UWORD8 patch_array[] ; | |
161 extern const UWORD8 DspCode_array[] ; | |
162 extern const UWORD8 DspData_array[]; | |
163 #endif | |
164 | |
165 extern const UWORD8 bootCode[] ; | |
166 UWORD32 fn_prev; // Added as a debug stage.. | |
167 /* DSP patch */ | |
168 | |
169 | |
170 /*-------------------------------------------------------*/ | |
171 /* Prototypes of internal functions used in this file. */ | |
172 /*-------------------------------------------------------*/ | |
173 void l1s_init_voice_blocks (void); | |
174 | |
175 /*-------------------------------------------------------*/ | |
176 /* Prototypes of external functions used in this file. */ | |
177 /*-------------------------------------------------------*/ | |
178 void l1dmacro_synchro (UWORD32 when, UWORD32 value); | |
179 void LA_ReleaseLead(void); | |
180 #if (CODE_VERSION != SIMULATION) | |
181 void l1s_audio_path_control (UWORD16 FIR_selection, UWORD16 audio_loop); | |
182 #endif | |
183 | |
184 #if (L1_GPRS) | |
185 // external functions from GPRS implementation | |
186 void initialize_l1pvar(void); | |
187 void l1pa_reset_cr_freq_list(void); | |
188 #endif | |
189 /*-------------------------------------------------------*/ | |
190 /* dsp_power_on() */ | |
191 /*-------------------------------------------------------*/ | |
192 /* Parameters : */ | |
193 /* Return : */ | |
194 /* Functionality : */ | |
195 /* Remarq : USART Buffer is 256 characters. While USART*/ | |
196 /* is not run during Application_Initialize */ | |
197 /* (hisrs not served because Nucleus scheduler*/ | |
198 /* is not running yet) : */ | |
199 /* ==> check string size < 256 !!!!!! */ | |
200 /*-------------------------------------------------------*/ | |
201 void dsp_power_on(void) | |
202 { | |
203 UWORD16 dsp_start_address =0 ;//omaps00090550 | |
204 UWORD16 param_size; | |
205 #if IDS | |
206 UWORD16 param_size2; | |
207 #endif | |
208 | |
209 API i; | |
210 API *pt; | |
211 volatile WORD16 j; | |
212 | |
213 T_NDB_MCU_DSP * dsp_ndb_ptr; | |
214 | |
215 #if (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
216 static API_SIGNED param_tab[] = { | |
217 | |
218 D_TRANSFER_RATE, | |
219 | |
220 // ..................Latencies | |
221 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM, | |
222 | |
223 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM, | |
224 | |
225 //...................p_gprs_install_adress | |
226 D_HOLE, | |
227 | |
228 //...................d_misc_config | |
229 D_MISC_CONFIG, | |
230 | |
231 | |
232 //...................d_cn_sw_workaround | |
233 C_DSP_SW_WORK_AROUND, | |
234 | |
235 //...................Reserved | |
236 D_HOLE, D_HOLE, | |
237 D_HOLE, D_HOLE, | |
238 | |
239 //...................Frequency burst | |
240 D_FB_MARGIN_BEG, D_FB_MARGIN_END, | |
241 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
242 D_FB_THR_DET_TRACK, | |
243 //...................Demodulation | |
244 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
245 D_DEM_POND_RED, | |
246 //...................TCH Full Speech | |
247 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
248 D_GU, D_GO, D_ATTMAX, | |
249 D_SM, D_B, | |
250 | |
251 //...................V42 bis | |
252 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX, | |
253 D_V42B_RESET_DELAY, | |
254 | |
255 //...................TCH Half Speech | |
256 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
257 D_GU_HR, D_GO_HR, D_B_HR, | |
258 D_SM_HR, D_ATTMAX_HR, | |
259 | |
260 //...................Added variables for EFR | |
261 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
262 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
263 C_SM_EFR, C_ATTMAX_EFR, | |
264 | |
265 //...................Full rate variables | |
266 D_SD_MIN_THR_TCHFS, | |
267 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
268 | |
269 //...................TCH Half Speech | |
270 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
271 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, | |
272 | |
273 //...................TCH Enhanced Full Rate Speech | |
274 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
275 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI, | |
276 | |
277 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
278 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
279 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
280 | |
281 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, | |
282 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT | |
283 }; | |
284 param_size = 79; | |
285 | |
286 #if (OP_L1_STANDALONE) | |
287 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
288 (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) | |
289 /* Dynamic clock configuration */ | |
290 param_tab[0] = p_dynamic_clock_cfg->d_transfer_rate; | |
291 param_tab[1] = p_dynamic_clock_cfg->d_lat_mcu_bridge; | |
292 param_tab[2] = p_dynamic_clock_cfg->d_lat_mcu_hom2sam; | |
293 param_tab[3] = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access; | |
294 param_tab[4] = p_dynamic_clock_cfg->d_lat_dsp_after_sam; | |
295 #endif | |
296 #endif | |
297 | |
298 #elif (DSP == 33) | |
299 static API_SIGNED param_tab[] = { | |
300 | |
301 D_TRANSFER_RATE, | |
302 | |
303 // ..................Latencies | |
304 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM, | |
305 | |
306 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM, | |
307 | |
308 //...................p_gprs_install_adress | |
309 D_HOLE, | |
310 | |
311 //...................d_misc_config | |
312 D_MISC_CONFIG, | |
313 | |
314 //...................d_cn_sw_workaround | |
315 C_DSP_SW_WORK_AROUND, | |
316 | |
317 #if DCO_ALGO | |
318 //...................d_cn_dco_param | |
319 C_CN_DCO_PARAM, | |
320 #else | |
321 //.................. Reserved | |
322 D_HOLE, | |
323 #endif | |
324 | |
325 //...................Reserved | |
326 D_HOLE, D_HOLE, | |
327 D_HOLE, | |
328 | |
329 //...................Frequency burst | |
330 D_FB_MARGIN_BEG, D_FB_MARGIN_END, | |
331 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
332 D_FB_THR_DET_TRACK, | |
333 //...................Demodulation | |
334 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
335 D_DEM_POND_RED, | |
336 //...................TCH Full Speech | |
337 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
338 D_GU, D_GO, D_ATTMAX, | |
339 D_SM, D_B, | |
340 | |
341 //...................V42 bis | |
342 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX, | |
343 D_V42B_RESET_DELAY, | |
344 | |
345 //...................TCH Half Speech | |
346 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
347 D_GU_HR, D_GO_HR, D_B_HR, | |
348 D_SM_HR, D_ATTMAX_HR, | |
349 | |
350 //...................Added variables for EFR | |
351 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
352 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
353 C_SM_EFR, C_ATTMAX_EFR, | |
354 | |
355 //...................Full rate variables | |
356 D_SD_MIN_THR_TCHFS, | |
357 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
358 | |
359 //...................TCH Half Speech | |
360 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
361 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, | |
362 | |
363 //...................TCH Enhanced Full Rate Speech | |
364 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
365 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI, | |
366 | |
367 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
368 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
369 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
370 | |
371 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, | |
372 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT | |
373 }; | |
374 param_size = 79; | |
375 | |
376 #if (OP_L1_STANDALONE) | |
377 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
378 (CHIPSET == 11) || (CHIPSET == 12) | |
379 /* Dynamic clock configuration */ | |
380 param_tab[0] = p_dynamic_clock_cfg->d_transfer_rate; | |
381 param_tab[1] = p_dynamic_clock_cfg->d_lat_mcu_bridge; | |
382 param_tab[2] = p_dynamic_clock_cfg->d_lat_mcu_hom2sam; | |
383 param_tab[3] = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access; | |
384 param_tab[4] = p_dynamic_clock_cfg->d_lat_dsp_after_sam; | |
385 #endif | |
386 #endif | |
387 | |
388 #else | |
389 | |
390 #if (VOC == FR) | |
391 static API_SIGNED param_tab[] = { | |
392 //...................Frequency burst | |
393 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
394 D_FB_THR_DET_TRACK, | |
395 //...................Demodulation | |
396 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
397 D_DEM_POND_RED, D_HOLE, D_HOLE, | |
398 //...................TCH Full Speech | |
399 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
400 D_GU, D_GO, D_ATTMAX, | |
401 D_SM, D_B, D_SD_MIN_THR_TCHFS, | |
402 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
403 //...................TCH Half Speech | |
404 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
405 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, D_WED_FIL_INI, | |
406 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
407 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
408 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
409 D_DSP_TEST | |
410 }; | |
411 param_size = 38; | |
412 #endif | |
413 | |
414 #if (VOC == FR_HR) | |
415 static API_SIGNED param_tab[] = { | |
416 //...................Frequency burst | |
417 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
418 D_FB_THR_DET_TRACK, | |
419 //...................Demodulation | |
420 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
421 D_DEM_POND_RED, D_HOLE, D_HOLE, | |
422 //...................TCH Full Speech | |
423 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
424 D_GU, D_GO, D_ATTMAX, | |
425 D_SM, D_B, | |
426 //...................TCH Half Speech | |
427 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
428 D_GU_HR, D_GO_HR, D_B_HR, | |
429 D_SM_HR, D_ATTMAX_HR, | |
430 //...................TCH Full Speech | |
431 D_SD_MIN_THR_TCHFS, | |
432 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
433 //...................TCH Half Speech | |
434 D_SD_MIN_THR_TCHHS, | |
435 D_MA_MIN_THR_TCHHS, | |
436 D_SD_AV_THR_TCHHS, | |
437 D_MD_MAX_THR_TCHHS, | |
438 D_MD1_MAX_THR_TCHHS, | |
439 D_WED_FIL_INI, | |
440 D_WED_FIL_TC, | |
441 D_X_MIN, | |
442 D_X_MAX, | |
443 D_SLOPE, | |
444 D_Y_MIN, | |
445 D_Y_MAX, | |
446 D_WED_DIFF_THRESHOLD, | |
447 D_MABFI_MIN_THR_TCHHS, | |
448 D_FACCH_THR, | |
449 D_DSP_TEST | |
450 }; | |
451 param_size = 46; | |
452 #endif | |
453 | |
454 #if (VOC == FR_EFR) | |
455 static API_SIGNED param_tab[] = { | |
456 //...................Frequency burst | |
457 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
458 D_FB_THR_DET_TRACK, | |
459 //...................Demodulation | |
460 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
461 D_DEM_POND_RED, D_HOLE, D_HOLE, | |
462 | |
463 //...................TCH Full Speech | |
464 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
465 D_GU, D_GO, D_ATTMAX, | |
466 D_SM, D_B, | |
467 | |
468 //...................Added variables for EFR | |
469 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
470 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
471 C_SM_EFR, C_ATTMAX_EFR, | |
472 | |
473 //...................Full rate variables | |
474 D_SD_MIN_THR_TCHFS, | |
475 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
476 | |
477 //...................TCH Enhanced Full Rate Speech | |
478 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
479 D_MD1_MAX_THR_TCHEFS, D_HOLE, D_WED_FIL_INI, | |
480 | |
481 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
482 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
483 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
484 D_DSP_TEST | |
485 }; | |
486 param_size = 46; | |
487 #endif | |
488 | |
489 #if (VOC == FR_HR_EFR) | |
490 static API_SIGNED param_tab[] = { | |
491 //...................Frequency burst | |
492 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
493 D_FB_THR_DET_TRACK, | |
494 //...................Demodulation | |
495 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
496 D_DEM_POND_RED, D_HOLE, D_TRANSFER_RATE, | |
497 //...................TCH Full Speech | |
498 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
499 D_GU, D_GO, D_ATTMAX, | |
500 D_SM, D_B, | |
501 | |
502 //...................TCH Half Speech | |
503 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
504 D_GU_HR, D_GO_HR, D_B_HR, | |
505 D_SM_HR, D_ATTMAX_HR, | |
506 | |
507 //...................Added variables for EFR | |
508 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
509 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
510 C_SM_EFR, C_ATTMAX_EFR, | |
511 | |
512 //...................Full rate variables | |
513 D_SD_MIN_THR_TCHFS, | |
514 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
515 | |
516 //...................TCH Half Speech | |
517 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
518 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, | |
519 | |
520 //...................TCH Enhanced Full Rate Speech | |
521 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
522 D_MD1_MAX_THR_TCHEFS, D_HOLE, D_WED_FIL_INI, | |
523 | |
524 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
525 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
526 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
527 D_HOLE, | |
528 | |
529 //...................Data patch provisions | |
530 D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, | |
531 | |
532 //...................Version Number, TI Number | |
533 D_HOLE, D_HOLE, | |
534 | |
535 // ..................DSP page | |
536 D_DSP_TEST | |
537 | |
538 #if IDS | |
539 ,D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, | |
540 D_M1_THRES, D_MAX_OVSP_DL | |
541 #endif | |
542 | |
543 }; | |
544 param_size = 67; | |
545 #if IDS | |
546 // Take care to not erased "d_version_number, d_ti_version and d_dsp_page" wrote by DSP before ARM | |
547 // set PARAM memory | |
548 param_size2 = 5; | |
549 #endif | |
550 #endif | |
551 #endif // (end of DSP != 33 || DSP != 34 || DSP != 35 || DSP != 36) || (DSP != 37) || (DSP != 38) || (DSP != 39) | |
552 | |
553 // NDB pointer. | |
554 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR; | |
555 | |
556 | |
557 //------------- | |
558 // DSP STARTUP | |
559 //------------- | |
560 { | |
561 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
562 #if (CHIPSET == 1) | |
563 L1_trace_string ("\n\r\n\rGEMINI/POLESTAR test code\n\r-------------------------"); | |
564 #elif (CHIPSET == 2) | |
565 L1_trace_string ("\n\r\n\rHERCULES test code\n\r------------------"); | |
566 #elif (CHIPSET == 3) | |
567 L1_trace_string ("\n\r\n\rULYSSE/ULYSSE G0 test code\n\r--------------------------"); | |
568 #elif (CHIPSET == 4) | |
569 L1_trace_string ("\n\r\n\rSAMSON test code\n\r----------------"); | |
570 #elif (CHIPSET == 5) | |
571 L1_trace_string ("\n\r\n\rULYSSE G1 test code 13 MHz\n\r-------------------"); | |
572 #elif (CHIPSET == 6) | |
573 L1_trace_string ("\n\r\n\rULYSSE G1 test code 26 MHz\n\r-------------------"); | |
574 #elif (CHIPSET == 7) | |
575 L1_trace_string ("\n\r\n\rCALYPSO Rev A test code\n\r-------------------"); | |
576 #elif (CHIPSET == 8) | |
577 L1_trace_string ("\n\r\n\rCALYPSO Rev B test code\n\r-------------------"); | |
578 #elif (CHIPSET == 9) | |
579 L1_trace_string ("\n\r\n\rULYSSE C035 test code\n\r-------------------"); | |
580 #elif (CHIPSET == 10) || (CHIPSET == 11) | |
581 L1_trace_string ("\n\r\n\rCALYPSO C035 test code\n\r-------------------"); | |
582 #elif (CHIPSET == 12) | |
583 L1_trace_string ("\n\r\n\rCALYPSO PLUS test code\n\r-------------------"); | |
584 #elif (CHIPSET == 15) | |
585 L1_trace_string ("\n\r\n\rLOCOSTO test code\n\r-------------------"); | |
586 #endif | |
587 #endif | |
588 | |
589 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
590 /* Display Audio Configuration */ | |
591 L1_trace_string ("\n\rAUDIO: "); | |
592 #if (KEYBEEP) | |
593 L1_trace_string ("KB "); | |
594 #endif | |
595 #if (TONE) | |
596 L1_trace_string ("TN "); | |
597 #endif | |
598 #if (MELODY_E1) | |
599 L1_trace_string ("E1 "); | |
600 #endif | |
601 #if (MELODY_E2) | |
602 L1_trace_string ("E2 "); | |
603 #endif | |
604 #if (VOICE_MEMO) | |
605 L1_trace_string ("VM "); | |
606 #endif | |
607 #if (L1_VOICE_MEMO_AMR) | |
608 L1_trace_string ("VMA "); | |
609 #endif | |
610 #if (SPEECH_RECO) | |
611 L1_trace_string ("SR "); | |
612 #endif | |
613 #if (L1_NEW_AEC) | |
614 L1_trace_string ("NEWAEC "); | |
615 #elif (AEC) | |
616 L1_trace_string ("AEC "); | |
617 #endif | |
618 #if (L1_GTT) | |
619 L1_trace_string ("GTT "); | |
620 #endif | |
621 #if (FIR) | |
622 L1_trace_string ("FIR "); | |
623 #endif | |
624 #if (AUDIO_MODE) | |
625 L1_trace_string ("AUM "); | |
626 #endif | |
627 #if (L1_CPORT == 1) | |
628 L1_trace_string ("CPO "); | |
629 #endif | |
630 #if (L1_STEREOPATH == 1) | |
631 L1_trace_string ("STP "); | |
632 #endif | |
633 #if (L1_EXT_AUDIO_MGT == 1) | |
634 L1_trace_string ("EAM "); | |
635 #endif | |
636 L1_trace_string ("\n\r"); | |
637 #endif | |
638 // Release Lead reset before DSP code/patch download to insure proper reset of DSP | |
639 LA_ReleaseLead(); | |
640 | |
641 // Init PLL : PLONOFF =1, PLMU = 0010 (k=3), PLLNDIV=1, PLLDIV=0 | |
642 LA_InitialLeadBoot(bootCode); // Load the bootCode in API | |
643 LA_StartLead(CLKSTART); // LEAD_PLL_CNTL register (on MCU side) | |
644 // On SAMSON, only the LEAD reset is released | |
645 | |
646 // GSM 1.5 | |
647 //----------------------------------------------------------------- | |
648 // After RESET release, DSP is in SAM Mode ! while API_CNTR (0xF900) | |
649 // register is in reset state: HOM mode, PLL off, Bridge off. No ws | |
650 // are applied for MCU<-->API access !!!!! So, MCU must wait for | |
651 // end of Leadboot execution before accessing API. | |
652 wait_ARM_cycles(convert_nanosec_to_cycles(10000)); // wait 10us | |
653 | |
654 | |
655 if(l1_config.dwnld == NO_DWNLD) | |
656 // NO DOWNLOAD... | |
657 { | |
658 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
659 L1_trace_string ("\n\r-> No download !!"); | |
660 #endif | |
661 | |
662 // Wait for READY status from DSP. | |
663 while(*((volatile UWORD16 *)DOWNLOAD_STATUS) != LEAD_READY); | |
664 | |
665 // Set DSP start address. | |
666 dsp_start_address = DSP_START; | |
667 } | |
668 else | |
669 if(l1_config.dwnld == DSP_DWNLD) | |
670 // DSP CODE DOWNLOAD... | |
671 { | |
672 WORD32 load_result; | |
673 | |
674 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
675 #if (VOC == FR) | |
676 L1_trace_string ("\n\r-> Downloading FR DSP code..."); | |
677 #endif | |
678 | |
679 #if (VOC == FR_HR) | |
680 L1_trace_string ("\n\r-> Downloading FR&HR DSP code..."); | |
681 #endif | |
682 | |
683 #if (VOC == FR_EFR) | |
684 L1_trace_string ("\n\r-> Downloading FR&EFR DSP code..."); | |
685 #endif | |
686 | |
687 #if (VOC == FR_HR_EFR) | |
688 #if IDS | |
689 L1_trace_string ("\n\r-> Download FR&IDS DSP code..."); | |
690 #else | |
691 L1_trace_string ("\n\r-> Downloading 3VOC DSP code..."); | |
692 #endif | |
693 #endif | |
694 #endif | |
695 | |
696 // Download DSP code into DSP via API / bootcode. | |
697 load_result = LA_LoadPage(DspCode_array,0,0); | |
698 | |
699 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
700 if(load_result) | |
701 L1_trace_string ("\n\r-> Download FAILED !!"); | |
702 else | |
703 L1_trace_string ("\n\r-> ... finished !!"); | |
704 #endif | |
705 | |
706 #if (VOC == FR_HR) || (VOC == FR_EFR) || (VOC == FR_HR_EFR) | |
707 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
708 #if (VOC == FR_HR) | |
709 L1_trace_string ("\n\r-> Downloading FR&HR DSP data ROM..."); | |
710 #endif | |
711 | |
712 #if (VOC == FR_EFR) | |
713 L1_trace_string ("\n\r-> Downloading FR&EFR DSP data ROM..."); | |
714 #endif | |
715 | |
716 #if (VOC == FR_HR_EFR) | |
717 #if IDS | |
718 L1_trace_string ("\n\r-> Download FR&IDS DSP Data ROM..."); | |
719 #else | |
720 L1_trace_string ("\n\r-> Downloading 3VOC DSP DATA ROM..."); | |
721 #endif | |
722 #endif | |
723 #endif | |
724 | |
725 load_result = LA_LoadPage(DspData_array,1,0); | |
726 | |
727 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
728 if(load_result) | |
729 L1_trace_string ("\n\r-> Download FAILED !!"); | |
730 else | |
731 L1_trace_string ("\n\r-> ... finished !!"); | |
732 #endif | |
733 #endif | |
734 | |
735 // Set DSP start address; | |
736 dsp_start_address = DSP_START; | |
737 } | |
738 else | |
739 if(l1_config.dwnld == PATCH_DWNLD) | |
740 // DSP PATCH DOWNLOAD... | |
741 { | |
742 WORD32 load_result; | |
743 | |
744 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
745 L1_trace_string ("\n\r-> Downloading patch..."); | |
746 #endif | |
747 | |
748 // Download DSP patch into DSP via API / bootcode. | |
749 load_result = LA_LoadPage(patch_array,0,0); | |
750 | |
751 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
752 if(load_result) | |
753 L1_trace_string ("\n\r-> Download FAILED !!"); | |
754 else | |
755 L1_trace_string ("\n\r-> ... finished !!"); | |
756 #endif | |
757 | |
758 // Catch start address always from patch_file#.c. | |
759 dsp_start_address = (WORD16)patch_array[3]; | |
760 dsp_start_address <<= 8; | |
761 dsp_start_address += (WORD16)patch_array[2]; | |
762 | |
763 // if COFF2CP output, the file begins by a null tag | |
764 if(dsp_start_address == 0) | |
765 { | |
766 dsp_start_address = (WORD16)patch_array[13]; | |
767 dsp_start_address <<= 8; | |
768 dsp_start_address += (WORD16)patch_array[12]; | |
769 } | |
770 } | |
771 else | |
772 if(l1_config.dwnld == PATCH_DSP_DWNLD) | |
773 // DSP CODE DOWNLOAD + PATCH DOWNLOAD... | |
774 { | |
775 WORD32 load_result; | |
776 | |
777 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
778 #if (VOC == FR) | |
779 L1_trace_string ("\n\r-> Downloading FR DSP code..."); | |
780 #endif | |
781 | |
782 #if (VOC == FR_HR) | |
783 L1_trace_string ("\n\r-> Downloading FR&HR DSP code..."); | |
784 #endif | |
785 | |
786 #if (VOC == FR_EFR) | |
787 L1_trace_string ("\n\r-> Downloading FR&EFR DSP code..."); | |
788 #endif | |
789 | |
790 #if (VOC == FR_HR_EFR) | |
791 #if IDS | |
792 L1_trace_string ("\n\r-> Download FR&IDS DSP code..."); | |
793 #else | |
794 L1_trace_string ("\n\r-> Downloading 3VOC DSP code..."); | |
795 #endif | |
796 #endif | |
797 #endif | |
798 | |
799 // Download DSP code into DSP via API / bootcode. | |
800 load_result = LA_LoadPage(DspCode_array,0,0); | |
801 | |
802 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
803 if(load_result) | |
804 L1_trace_string ("\n\r-> Download FAILED !!"); | |
805 else | |
806 L1_trace_string ("\n\r-> ... finished !!"); | |
807 #endif | |
808 | |
809 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
810 L1_trace_string ("\n\r-> Downloading patch..."); | |
811 #endif | |
812 | |
813 // Download DSP patch into DSP via API / bootcode. | |
814 load_result = LA_LoadPage(patch_array,0,0); | |
815 | |
816 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
817 if(load_result) | |
818 L1_trace_string ("\n\r-> Download FAILED !!"); | |
819 else | |
820 L1_trace_string ("\n\r-> ... finished !!"); | |
821 #endif | |
822 | |
823 #if ((VOC == FR_HR) || (VOC == FR_EFR) || (VOC == FR_HR_EFR)) | |
824 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
825 #if (VOC == FR_HR) | |
826 L1_trace_string ("\n\r-> Downloading FR&HR DSP data ROM..."); | |
827 #endif | |
828 | |
829 #if (VOC == FR_EFR) | |
830 L1_trace_string ("\n\r-> Downloading FR&EFR DSP data ROM..."); | |
831 #endif | |
832 | |
833 #if (VOC == FR_HR_EFR) | |
834 #if IDS | |
835 L1_trace_string ("\n\r-> Download FR&IDS DSP data ROM..."); | |
836 #else | |
837 L1_trace_string ("\n\r-> Downloading 3VOC DSP data ROM..."); | |
838 #endif | |
839 #endif | |
840 #endif | |
841 | |
842 load_result = LA_LoadPage(DspData_array,1,0); | |
843 | |
844 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
845 if(load_result) | |
846 L1_trace_string ("\n\r-> Download FAILED !!"); | |
847 else | |
848 L1_trace_string ("\n\r-> ... finished !!"); | |
849 #endif | |
850 #endif | |
851 | |
852 | |
853 // Catch start address always from patch_file#.c. | |
854 dsp_start_address = (WORD16)patch_array[3]; | |
855 dsp_start_address <<= 8; | |
856 dsp_start_address += (WORD16)patch_array[2]; | |
857 | |
858 // if COFF2CP output, the file begins by a null tag | |
859 if(dsp_start_address == 0) | |
860 { | |
861 dsp_start_address = (WORD16)patch_array[13]; | |
862 dsp_start_address <<= 8; | |
863 dsp_start_address += (WORD16)patch_array[12]; | |
864 } | |
865 } | |
866 | |
867 #if (DSP == 16 || DSP == 17 || DSP == 30 || DSP == 31 || DSP == 32) | |
868 dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1; // PLL variable (multiply by 3 factor)+ Power consumpt. | |
869 dsp_ndb_ptr->d_pll_clkmod2 = CLKMOD2; // PLL variable (40 us lock time) | |
870 #endif | |
871 } | |
872 | |
873 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
874 L1_trace_string ("\n\r\n\r"); | |
875 #endif | |
876 | |
877 //-------------------------------------------------------------- | |
878 // Loading of NDB parameters....... | |
879 //-------------------------------------------------------------- | |
880 | |
881 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
882 // Initialize background control variable to No background. Background tasks can be launch in GPRS | |
883 // as in GSM. | |
884 dsp_ndb_ptr->d_background_enable = 0; | |
885 dsp_ndb_ptr->d_background_abort = 0; | |
886 dsp_ndb_ptr->d_background_state = 0; | |
887 dsp_ndb_ptr->d_debug_ptr = 0x0074; | |
888 dsp_ndb_ptr->d_debug_bk = 0x0001; | |
889 dsp_ndb_ptr->d_pll_config = C_PLL_CONFIG; | |
890 dsp_ndb_ptr->p_debug_buffer = C_DEBUG_BUFFER_ADD; | |
891 dsp_ndb_ptr->d_debug_buffer_size = C_DEBUG_BUFFER_SIZE; | |
892 dsp_ndb_ptr->d_debug_trace_type = C_DEBUG_TRACE_TYPE; | |
893 | |
894 | |
895 #if (CHIPSET == 12) || (CHIPSET == 15) | |
896 dsp_ndb_ptr->d_swh_flag_ndb = 0; /* interpolation off for non SAIC build*/ | |
897 dsp_ndb_ptr->d_swh_Clipping_Threshold_ndb = 0x0000; | |
898 #if (DSP == 36) || (DSP == 37) || (DSP == 39) | |
899 #if (L1_SAIC != 0) | |
900 dsp_ndb_ptr->d_swh_flag_ndb = SAIC_INITIAL_VALUE; | |
901 dsp_ndb_ptr->d_swh_Clipping_Threshold_ndb = 0x4000; | |
902 #endif | |
903 #endif | |
904 #endif | |
905 | |
906 #if (W_A_DSP_IDLE3 == 1) | |
907 // Deep Sleep work around used on Calypso | |
908 // This init is used to backward compatibility with old patch. | |
909 dsp_ndb_ptr->d_dsp_state = C_DSP_IDLE3; | |
910 #endif | |
911 | |
912 dsp_ndb_ptr->d_audio_gain_ul = 0; | |
913 dsp_ndb_ptr->d_audio_gain_dl = 0; | |
914 | |
915 // for patch >= 2100, use new AEC | |
916 #if (!L1_NEW_AEC) | |
917 dsp_ndb_ptr->d_es_level_api = 0x5213; | |
918 #endif | |
919 dsp_ndb_ptr->d_mu_api = 0x5000; | |
920 #else | |
921 #if L1_GPRS | |
922 { | |
923 T_NDB_MCU_DSP_GPRS *p_ndb_gprs = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS; | |
924 | |
925 // Initialize background control variable to No background. | |
926 p_ndb_gprs->d_background_enable = 0; | |
927 p_ndb_gprs->d_background_abort = 0; | |
928 p_ndb_gprs->d_background_state = 0; | |
929 } | |
930 #endif | |
931 | |
932 #if (AMR == 1) | |
933 // Reset NDB pointer for AMR trace | |
934 dsp_ndb_ptr->p_debug_amr = 0; | |
935 #endif | |
936 | |
937 #endif | |
938 | |
939 //-------------------------------------------------------------- | |
940 // Loading of PARAM area....... | |
941 //-------------------------------------------------------------- | |
942 // Load PARAM memory... | |
943 pt = (API *) PARAM_ADR; | |
944 | |
945 for (i=0; i<param_size; i++) *pt++ = param_tab[i]; | |
946 #if (DSP < 33) && (IDS) | |
947 pt += 3; | |
948 for (i= param_size + 3; i<param_size + 3 + param_size2; i++) *pt++ = param_tab[i]; | |
949 #endif | |
950 | |
951 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
952 { | |
953 T_PARAM_MCU_DSP *pt_param = (T_PARAM_MCU_DSP *) PARAM_ADR; | |
954 | |
955 // "d_gprs_install_address" has to be set only if no PATCH is download, i.e. | |
956 // "d_gprs_install_address" is automatically set by DSP if a PATCH is download | |
957 if ((l1_config.dwnld == DSP_DWNLD) || (l1_config.dwnld == NO_DWNLD)) | |
958 pt_param->d_gprs_install_address = INSTALL_ADD; | |
959 } | |
960 #endif | |
961 | |
962 #if L1_GPRS | |
963 //-------------------------------------------------------------- | |
964 // Loading of GPRS PARAM area....... | |
965 //-------------------------------------------------------------- | |
966 // Load GPRS PARAM memory... | |
967 { | |
968 T_PARAM_MCU_DSP_GPRS *pt_gprs = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS; | |
969 | |
970 // WARNING: must be configured according to the ARM & DSP clock speed. | |
971 // The following values are required with a 13MHz ARM clock and with a 65 MIPS DSP. | |
972 pt_gprs->d_overlay_rlcmac_cfg_gprs = 0; | |
973 pt_gprs->d_mac_threshold = 0x4e20; | |
974 pt_gprs->d_sd_threshold = 0x0016; | |
975 pt_gprs->d_nb_max_iteration = 0x0004; | |
976 | |
977 #if (DSP != 33) && (DSP != 34) && (DSP != 35) && (DSP != 36) && (DSP != 37) && (DSP != 38) && (DSP != 39) | |
978 | |
979 #if (OP_L1_STANDALONE) | |
980 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
981 (CHIPSET == 11) || (CHIPSET == 12) | |
982 pt_gprs->d_lat_mcu_bridge = p_dynamic_clock_cfg->d_lat_mcu_bridge; | |
983 pt_gprs->d_lat_mcu_hom2sam = p_dynamic_clock_cfg->d_lat_mcu_hom2sam; | |
984 #endif | |
985 #endif | |
986 | |
987 #if (CHIPSET == 4) | |
988 #if (!OP_L1_STANDALONE) | |
989 // Latency for DSP at 78 MIPS | |
990 pt_gprs->d_lat_mcu_bridge = 0x0009; | |
991 #endif | |
992 pt_gprs->d_lat_pll2div = 0x000C; | |
993 #if (!OP_L1_STANDALONE) | |
994 pt_gprs->d_lat_mcu_hom2sam = 0x000C; | |
995 #endif | |
996 #else | |
997 #if (!OP_L1_STANDALONE) | |
998 pt_gprs->d_lat_mcu_bridge = 0x0008; | |
999 #endif | |
1000 pt_gprs->d_lat_pll2div = 0x000A; | |
1001 #if (!OP_L1_STANDALONE) | |
1002 pt_gprs->d_lat_mcu_hom2sam = 0x000A; | |
1003 #endif | |
1004 #endif | |
1005 | |
1006 // To be removed once G0 patch process will be aligned with G1 & G2 | |
1007 // i.e. "d_gprs_install_address" automatically set by DSP if a Patch is present. | |
1008 #if (DSP == 31) | |
1009 if ((l1_config.dwnld == PATCH_DSP_DWNLD) || | |
1010 (l1_config.dwnld == PATCH_DWNLD)) | |
1011 pt_gprs->d_gprs_install_address = INSTALL_ADD_WITH_PATCH; | |
1012 else | |
1013 pt_gprs->d_gprs_install_address = INSTALL_ADD; | |
1014 #else | |
1015 if ((l1_config.dwnld == DSP_DWNLD) || (l1_config.dwnld == NO_DWNLD)) | |
1016 pt_gprs->d_gprs_install_address = INSTALL_ADD; | |
1017 #endif | |
1018 #endif // DSP != 33 && DSP != 34 && (DSP != 35) && DSP != 36 && DSP != 37 && DSP != 38 | |
1019 } | |
1020 #endif // L1_GPRS | |
1021 | |
1022 *(volatile UWORD16 *) DOWNLOAD_SIZE = 0; // Size=0 to force DSP to start from address... | |
1023 *(volatile UWORD16 *) DOWNLOAD_ADDR = dsp_start_address; // Start address. | |
1024 *(volatile UWORD16 *) DOWNLOAD_STATUS = BLOCK_READY; // Start DSP... | |
1025 | |
1026 } | |
1027 #endif //#if CODE_VERSION!=SIMULATION | |
1028 | |
1029 /*-------------------------------------------------------*/ | |
1030 /* l1s_reset_db_mcu_to_dsp() */ | |
1031 /*-------------------------------------------------------*/ | |
1032 /* Parameters : */ | |
1033 /* Return : */ | |
1034 /* Functionality : */ | |
1035 /*-------------------------------------------------------*/ | |
1036 void l1s_reset_db_mcu_to_dsp(T_DB_MCU_TO_DSP *page_ptr) | |
1037 { | |
1038 API i; | |
1039 API size = sizeof(T_DB_MCU_TO_DSP) / sizeof(API); | |
1040 API *ptr = (API *)page_ptr; | |
1041 | |
1042 // Clear all locations. | |
1043 for(i=0; i<size; i++) *ptr++ = 0; | |
1044 } | |
1045 | |
1046 #if (DSP == 38) || (DSP == 39) | |
1047 /*-------------------------------------------------------*/ | |
1048 /* l1s_reset_db_common_mcu_to_dsp() */ | |
1049 /*-------------------------------------------------------*/ | |
1050 /* Parameters : */ | |
1051 /* Return : */ | |
1052 /* Functionality : */ | |
1053 /*-------------------------------------------------------*/ | |
1054 void l1s_reset_db_common_mcu_to_dsp(T_DB_COMMON_MCU_TO_DSP *page_ptr) | |
1055 { | |
1056 API i; | |
1057 API size = sizeof(T_DB_COMMON_MCU_TO_DSP) / sizeof(API); | |
1058 API *ptr = (API *)page_ptr; | |
1059 | |
1060 // Clear all locations. | |
1061 for(i=0; i<size; i++) *ptr++ = 0; | |
1062 } | |
1063 #endif | |
1064 /*-------------------------------------------------------*/ | |
1065 /* l1s_reset_db_dsp_to_mcu() */ | |
1066 /*-------------------------------------------------------*/ | |
1067 /* Parameters : */ | |
1068 /* Return : */ | |
1069 /* Functionality : */ | |
1070 /*-------------------------------------------------------*/ | |
1071 void l1s_reset_db_dsp_to_mcu(T_DB_DSP_TO_MCU *page_ptr) | |
1072 { | |
1073 API i; | |
1074 API size = sizeof(T_DB_DSP_TO_MCU) / sizeof(API); | |
1075 API *ptr = (API *)page_ptr; | |
1076 | |
1077 // Clear all locations. | |
1078 for(i=0; i<size; i++) *ptr++ = 0; | |
1079 | |
1080 // Set crc result as "SB not found". | |
1081 page_ptr->a_sch[0] = (1<<B_SCH_CRC); // B_SCH_CRC =1, BLUD =0 | |
1082 } | |
1083 | |
1084 /*-------------------------------------------------------*/ | |
1085 /* l1s_increment_time() */ | |
1086 /*-------------------------------------------------------*/ | |
1087 /* Parameters : */ | |
1088 /* Return : */ | |
1089 /* Functionality : */ | |
1090 /*-------------------------------------------------------*/ | |
1091 void l1s_increment_time(T_TIME_INFO *time, UWORD32 fn_offset) | |
1092 { | |
1093 // Increment FN % MAX_FN. | |
1094 //------------------------ | |
1095 IncMod(time->fn, fn_offset, MAX_FN); | |
1096 | |
1097 if(fn_offset == 1) | |
1098 // Frame by frame increment... | |
1099 //---------------------------- | |
1100 { | |
1101 IncMod(time->t2, 1, 26); // increment T2 % 26. | |
1102 IncMod(time->t3, 1, 51); // increment T3 % 51. | |
1103 IncMod(time->fn_mod42432, 1, 42432); // increment FN % 42432. | |
1104 IncMod(time->fn_mod13, 1, 13); // increment FN % 13. | |
1105 IncMod(time->fn_mod13_mod4, 1, 4); // increment (FN % 13) % 4. | |
1106 if(time->fn_mod13 == 0) | |
1107 time->fn_mod13_mod4 = 0; | |
1108 | |
1109 if(time->t3 == 0) | |
1110 // new FN is a multiple of 51. | |
1111 { | |
1112 // Increment TC ((FN/51) % 8). | |
1113 IncMod(time->tc, 1, 8); | |
1114 | |
1115 // New FN is a multiple of 26 and 51 -> increment T1 % 2048 (T1=FN div (26*51)). | |
1116 if(time->t2 == 0) IncMod(time->t1, 1, 2048); | |
1117 } | |
1118 | |
1119 #if (L1_GPRS) | |
1120 IncMod(time->fn_mod52, 1, 52); // increment FN % 52. | |
1121 IncMod(time->fn_mod104, 1, 104); // increment FN % 104. | |
1122 | |
1123 if((time->fn_mod13 == 0) || (time->fn_mod13 == 4) || (time->fn_mod13 == 8)) | |
1124 IncMod(time->block_id, 1, MAX_BLOCK_ID); | |
1125 #endif | |
1126 | |
1127 } | |
1128 | |
1129 else | |
1130 // Jumping on a new serving cell. | |
1131 //------------------------------- | |
1132 { | |
1133 time->t2 = time->fn % 26; // T2 = FN % 26. | |
1134 time->t3 = time->fn % 51; // T3 = FN % 51. | |
1135 time->t1 = time->fn / (26L*51L); // T1 = FN div 26*51 | |
1136 time->tc = (time->fn / 51) % 8; // TC = (FN div 51) % 8 | |
1137 time->fn_mod42432 = time->fn % 42432; // FN%42432. | |
1138 time->fn_mod13 = time->fn % 13; // FN % 13. | |
1139 time->fn_mod13_mod4 = time->fn_mod13 % 4; // FN % 13 % 4. | |
1140 | |
1141 #if (L1_GPRS) | |
1142 time->fn_mod104 = time->fn % 104; // FN % 104. | |
1143 | |
1144 if(time->fn_mod104 >= 52) // FN % 52. | |
1145 time->fn_mod52 = time->fn_mod104 - 52; | |
1146 else | |
1147 time->fn_mod52 = time->fn_mod104; | |
1148 | |
1149 time->block_id = ((3 * (time->fn / 13)) + (time->fn_mod13 / 4)); | |
1150 #endif | |
1151 | |
1152 } | |
1153 | |
1154 // Computes reporting period frame number according to the current FN | |
1155 if(l1a_l1s_com.l1s_en_task[DEDIC] == TASK_ENABLED) | |
1156 { | |
1157 T_CHANNEL_DESCRIPTION *desc_ptr; | |
1158 UWORD8 timeslot_no; | |
1159 UWORD8 subchannel; | |
1160 | |
1161 // Get a meaningfull channel description. | |
1162 //--------------------------------------- | |
1163 // Rem1: this is to avoid a bad setting of "fn_in_report" when synchro is performed | |
1164 // whereas L1 is waiting for starting time and no channel discribed BEFORE STI. | |
1165 // Rem2: "fn_in_report" is computed with "CHAN1" parameters since it is the channel | |
1166 // which carries the SACCH. | |
1167 if(l1a_l1s_com.dedic_set.aset->chan1.desc_ptr->channel_type == INVALID_CHANNEL) | |
1168 desc_ptr = &l1a_l1s_com.dedic_set.aset->chan1.desc; | |
1169 else | |
1170 desc_ptr = l1a_l1s_com.dedic_set.aset->chan1.desc_ptr; | |
1171 | |
1172 timeslot_no = desc_ptr->timeslot_no; | |
1173 subchannel = desc_ptr->subchannel; | |
1174 if(desc_ptr->channel_type == TCH_H) timeslot_no = (2*(timeslot_no/2) + subchannel); | |
1175 | |
1176 | |
1177 // Compute "fn_in_report" according to the channel_type. | |
1178 //------------------------------------------------------ | |
1179 if(desc_ptr->channel_type == SDCCH_4) | |
1180 // FN_REPORT for SDCCH/4 is: fn%102 in [37..36]. | |
1181 { | |
1182 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - 37 + 102) % 102); | |
1183 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - 37 + 102) % 102); | |
1184 } | |
1185 else | |
1186 if(desc_ptr->channel_type == SDCCH_8) | |
1187 // FN_REPORT for SDCCH/4 is: fn%102 in [12..11]. | |
1188 { | |
1189 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - 12 + 102) % 102); | |
1190 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - 12 + 102) % 102); | |
1191 } | |
1192 else | |
1193 // TCH_F or TCH_H... | |
1194 { | |
1195 // 1) (timeslot_no * 13) is computed in order to substract the considered beginning for this | |
1196 // timeslot and then always be in the range 0..103 | |
1197 // 2) 104 is added in order to cope with negative numbers. | |
1198 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - (timeslot_no * 13) + 104) % 104); | |
1199 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - (timeslot_no * 13) + 104) % 104); | |
1200 } | |
1201 } | |
1202 } | |
1203 | |
1204 /*-------------------------------------------------------*/ | |
1205 /* l1s_encode_rxlev() */ | |
1206 /*-------------------------------------------------------*/ | |
1207 /* Parameters : */ | |
1208 /* Return : */ | |
1209 /* Functionality : */ | |
1210 /*-------------------------------------------------------*/ | |
1211 WORD16 l1s_encode_rxlev(UWORD8 inlevel) | |
1212 { | |
1213 WORD16 rxlev; | |
1214 | |
1215 rxlev = (221 - inlevel) / 2; // the result is divided by 2 due to | |
1216 // the IL format is 7.1 and rxlev format is 8.0 | |
1217 | |
1218 return(rxlev); | |
1219 } | |
1220 | |
1221 /*-------------------------------------------------------*/ | |
1222 /* l1s_send_ho_finished() */ | |
1223 /*-------------------------------------------------------*/ | |
1224 /* Parameters : */ | |
1225 /* Return : */ | |
1226 /* Functionality : */ | |
1227 /*-------------------------------------------------------*/ | |
1228 void l1s_send_ho_finished(UWORD8 cause) | |
1229 { | |
1230 xSignalHeaderRec *msg; | |
1231 | |
1232 msg = os_alloc_sig(sizeof(T_MPHC_HANDOVER_FINISHED)); | |
1233 DEBUGMSG(status,NU_ALLOC_ERR) | |
1234 msg->SignalCode = L1C_HANDOVER_FINISHED; | |
1235 ((T_MPHC_HANDOVER_FINISHED *)(msg->SigP))->cause = cause; | |
1236 | |
1237 os_send_sig(msg, L1C1_QUEUE); | |
1238 DEBUGMSG(status,NU_SEND_QUEUE_ERR) | |
1239 } | |
1240 | |
1241 | |
1242 /*-------------------------------------------------------*/ | |
1243 /* l1s_get_versions() */ | |
1244 /*-------------------------------------------------------*/ | |
1245 /* Parameters : */ | |
1246 /* Return : */ | |
1247 /* Functionality : return address of version structur */ | |
1248 /*-------------------------------------------------------*/ | |
1249 T_VERSION *l1s_get_version (void) | |
1250 { | |
1251 //update the fields not initialized by the sw init. | |
1252 | |
1253 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
1254 l1s.version.dsp_code_version = l1s_dsp_com.dsp_ndb_ptr->d_version_number1; | |
1255 l1s.version.dsp_patch_version = l1s_dsp_com.dsp_ndb_ptr->d_version_number2; | |
1256 // Note: if l1s.version.dsp_checksum is not initialized (field set to 0) | |
1257 // use TST_TEST_HW_REQ message to initialize the whole structur. | |
1258 #else | |
1259 l1s.version.dsp_patch_version = l1s_dsp_com.dsp_param_ptr->d_version_number; | |
1260 // Note: if l1s.version.dsp_code_version and l1s.version.dsp_checksum | |
1261 // are not initialized (fields set to 0) | |
1262 // use TST_TEST_HW_REQ message to initialize the whole structur. | |
1263 #endif | |
1264 | |
1265 return (&l1s.version); | |
1266 } | |
1267 | |
1268 /*-------------------------------------------------------*/ | |
1269 /* l1s_reset_dedic_meas() */ | |
1270 /*-------------------------------------------------------*/ | |
1271 /* Parameters : */ | |
1272 /* Return : */ | |
1273 /* Functionality : */ | |
1274 /*-------------------------------------------------------*/ | |
1275 void l1s_reset_dedic_serving_meas(void) | |
1276 { | |
1277 // Reset rxlev related fields | |
1278 l1a_l1s_com.Scell_info.meas.acc = 0; | |
1279 l1a_l1s_com.Scell_info.meas.nbr_meas = 0; | |
1280 l1a_l1s_com.Smeas_dedic.acc_sub = 0; | |
1281 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0; | |
1282 | |
1283 // Reset rxqual related fields | |
1284 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0; | |
1285 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0; | |
1286 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0; | |
1287 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0; | |
1288 | |
1289 | |
1290 #if REL99 | |
1291 #if FF_EMR | |
1292 // Reset EMR variables | |
1293 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0; | |
1294 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0; | |
1295 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0; | |
1296 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0; | |
1297 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0; | |
1298 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0; | |
1299 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0; | |
1300 #endif | |
1301 #endif | |
1302 | |
1303 | |
1304 // Reset dtx frame counter | |
1305 l1a_l1s_com.Smeas_dedic.dtx_used = 0; | |
1306 } | |
1307 | |
1308 /*-------------------------------------------------------*/ | |
1309 /* SwapIQ_dl() */ | |
1310 /*-------------------------------------------------------*/ | |
1311 /* Parameters : */ | |
1312 /* Return : */ | |
1313 /* Functionality : */ | |
1314 /*-------------------------------------------------------*/ | |
1315 UWORD32 l1s_swap_iq_dl(UWORD16 radio_freq, UWORD8 task) | |
1316 { | |
1317 UWORD8 swap_iq; | |
1318 UWORD32 task_tab= 0; //omaps00090550 | |
1319 | |
1320 #if (L1_FF_MULTIBAND == 0) | |
1321 if(((l1_config.std.id == DUAL) || (l1_config.std.id == DUALEXT) || (l1_config.std.id == DUAL_US)) && | |
1322 (radio_freq >= l1_config.std.first_radio_freq_band2)) | |
1323 { | |
1324 swap_iq = l1_config.std.swap_iq_band2; | |
1325 } | |
1326 else | |
1327 { | |
1328 swap_iq = l1_config.std.swap_iq_band1; | |
1329 } | |
1330 #else // L1_FF_MULTIBAND = 1 below | |
1331 | |
1332 UWORD16 physical_band_id; | |
1333 physical_band_id = | |
1334 l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq); | |
1335 swap_iq = rf_band[physical_band_id].swap_iq; | |
1336 | |
1337 #endif // #if (L1_FF_MULTIBAND == 0) else | |
1338 | |
1339 switch(swap_iq) | |
1340 { | |
1341 case 0: /* No swap at all. */ | |
1342 case 2: /* DL, no swap. */ | |
1343 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1344 break; | |
1345 case 1: /* DL I/Q swap. */ | |
1346 case 3: /* DL I/Q swap. */ | |
1347 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1348 task_tab |= 0x8000L; | |
1349 break; | |
1350 } | |
1351 return(task_tab); | |
1352 } | |
1353 | |
1354 /*-------------------------------------------------------*/ | |
1355 /* l1s_swap_iq_ul() */ | |
1356 /*-------------------------------------------------------*/ | |
1357 /* Parameters : */ | |
1358 /* Return : */ | |
1359 /* Functionality : */ | |
1360 /*-------------------------------------------------------*/ | |
1361 UWORD32 l1s_swap_iq_ul(UWORD16 radio_freq, UWORD8 task) | |
1362 { | |
1363 UWORD8 swap_iq; | |
1364 UWORD32 task_tab = 0; //omaps00090550 | |
1365 | |
1366 #if (L1_FF_MULTIBAND == 0) | |
1367 | |
1368 if(((l1_config.std.id == DUAL) || (l1_config.std.id == DUALEXT) || (l1_config.std.id == DUAL_US)) && | |
1369 (radio_freq >= l1_config.std.first_radio_freq_band2)) | |
1370 { | |
1371 swap_iq = l1_config.std.swap_iq_band2; | |
1372 } | |
1373 else | |
1374 { | |
1375 swap_iq = l1_config.std.swap_iq_band1; | |
1376 } | |
1377 #else // L1_FF_MULTIBAND = 1 below | |
1378 | |
1379 UWORD16 physical_band_id = 0; | |
1380 physical_band_id = | |
1381 l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq); | |
1382 swap_iq = rf_band[physical_band_id].swap_iq; | |
1383 | |
1384 #endif // #if (L1_FF_MULTIBAND == 0) else | |
1385 | |
1386 switch(swap_iq) | |
1387 { | |
1388 case 0: /* No swap at all. */ | |
1389 case 1: /* UL, no swap. */ | |
1390 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1391 break; | |
1392 case 2: /* UL I/Q swap. */ | |
1393 case 3: /* UL I/Q swap. */ | |
1394 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1395 task_tab |= 0x8000L; | |
1396 break; | |
1397 } | |
1398 return(task_tab); | |
1399 } | |
1400 | |
1401 | |
1402 /*-------------------------------------------------------*/ | |
1403 /* l1s_ADC_decision_on_NP() */ | |
1404 /*-------------------------------------------------------*/ | |
1405 /* Parameters : */ | |
1406 /* Return : */ | |
1407 /* Functionality : */ | |
1408 /*-------------------------------------------------------*/ | |
1409 UWORD8 l1s_ADC_decision_on_NP(void) | |
1410 { | |
1411 UWORD8 adc_active = INACTIVE; | |
1412 | |
1413 if (l1a_l1s_com.l1s_en_task[ALLC] == TASK_DISABLED) // no reorg mode | |
1414 { | |
1415 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING) // perform ADC only one time | |
1416 { | |
1417 adc_active = ACTIVE; | |
1418 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle | |
1419 } | |
1420 else | |
1421 { | |
1422 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING) // perform ADC on each "period" x bloc | |
1423 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period | |
1424 { | |
1425 adc_active = ACTIVE; | |
1426 l1a_l1s_com.adc_cpt = 0; | |
1427 } | |
1428 } | |
1429 } | |
1430 else // ADC measurement in reorg mode | |
1431 { | |
1432 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING_REORG) // perform ADC only one time | |
1433 { | |
1434 adc_active = ACTIVE; | |
1435 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle | |
1436 } | |
1437 else | |
1438 { | |
1439 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING_REORG) // perform ADC on each "period" x bloc | |
1440 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period | |
1441 { | |
1442 adc_active = ACTIVE; | |
1443 l1a_l1s_com.adc_cpt = 0; | |
1444 } | |
1445 } | |
1446 } | |
1447 return(adc_active); | |
1448 } | |
1449 | |
1450 | |
1451 #if (AMR == 1) | |
1452 /*-------------------------------------------------------*/ | |
1453 /* l1s_amr_get_ratscch_type() */ | |
1454 /*-------------------------------------------------------*/ | |
1455 /* */ | |
1456 /* Description: */ | |
1457 /* ------------ */ | |
1458 /* This function returns the type of a RATSCCH block */ | |
1459 /* Decoding is done according to ETSI spec 05.09 */ | |
1460 /* */ | |
1461 /* Input parameter: */ | |
1462 /* --------------- */ | |
1463 /* "a_ratscch" */ | |
1464 /* pointer to the RATSCCH block */ | |
1465 /* */ | |
1466 /* Output parameter: */ | |
1467 /* ---------------- */ | |
1468 /* Type of RATSCCH block. */ | |
1469 /* Can be: C_RATSCCH_UNKNOWN */ | |
1470 /* C_RATSCCH_CMI_PHASE_REQ */ | |
1471 /* C_RATSCCH_AMR_CONFIG_REQ_MAIN */ | |
1472 /* C_RATSCCH_AMR_CONFIG_REQ_ALT */ | |
1473 /* C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE */ | |
1474 /* C_RATSCCH_THRES_REQ */ | |
1475 /* */ | |
1476 /*-------------------------------------------------------*/ | |
1477 UWORD8 l1s_amr_get_ratscch_type(API *a_ratscch) | |
1478 { | |
1479 // Check if the RATSCCH block is a CMI_PHASE_REQ block | |
1480 // -> if and only if bits 1, 3 through 34 are cleared and bit 2 is set | |
1481 if(((UWORD16)(a_ratscch[3] & 0xFFFE) == 0x0004) && // bits 1, 3-15 are cleared, bit 2 is set | |
1482 ((UWORD16)(a_ratscch[4]) == 0x0000) && // bits 16-31 are cleared | |
1483 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0000)) // bits 32-34 are cleared | |
1484 { | |
1485 return C_RATSCCH_CMI_PHASE_REQ; | |
1486 } | |
1487 | |
1488 // Check if the RATSCCH block is a THRES_REQ block | |
1489 // -> if and only if bits 31 through 34 are cleared and bit 30 is set | |
1490 if(((UWORD16)(a_ratscch[4] & 0xC000) == 0x4000) && // bit 30 is set, bit 31 is cleared | |
1491 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0000)) // bits 32-34 are cleared | |
1492 { | |
1493 return C_RATSCCH_THRES_REQ; | |
1494 } | |
1495 | |
1496 // Check if the RATSCCH block is a AMR_CONFIG_REQ block | |
1497 // -> if and only if bits 33-34 are cleared and bits 30-32 are set | |
1498 if(((UWORD16)(a_ratscch[4] & 0xC000) == 0xC000) && // bits 30-31 are set | |
1499 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0001)) // bit 32 is set, bits 33-34 are cleared | |
1500 { | |
1501 // Check if it's a main AMR_CONFIG_REQ block or an alternative AMR_CONFIG_REQ block | |
1502 UWORD16 ratscch_acs = (a_ratscch[4] & 0x0FF0) >> 4; // get bits 20-27 | |
1503 UWORD8 nb_coders,i; | |
1504 | |
1505 // Count number of active coders | |
1506 for(i=0, nb_coders=0; i<8; i++) | |
1507 { | |
1508 if((ratscch_acs & 1)==1) nb_coders++; | |
1509 ratscch_acs >>= 1; | |
1510 } | |
1511 | |
1512 // If the number of coders is 1, 2 or 3, it is a main AMR_CONFIG_REQ block | |
1513 if(nb_coders<=3) | |
1514 return C_RATSCCH_AMR_CONFIG_REQ_MAIN; | |
1515 | |
1516 // If the number of coders is more than 4, it is an alternate AMR_CONFIG_REQ block | |
1517 // Check if it must be ignored (block THRES_REQ pending) or not | |
1518 // -> if and only if bits 0 through 19 are set | |
1519 if(((UWORD16)(a_ratscch[3]) == 0xFFFF) && // bits 0-15 are set | |
1520 ((UWORD16)(a_ratscch[4] & 0x000F) == 0x000F)) // bits 16-19 are set | |
1521 return C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE; | |
1522 else | |
1523 return C_RATSCCH_AMR_CONFIG_REQ_ALT; | |
1524 } | |
1525 | |
1526 // Block is not recognized | |
1527 return C_RATSCCH_UNKNOWN; | |
1528 } | |
1529 | |
1530 | |
1531 /*--------------------------------------------------------*/ | |
1532 /* l1s_amr_update_from_ratscch() */ | |
1533 /*--------------------------------------------------------*/ | |
1534 /* */ | |
1535 /* Description: */ | |
1536 /* ------------ */ | |
1537 /* This function updates the AMR parameters modified by */ | |
1538 /* the RATSCCH block received. This updates is done both */ | |
1539 /* in the NDB and in the L1A/L1S communication structure */ | |
1540 /* (aset pointer). */ | |
1541 /* Data manipulation is done according to ETSI spec 05.08 */ | |
1542 /* */ | |
1543 /* Input parameter: */ | |
1544 /* --------------- */ | |
1545 /* "a_ratscch_dl" */ | |
1546 /* pointer to the RATSCCH block */ | |
1547 /* */ | |
1548 /* Output parameter: */ | |
1549 /* ---------------- */ | |
1550 /* n/a */ | |
1551 /* */ | |
1552 /*--------------------------------------------------------*/ | |
1553 void l1s_amr_update_from_ratscch(API *a_ratscch_dl) | |
1554 { | |
1555 UWORD16 acs,hysteresis1,hysteresis2,hysteresis3,threshold1,threshold2,threshold3,icm,cmip; | |
1556 UWORD16 amr_change_bitmap=0; | |
1557 UWORD8 ratscch_type; | |
1558 BOOL ratscch_unknown=TRUE; // No AMR parameters update | |
1559 | |
1560 // Get the RATSCCH block's type | |
1561 ratscch_type = l1s_amr_get_ratscch_type(a_ratscch_dl); | |
1562 | |
1563 // Check the RATSCCH block's type | |
1564 switch(ratscch_type) | |
1565 { | |
1566 case C_RATSCCH_CMI_PHASE_REQ: | |
1567 { | |
1568 // Copy CMIP to L1 structure | |
1569 cmip = a_ratscch_dl[3] & 0x0001; // bit 0 | |
1570 l1a_l1s_com.dedic_set.aset->cmip=(UWORD8)cmip; | |
1571 amr_change_bitmap |= 1 << C_AMR_CHANGE_CMIP; | |
1572 // AMR parameters update flag | |
1573 ratscch_unknown=FALSE; | |
1574 } | |
1575 break; | |
1576 case C_RATSCCH_AMR_CONFIG_REQ_MAIN: | |
1577 { | |
1578 // Copy ACS to L1 structure | |
1579 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27 | |
1580 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs; | |
1581 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS; | |
1582 | |
1583 // Copy ICM to L1 structure | |
1584 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29 | |
1585 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm; | |
1586 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM; | |
1587 | |
1588 // Copy hysteresis 1 to L1 structure | |
1589 hysteresis1 = (a_ratscch_dl[3] & 0x03C0) >> 6; // bits 6-9 | |
1590 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]=(UWORD8)hysteresis1; | |
1591 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST1; | |
1592 | |
1593 // Copy threshold 1 to L1 structure | |
1594 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5 | |
1595 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1; | |
1596 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1; | |
1597 | |
1598 // Copy hysteresis 2 to L1 structure | |
1599 hysteresis2 = a_ratscch_dl[4] & 0x000F; // bits 16-19 | |
1600 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]=(UWORD8)hysteresis2; | |
1601 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST2; | |
1602 | |
1603 // Copy threshold 2 to L1 structure | |
1604 threshold2 = (a_ratscch_dl[3] & 0xFC00) >> 10; // bits 10-15 | |
1605 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2; | |
1606 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2; | |
1607 // AMR parameters update flag | |
1608 ratscch_unknown=FALSE; | |
1609 } | |
1610 break; | |
1611 case C_RATSCCH_AMR_CONFIG_REQ_ALT: | |
1612 { | |
1613 // Copy ACS to L1 structure | |
1614 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27 | |
1615 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs; | |
1616 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS; | |
1617 | |
1618 // Copy ICM to L1 structure | |
1619 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29 | |
1620 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm; | |
1621 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM; | |
1622 | |
1623 // Copy threshold 1 to L1 structure | |
1624 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5 | |
1625 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1; | |
1626 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1; | |
1627 | |
1628 // Copy threshold 2 to L1 structure | |
1629 threshold2 = (a_ratscch_dl[3] & 0x0FC0) >> 6; // bits 6-11 | |
1630 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2; | |
1631 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2; | |
1632 | |
1633 // Copy threshold 3 to L1 structure | |
1634 threshold3 = ((a_ratscch_dl[3] & 0xF000) >> 12) | // bits 12-15 | |
1635 ((a_ratscch_dl[4] & 0x0003) << 4); // bits 16-17 | |
1636 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[2]=(UWORD8)threshold3; | |
1637 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR3; | |
1638 | |
1639 // Copy hysteresis 1, 2 and 3 (common hysteresis) to L1 structure | |
1640 hysteresis1 = (a_ratscch_dl[4] & 0x000C) >> 2; // bits 18-19 | |
1641 hysteresis2 = hysteresis3 = hysteresis1; | |
1642 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]= | |
1643 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]= | |
1644 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[2]=(UWORD8)hysteresis1; | |
1645 amr_change_bitmap |= (1 << C_AMR_CHANGE_HYST1) | (1 << C_AMR_CHANGE_HYST2) | (1 << C_AMR_CHANGE_HYST3); | |
1646 // AMR parameters update flag | |
1647 ratscch_unknown=FALSE; | |
1648 } | |
1649 break; | |
1650 case C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE: | |
1651 { | |
1652 // Copy ACS to L1 structure | |
1653 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27 | |
1654 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs; | |
1655 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS; | |
1656 | |
1657 // Copy ICM to L1 structure | |
1658 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29 | |
1659 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm; | |
1660 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM; | |
1661 // AMR parameters update flag | |
1662 ratscch_unknown=FALSE; | |
1663 } | |
1664 break; | |
1665 case C_RATSCCH_THRES_REQ: | |
1666 { | |
1667 // Copy hysteresis 1 to L1 structure | |
1668 hysteresis1 = (a_ratscch_dl[3] & 0x03C0) >> 6; // bits 6-9 | |
1669 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]=(UWORD8)hysteresis1; | |
1670 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST1; | |
1671 | |
1672 // Copy threshold 1 to L1 structure | |
1673 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5 | |
1674 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1; | |
1675 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1; | |
1676 | |
1677 // Copy hysteresis 2 to L1 structure | |
1678 hysteresis2 = a_ratscch_dl[4] & 0x000F; // bits 16-19 | |
1679 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]=(UWORD8)hysteresis2; | |
1680 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST2; | |
1681 | |
1682 // Copy threshold 2 to L1 structure | |
1683 threshold2 = (a_ratscch_dl[3] & 0xFC00) >> 10; // bits 10-15 | |
1684 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2; | |
1685 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2; | |
1686 | |
1687 // Copy hysteresis 3 to L1 structure | |
1688 hysteresis3 = (a_ratscch_dl[4] & 0x3C00) >> 10; // bits 26-29 | |
1689 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[2]=(UWORD8)hysteresis3; | |
1690 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST3; | |
1691 | |
1692 // Copy threshold 3 to L1 structure | |
1693 threshold3 = (a_ratscch_dl[4] & 0x03F0) >> 4; // bits 20-25 | |
1694 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[2]=(UWORD8)threshold3; | |
1695 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR3; | |
1696 // AMR parameters update flag | |
1697 ratscch_unknown=FALSE; | |
1698 } | |
1699 break; | |
1700 case C_RATSCCH_UNKNOWN: | |
1701 { | |
1702 // No AMR parameters update | |
1703 ratscch_unknown=TRUE; | |
1704 } | |
1705 break; | |
1706 } | |
1707 // AMR parameters update only if valid RATSCCH | |
1708 if(ratscch_unknown==FALSE) | |
1709 { | |
1710 // Update NDB with new AMR parameters | |
1711 l1ddsp_load_amr_param(l1a_l1s_com.dedic_set.aset->amr_configuration,l1a_l1s_com.dedic_set.aset->cmip); | |
1712 | |
1713 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) | |
1714 l1_trace_ratscch(l1s.actual_time.fn_mod42432,amr_change_bitmap); | |
1715 #endif | |
1716 } | |
1717 } | |
1718 | |
1719 #endif // AMR | |
1720 | |
1721 | |
1722 | |
1723 /*--------------------------------------------------------*/ | |
1724 /* l1_memcpy_16bit() */ | |
1725 /*--------------------------------------------------------*/ | |
1726 /* */ | |
1727 /* Description: */ | |
1728 /* ------------ */ | |
1729 /* This function is equivalemt of memcopy. Thid function */ | |
1730 /* does only 8/16 bit accessed to both source and */ | |
1731 /* destination */ | |
1732 /* */ | |
1733 /* Input parameter: */ | |
1734 /* --------------- */ | |
1735 /* "src" - input pointer */ | |
1736 /* "len" - number of bytes to copy */ | |
1737 /* */ | |
1738 /* Output parameter: */ | |
1739 /* ---------------- */ | |
1740 /* "dst" - output pointer */ | |
1741 /* */ | |
1742 /*--------------------------------------------------------*/ | |
1743 void l1_memcpy_16bit(void *dst,void* src,unsigned int len) | |
1744 { | |
1745 unsigned int i; | |
1746 unsigned int tempLen; | |
1747 unsigned char *cdst,*csrc; | |
1748 unsigned short *ssrc,*sdst; | |
1749 | |
1750 cdst=dst; | |
1751 csrc=src; | |
1752 sdst=dst; | |
1753 ssrc=src; | |
1754 | |
1755 if(((unsigned int)src&0x01) || ((unsigned int)dst&0x01)){ | |
1756 // if either source or destination is not 16-bit aligned do the entire memcopy | |
1757 // in 8-bit | |
1758 for(i=0;i<len;i++){ | |
1759 *cdst++=*csrc++; | |
1760 } | |
1761 } | |
1762 else{ | |
1763 // if both the source and destination are 16-bit aligned do the memcopy | |
1764 // in 16-bits | |
1765 tempLen = len>>1; | |
1766 for(i=0;i<tempLen;i++){ | |
1767 *sdst++ = *ssrc++; | |
1768 } | |
1769 if(len & 0x1){ | |
1770 // if the caller wanted to copy odd number of bytes do a last 8-bit copy | |
1771 cdst=(unsigned char*)sdst; | |
1772 csrc=(unsigned char*)ssrc; | |
1773 *cdst++ = *csrc++; | |
1774 } | |
1775 } | |
1776 return; | |
1777 } | |
1778 | |
1779 /*-----------------------------------------------------------------*/ | |
1780 /* l1s_restore_synchro */ | |
1781 /*-----------------------------------------------------------------*/ | |
1782 /* Description: */ | |
1783 /* ------------ */ | |
1784 /* This function restores TPU synchro after an actiity */ | |
1785 /* using synchro/synchro back scheme. */ | |
1786 /* */ | |
1787 /* Input parameters: */ | |
1788 /* ----------------- */ | |
1789 /* None */ | |
1790 /* */ | |
1791 /* Input parameters from globals: */ | |
1792 /* ------------------------------ */ | |
1793 /* l1s.tpu_offset */ | |
1794 /* l1s.next_time */ | |
1795 /* l1s.next_plus_time */ | |
1796 /* */ | |
1797 /* Output parameters: */ | |
1798 /* ------------------ */ | |
1799 /* None */ | |
1800 /* */ | |
1801 /* Modified parameters from globals: */ | |
1802 /* --------------------------------- */ | |
1803 /* l1s.actual_time */ | |
1804 /* l1s.next_time */ | |
1805 /* l1s.next_plus_time */ | |
1806 /* l1s.tpu_ctrl_reg */ | |
1807 /* l1s.dsp_ctrl_reg */ | |
1808 /*-----------------------------------------------------------------*/ | |
1809 void l1s_restore_synchro(void) | |
1810 { | |
1811 // Slide synchro back to mach current serving timeslot. | |
1812 l1dmacro_synchro(SWITCH_TIME, l1s.tpu_offset); | |
1813 | |
1814 // Increment frame number. | |
1815 #if L1_GPRS | |
1816 l1s.actual_time = l1s.next_time; | |
1817 l1s.next_time = l1s.next_plus_time; | |
1818 l1s_increment_time(&(l1s.next_plus_time), 1); // Increment "next_plus time". | |
1819 #else | |
1820 l1s.actual_time = l1s.next_time; | |
1821 l1s_increment_time(&(l1s.next_time), 1); // Increment "next time". | |
1822 #endif | |
1823 | |
1824 l1s.tpu_ctrl_reg |= CTRL_SYCB; | |
1825 l1s.dsp_ctrl_reg |= CTRL_SYNC; | |
1826 | |
1827 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) | |
1828 trace_fct(CST_L1S_ADJUST_TIME, (UWORD32)(-1)); | |
1829 #endif | |
1830 } | |
1831 | |
1832 #if (FF_L1_FAST_DECODING == 1) | |
1833 BOOL l1s_check_deferred_control(UWORD8 task, UWORD8 burst_id) | |
1834 { | |
1835 /* Control activities are performed only if: | |
1836 - Fast decoding is not authorized | |
1837 - Fast decoding authorized, control running inside the fast HISR context and not first burst | |
1838 - Fast decoding authorized, control running inside L1S context and first burst */ | |
1839 | |
1840 /* Running from fast API HISR? */ | |
1841 BOOL fast_decoding_hisr = (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_PROCESSING); | |
1842 | |
1843 if (fast_decoding_hisr && (burst_id == BURST_1)) | |
1844 { | |
1845 /* Error this case shouldn't happen */ | |
1846 return TRUE; | |
1847 } | |
1848 else if (!fast_decoding_hisr && (burst_id != BURST_1)) | |
1849 { | |
1850 /* Currently running from L1S, control must be performed on the upcoming fast HISR */ | |
1851 l1a_apihisr_com.fast_decoding.task = task; | |
1852 l1a_apihisr_com.fast_decoding.burst_id = burst_id; | |
1853 /* If a tasks semaphore get SET do not do deferred control */ | |
1854 if(!(l1a_l1s_com.task_param[task] == SEMAPHORE_SET)) | |
1855 { | |
1856 l1a_apihisr_com.fast_decoding.deferred_control_req = TRUE; | |
1857 return TRUE; | |
1858 } | |
1859 } | |
1860 else if (!fast_decoding_hisr && (burst_id == BURST_1)) | |
1861 { | |
1862 /* Control running from L1S for the first burst => Control must be performed now. */ | |
1863 /* As a result, a fast API IT will be triggered on the next frame */ | |
1864 | |
1865 if (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_AWAITED) | |
1866 { | |
1867 /* A fast API IT was already awaited. It means that we are starting the fast decoding */ | |
1868 /* of a new block before the previous one is finished. */ | |
1869 /* This case is signaled through the variable below so the status can stay as awaited */ | |
1870 /* for the first fast API IT of the new block. */ | |
1871 l1a_apihisr_com.fast_decoding.contiguous_decoding = TRUE; | |
1872 } | |
1873 else | |
1874 { | |
1875 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_AWAITED; | |
1876 } | |
1877 l1a_apihisr_com.fast_decoding.task = task; | |
1878 return FALSE; | |
1879 } | |
1880 /* In other cases do control now. */ | |
1881 return FALSE; | |
1882 } /* end function l1s_check_deferred_control */ | |
1883 | |
1884 BOOL l1s_check_fast_decoding_authorized(UWORD8 task) | |
1885 { | |
1886 BOOL result = FALSE; | |
1887 | |
1888 /* Is a fast decoding already in progress (AWAITED or PROCESSING states)? */ | |
1889 /* Is a fast decoding complete but waiting for the read activity (COMPLETE state)? */ | |
1890 /* In that case, it will continue, even if a mode change has occured. */ | |
1891 BOOL already_in_progress = ( (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_AWAITED) | |
1892 || (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_PROCESSING) | |
1893 || (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_COMPLETE) ); | |
1894 | |
1895 /* One variable used later that contains the status of several tasks */ | |
1896 BOOL no_serving_audio_and_neighbour_tasks = ( | |
1897 (l1a_l1s_com.l1s_en_task[EP] == TASK_DISABLED) | |
1898 && (l1a_l1s_com.l1s_en_task[ALLC] == TASK_DISABLED) | |
1899 && (l1a_l1s_com.l1s_en_task[NSYNC] == TASK_DISABLED) | |
1900 && (l1a_l1s_com.l1s_en_task[FBNEW] == TASK_DISABLED) | |
1901 && (l1a_l1s_com.l1s_en_task[SBCONF] == TASK_DISABLED) | |
1902 && (l1a_l1s_com.l1s_en_task[BCCHN] == TASK_DISABLED) | |
1903 && (l1a_l1s_com.l1s_en_task[EBCCHS] == TASK_DISABLED) | |
1904 //&& (l1a_l1s_com.l1s_en_task[NBCCHS] == TASK_DISABLED) | |
1905 && (l1a_l1s_com.l1s_en_task[BCCHN_TOP] == TASK_DISABLED) | |
1906 #if (L1_GPRS) | |
1907 && (l1a_l1s_com.l1s_en_task[PBCCHS] == TASK_DISABLED) | |
1908 && (l1a_l1s_com.l1s_en_task[PEP] == TASK_DISABLED) | |
1909 && (l1a_l1s_com.l1s_en_task[PALLC] == TASK_DISABLED) | |
1910 && (l1a_l1s_com.l1s_en_task[PBCCHN_IDLE] == TASK_DISABLED) | |
1911 #endif /* L1_GPRS */ | |
1912 //&& (l1a_l1s_com.l1s_en_task[SMSCB] == TASK_DISABLED) | |
1913 #if (L1_MP3 == 1) | |
1914 && (l1a_apihisr_com.mp3.running == FALSE) | |
1915 #endif | |
1916 #if (L1_AAC == 1) | |
1917 && (l1a_apihisr_com.aac.running == FALSE) | |
1918 #endif | |
1919 ); | |
1920 | |
1921 /* If fast decoding is already forbidden, do not enable it until the end of the block. */ | |
1922 /* The forbidden status is reset at the first control of the block */ | |
1923 if (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_FORBIDDEN) | |
1924 { | |
1925 return FALSE; | |
1926 } | |
1927 | |
1928 switch(task) | |
1929 { | |
1930 case NP: | |
1931 { | |
1932 /* Enable Fast Paging (NP) except if CCCH reorg*/ | |
1933 if ( ( already_in_progress == TRUE ) | |
1934 || | |
1935 ( (l1a_l1s_com.mode == I_MODE) | |
1936 && (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED) | |
1937 && (no_serving_audio_and_neighbour_tasks == TRUE) ) | |
1938 ) | |
1939 { | |
1940 result = TRUE; | |
1941 } | |
1942 break; | |
1943 } /* case NP */ | |
1944 | |
1945 case NBCCHS: | |
1946 { | |
1947 /* Enable Fast Paging (NP) except if CCCH reorg*/ | |
1948 if ( ( already_in_progress == TRUE ) | |
1949 || | |
1950 ( (l1a_l1s_com.mode == I_MODE) | |
1951 && (l1a_l1s_com.l1s_en_task[NBCCHS] == TASK_ENABLED) | |
1952 && (no_serving_audio_and_neighbour_tasks == TRUE) ) | |
1953 ) | |
1954 { | |
1955 result = TRUE; | |
1956 } | |
1957 break; | |
1958 } /* case NBCCHS */ | |
1959 | |
1960 #if (L1_GPRS) | |
1961 case PNP: | |
1962 { | |
1963 /* Enable Fast Paging (PNP) except if PCCCH reorg*/ | |
1964 if ( ( already_in_progress == TRUE ) | |
1965 || | |
1966 ( (l1a_l1s_com.mode == I_MODE) | |
1967 && (l1a_l1s_com.l1s_en_task[PNP] == TASK_ENABLED) | |
1968 && (no_serving_audio_and_neighbour_tasks == TRUE) | |
1969 ) | |
1970 ) | |
1971 { | |
1972 result = TRUE; | |
1973 } | |
1974 break; | |
1975 } /* case PNP */ | |
1976 #endif /* L1_GPRS*/ | |
1977 | |
1978 } /* switch(task) */ | |
1979 | |
1980 #if (L1_GPRS) | |
1981 if ((result == FALSE) && ((task == NP) || (task == PNP) || (task == NBCCHS))) | |
1982 #else /* NO_GPRS*/ | |
1983 if ((result == FALSE) && ((task == NP) || (task == NBCCHS))) | |
1984 #endif /* L1_GPRS */ | |
1985 { | |
1986 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_FORBIDDEN; | |
1987 } | |
1988 | |
1989 return result; | |
1990 } /* end function l1s_check_fast_decoding_authorized */ | |
1991 | |
1992 #endif /* FF_L1_FAST_DECODING */ | |
1993 /*-----------------------------------------------------------------*/ | |
1994 /* l1s_check_sacch_dl_block */ | |
1995 /*-----------------------------------------------------------------*/ | |
1996 /* Description: */ | |
1997 /* ------------ */ | |
1998 /* Downlink SACCH buffer comparison function for FER Traces */ | |
1999 /* This is called only when there is a successfully decoded */ | |
2000 /* block. The count of no of successfully decoded SACCH blocks */ | |
2001 /* is updated. */ | |
2002 /* */ | |
2003 /* Input parameters: */ | |
2004 /* ----------------- */ | |
2005 /* sacch_dl_block "Downlink SACCH BLOCK" */ | |
2006 /* */ | |
2007 /* Output parameters: */ | |
2008 /* ------------------ */ | |
2009 /* None */ | |
2010 /* */ | |
2011 /*-----------------------------------------------------------------*/ | |
2012 #if ((FF_REPEATED_SACCH) && (TRACE_TYPE ==1 || TRACE_TYPE == 4)) | |
2013 | |
2014 void l1s_check_sacch_dl_block(API *sacch_dl_block) | |
2015 { | |
2016 int i,j,repeat=1; | |
2017 if( trace_info.repeat_sacch.dl_buffer_empty == FALSE ) | |
2018 { | |
2019 for(i=3,j=0;i<15;i++,j++) | |
2020 { | |
2021 if(trace_info.repeat_sacch.dl_buffer[j] != sacch_dl_block[i]) | |
2022 { | |
2023 break; | |
2024 } | |
2025 } | |
2026 if( i != 15 ) | |
2027 { | |
2028 repeat=0; | |
2029 } | |
2030 } | |
2031 else /* if( trace_info.repeat_sacch.dl_buffer_empty == FALSE ) */ | |
2032 { | |
2033 repeat=0; | |
2034 } /* end else empty DL SACCH buffer*/ | |
2035 if(repeat == 0) | |
2036 { | |
2037 trace_info.repeat_sacch.dl_good_norep++; | |
2038 for ( i=3 ; i<15 ; i++ ) | |
2039 { | |
2040 trace_info.repeat_sacch.dl_buffer[i] = sacch_dl_block[i];// info_address[i]; | |
2041 } | |
2042 trace_info.repeat_sacch.dl_buffer_empty = FALSE; | |
2043 } /* end if repeat = 0*/ | |
2044 else | |
2045 { | |
2046 trace_info.repeat_sacch.dl_buffer_empty = TRUE; | |
2047 } /* end else repeat = 1*/ | |
2048 } /* end function void l1s_check_sacch_dl_block */ | |
2049 #endif /* ((FF_REPEATED_SACCH) && (TRACE_TYPE ==1 || TRACE_TYPE == 4)) */ | |
2050 | |
2051 | |
2052 /*-----------------------------------------------------------------*/ | |
2053 /* l1s_store_sacch_buffer */ | |
2054 /*-----------------------------------------------------------------*/ | |
2055 /* Description: */ | |
2056 /* ------------ */ | |
2057 /* Function to store data in case of a retransmission. */ | |
2058 /* */ | |
2059 /* */ | |
2060 /* Input parameters: */ | |
2061 /* ----------------- */ | |
2062 /* sacch_ul_block "SACCH Uplink block to be stored" */ | |
2063 /* repeat_sacch "The buffer tocontain the stored block" */ | |
2064 /* */ | |
2065 /* Output parameters: */ | |
2066 /* ------------------ */ | |
2067 /* None */ | |
2068 /* */ | |
2069 /*-----------------------------------------------------------------*/ | |
2070 | |
2071 #if (FF_REPEATED_SACCH == 1 ) | |
2072 void l1s_store_sacch_buffer(T_REPEAT_SACCH *repeat_sacch, UWORD8 *sacch_ul_block) | |
2073 { | |
2074 int i=0; | |
2075 /* Store the first 11 words after header in the first 22 bytes. */ | |
2076 for(i=0;i<23;i++) | |
2077 { | |
2078 repeat_sacch->buffer[i] = sacch_ul_block[i] ; | |
2079 } | |
2080 repeat_sacch->buffer_empty = FALSE; | |
2081 } | |
2082 #endif /* (FF_REPEATED_SACCH == 1 ) */ | |
2083 | |
2084 | |
2085 /*-----------------------------------------------------------------*/ | |
2086 /* l1s_repeated_facch_check */ | |
2087 /*-----------------------------------------------------------------*/ | |
2088 /* Description: */ | |
2089 /* ------------ */ | |
2090 /* If two successfully decoded blocks (separated by 8 or 9 frames) are */ | |
2091 /* identical then it returns a NULL buffer otherwise a pointer to the last block */ | |
2092 /* data. */ | |
2093 /* */ | |
2094 /* */ | |
2095 /* Input parameters: */ | |
2096 /* ----------------- */ | |
2097 /* "FACCH block to be stored" */ | |
2098 /* */ | |
2099 /* Output parameters: */ | |
2100 /* ------------------ */ | |
2101 /* None */ | |
2102 /* */ | |
2103 /*-----------------------------------------------------------------*/ | |
2104 | |
2105 | |
2106 #if ( FF_REPEATED_DL_FACCH == 1 ) | |
2107 API * l1s_repeated_facch_check(API *info_address) | |
2108 { | |
2109 unsigned int repeat=1; | |
2110 unsigned int i,j; | |
2111 UWORD8 counter_candidate; | |
2112 | |
2113 counter_candidate=l1s.repeated_facch.counter_candidate; | |
2114 if( l1s.repeated_facch.pipeline[counter_candidate].buffer_empty == FALSE ) | |
2115 { | |
2116 for(i=3,j=0;i<15;j++,i++) | |
2117 { | |
2118 if(l1s.repeated_facch.pipeline[counter_candidate].buffer[j] != info_address[i]) | |
2119 { | |
2120 break; | |
2121 } | |
2122 } | |
2123 if( i != 15 ) | |
2124 { | |
2125 repeat=0; | |
2126 } | |
2127 } | |
2128 else | |
2129 { | |
2130 repeat=0; | |
2131 } /* end else buffer empty*/ | |
2132 #if TESTMODE | |
2133 if(l1_config.repeat_facch_dl_enable != REPEATED_FACCHDL_ENABLE) // repeated FACCH mode is disabled | |
2134 { | |
2135 repeat = 0; | |
2136 } | |
2137 #endif | |
2138 if(repeat == 0) | |
2139 { | |
2140 return &info_address[0]; | |
2141 } | |
2142 else | |
2143 { | |
2144 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) | |
2145 trace_info.facch_dl_repetition_block_count++; | |
2146 #endif | |
2147 if (((l1s.actual_time.fn - fn_prev ) == 8) || ((l1s.actual_time.fn - fn_prev ) == 9 )) // added debug | |
2148 return (API)NULL; | |
2149 else | |
2150 return &info_address[0]; | |
2151 } | |
2152 } | |
2153 #endif /* FF_REPEATED_DL_FACCH == 1 */ | |
2154 | |
2155 | |
2156 | |
2157 #if ( FF_REPEATED_DL_FACCH == 1 ) | |
2158 void l1s_store_facch_buffer(T_REPEAT_FACCH *repeated_facch, API *facch_block) | |
2159 { | |
2160 int i; | |
2161 UWORD8 counter_candidate; | |
2162 fn_prev = l1s.actual_time.fn ;// added | |
2163 counter_candidate=repeated_facch->counter_candidate; | |
2164 /* Store the first 12 words after header in the first 23 bytes. */ | |
2165 for(i=0;i<13;i++) | |
2166 { | |
2167 repeated_facch->pipeline[counter_candidate].buffer[i] = facch_block[i] ; | |
2168 } | |
2169 repeated_facch->pipeline[counter_candidate].buffer_empty = FALSE; | |
2170 } | |
2171 #endif /* ( FF_REPEATED_DL_FACCH == 1 ) */ | |
2172 | |
2173 #if(L1_FF_MULTIBAND == 1) | |
2174 | |
2175 #if 0 | |
2176 | |
2177 /*-------------------------------------------------------*/ | |
2178 /* l1_multiband_radio_freq_convert_into_effective_band_id*/ | |
2179 /*-------------------------------------------------------*/ | |
2180 /* Parameters : radio_freq the frequency to convert */ | |
2181 /* */ | |
2182 /* */ | |
2183 /* */ | |
2184 /* Return : the ID of the effectiev band in which */ | |
2185 /* is located radio_freq */ | |
2186 /* Functionality : compare radio_freq with the effective */ | |
2187 /* bands ranges, return efective_band_id */ | |
2188 /* */ | |
2189 /* */ | |
2190 /*-------------------------------------------------------*/ | |
2191 UWORD8 l1_multiband_radio_freq_convert_into_effective_band_id(UWORD16 radio_freq) | |
2192 { | |
2193 UWORD8 effective_band_id = 0; | |
2194 while( effective_band_id < NB_MAX_EFFECTIVE_SUPPORTED_BANDS) | |
2195 { | |
2196 if ((radio_freq >= multiband_conversion_data[effective_band_id].first_radio_freq) | |
2197 && (radio_freq < (multiband_conversion_data[effective_band_id].first_radio_freq + multiband_conversion_data[effective_band_id].nbmax_carrier)) ) | |
2198 | |
2199 { | |
2200 return(effective_band_id); | |
2201 } | |
2202 else | |
2203 { | |
2204 effective_band_id ++; | |
2205 } | |
2206 } | |
2207 if(effective_band_id == NB_MAX_EFFECTIVE_SUPPORTED_BANDS) | |
2208 { | |
2209 l1_multiband_error_handler(radio_freq); | |
2210 } | |
2211 return(effective_band_id); | |
2212 | |
2213 } | |
2214 /*-------------------------------------------------------*/ | |
2215 /* l1_multiband_radio_freq_convert_into_physical_band_id */ | |
2216 /*-------------------------------------------------------*/ | |
2217 /* Parameters : radio_freq the frequency to convert */ | |
2218 /* */ | |
2219 /* */ | |
2220 /* */ | |
2221 /* Return : the ID of the physical_band band in which*/ | |
2222 /* radio_freq is located */ | |
2223 /* Functionality : Identify effective_band_id, the ID of */ | |
2224 /* the effective band in whicb radio_freq is located */ | |
2225 /* then derive physical_band_id from effective_band_id */ | |
2226 /*-------------------------------------------------------*/ | |
2227 | |
2228 UWORD8 l1_multiband_radio_freq_convert_into_physical_band_id(UWORD16 radio_freq) | |
2229 { | |
2230 UWORD8 effective_band_id, physical_band_id; | |
2231 effective_band_id = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq); | |
2232 physical_band_id = multiband_conversion_data[effective_band_id].physical_band_id; | |
2233 return(physical_band_id); | |
2234 } | |
2235 | |
2236 /*-------------------------------------------------------*/ | |
2237 /* l1_multiband_radio_freq_convert_into_operative_radio_freq*/ | |
2238 /*-------------------------------------------------------*/ | |
2239 /* Parameters : radio_freq the frequency to convert */ | |
2240 /* */ | |
2241 /* */ | |
2242 /* */ | |
2243 /* Return : the operative_radio_freq corresponding to radio_freq */ | |
2244 /* Functionality : identify effective_band_id, then */ | |
2245 /* based on the relationships linking the ranges of operative_radio_freq*/ | |
2246 /* and radio_freq , derive operative_radio_freq */ | |
2247 /*-------------------------------------------------------*/ | |
2248 UWORD16 l1_multiband_radio_freq_convert_into_operative_radio_freq(UWORD16 radio_freq) | |
2249 { | |
2250 UWORD8 effective_band_id; | |
2251 UWORD16 operative_radio_freq; | |
2252 effective_band_id = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq); | |
2253 operative_radio_freq = radio_freq - multiband_conversion_data[effective_band_id].first_radio_freq + multiband_conversion_data[effective_band_id].first_operative_radio_freq; | |
2254 return(operative_radio_freq); | |
2255 } | |
2256 /*--------------------------------------------------------*/ | |
2257 /* l1_multiband_map_radio_freq_into_tpu_table */ | |
2258 /*--------------------------------------------------------*/ | |
2259 /* Parameters : */ | |
2260 /* radio_freq the parameter to be converted */ | |
2261 /* */ | |
2262 /* Return : the index in table rf_band or rf_tpu_band */ | |
2263 /* corresponding to radio_freq */ | |
2264 /* Functionality :identify physical_band_id */ | |
2265 /* then derive from physical_band_id, tpu_band_index to be*/ | |
2266 /* returned a physical band having the ID physical_band_id*/ | |
2267 /* is mapped to the table rf_band[physical_band_id ] */ | |
2268 /*--------------------------------------------------------*/ | |
2269 UWORD8 l1_multiband_map_radio_freq_into_tpu_table(UWORD16 radio_freq) | |
2270 { | |
2271 UWORD8 tpu_table_index = 0; | |
2272 UWORD8 physical_band_id = 0; | |
2273 physical_band_id = l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq); | |
2274 /*For Neptune a band having the ID physical_band_id is mapped to multiband_rf_data[physical_band_id], rf_band[physical_band_id]*/ | |
2275 /*Consequently the existence of this API for API is not necessary since it is redundant with l1_multiband_radio_freq_convert_into_physical_band_id*/ | |
2276 tpu_table_index = physical_band_id; | |
2277 return(tpu_table_index); | |
2278 } | |
2279 /*--------------------------------------------------------*/ | |
2280 /* l1_multiband_error_handler */ | |
2281 /*--------------------------------------------------------*/ | |
2282 /* Parameters : */ | |
2283 /* radio_freq the channel number received from the L3 */ | |
2284 /* */ | |
2285 /* Return : */ | |
2286 /* corresponding to radio_freq */ | |
2287 /* Functionality :handling error code of MULTIBAND */ | |
2288 /*--------------------------------------------------------*/ | |
2289 void l1_multiband_error_handler(UWORD16 radio_freq) | |
2290 { | |
2291 L1_MULTIBAND_TRACE_PARAMS(MULTIBAND_ERROR_TRACE_ID, 1); | |
2292 #if (OP_L1_STANDALONE == 1) | |
2293 #if(CODE_VERSION == NOT_SIMULATION) | |
2294 L1BSP_error_handler(); | |
2295 #endif /*if(CODE_VERSION == NOT_SIMULATION)*/ | |
2296 #endif | |
2297 } | |
2298 #endif // if 0 | |
2299 #endif /*if (L1_FF_MULTIBAND == 1)*/ | |
2300 | |
2301 #if (OP_L1_STANDALONE == 1) | |
2302 | |
2303 UWORD8 l1_get_pwr_mngt() | |
2304 { | |
2305 return(l1_config.pwr_mngt); | |
2306 } | |
2307 | |
2308 #endif | |
2309 | |
2310 void l1_multiband_error_handler(UWORD16 radio_freq) | |
2311 { | |
2312 while(1); | |
2313 } | |
2314 | |
2315 |