FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cfile/l1_pwmgr.c @ 126:c0a6b2f9723b

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
l1_pwmgr.c: removed a bunch of dead LoCosto code
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Fri, 13 May 2016 16:48:47 +0000
parents 813c4bb83603
children 633cc67bebbc
comparison
equal deleted inserted replaced
125:813c4bb83603 126:c0a6b2f9723b
155 155
156 #if (CHIPSET == 12) || (CHIPSET == 15) 156 #if (CHIPSET == 12) || (CHIPSET == 15)
157 #include "timer/timer_sec.h" 157 #include "timer/timer_sec.h"
158 #include "inth/sys_inth.h" 158 #include "inth/sys_inth.h"
159 159
160 160 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */
161
162 #if(CHIPSET == 15)
163 #include "l1_pwmgr.h"
164 #if (OP_L1_STANDALONE == 0)
165 #include "lcc/lcc_api.h"
166 #endif
167
168 /* If NAND is enabled */
169 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
170 unsigned int temp_NAND_Reg1;
171 unsigned int temp_NAND_Reg2;
172 unsigned int temp_NAND_Reg3;
173 #endif
174
175
176
177
178
179 #if (OP_L1_STANDALONE == 1)
180
181 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]=
182 {
183 f_peripheral_interface_dummy,
184 f_peripheral_interface_dummy,
185 f_peripheral_interface_dummy,
186 f_peripheral_interface_dummy,
187 f_peripheral_interface_dummy,
188 f_peripheral_interface_dummy,
189 f_peripheral_interface_dummy,
190 f_peripheral_interface_dummy,
191 madc_outen_check, /* MADC_AS_ID = 8 */
192 f_peripheral_interface_dummy,
193 f_peripheral_interface_dummy,
194 f_peripheral_interface_dummy,
195 f_peripheral_interface_dummy,
196 f_peripheral_interface_dummy,
197 f_peripheral_interface_dummy,
198 f_peripheral_interface_dummy,
199 };
200
201 const t_application_interface Application_interface [MAX_APPLICATIONS] =
202 {
203 f_application_interface_dummy,
204 f_application_interface_dummy,
205 f_application_interface_dummy,
206 f_application_interface_dummy,
207 f_application_interface_dummy,
208 f_application_interface_dummy,
209 f_application_interface_dummy,
210 f_application_interface_dummy,
211 f_application_interface_dummy,
212 f_application_interface_dummy,
213 f_application_interface_dummy,
214 f_application_interface_dummy,
215 f_application_interface_dummy,
216 f_application_interface_dummy,
217 f_application_interface_dummy,
218 f_application_interface_dummy,
219 };
220 #else // For integrated Build
221 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]=
222 {
223 uart_pwr_interface,
224 #ifdef RVM_USB_SWE
225 usb_pwr_interface,
226 #else
227 f_peripheral_interface_dummy,
228 #endif
229 usim_pwr_interface,
230 i2c_pwr_interface,
231 lcd_pwr_interface,
232 #ifdef RVM_CAMD_SWE
233 #if (OP_L1_STANDALONE == 0)
234 camera_pwr_interface,
235 #endif
236 #else
237 f_peripheral_interface_dummy,
238 #endif
239 backlight_pwr_interface,
240 f_peripheral_interface_dummy,
241 audio_madc_sleep, /* MADC_AS_ID = 8 */
242 lcc_pwr_interface,
243 f_peripheral_interface_dummy,
244 f_peripheral_interface_dummy,
245 f_peripheral_interface_dummy,
246 f_peripheral_interface_dummy,
247 f_peripheral_interface_dummy,
248 f_peripheral_interface_dummy,
249 };
250
251 const t_application_interface Application_interface [MAX_APPLICATIONS] =
252 {
253 #ifdef BTS
254
255 BTHAL_PM_HandleSleepManagerReq,
256 #else
257 f_application_interface_dummy,
258 #endif
259 f_application_interface_dummy,
260 f_application_interface_dummy,
261 f_application_interface_dummy,
262 f_application_interface_dummy,
263 f_application_interface_dummy,
264 f_application_interface_dummy,
265 f_application_interface_dummy,
266 f_application_interface_dummy,
267 f_application_interface_dummy,
268 f_application_interface_dummy,
269 f_application_interface_dummy,
270 f_application_interface_dummy,
271 f_application_interface_dummy,
272 f_application_interface_dummy,
273 f_application_interface_dummy,
274 };
275
276
277 #endif // (OP_L1_STANDALONE == 1)
278
279 #endif // omaps00090550 #14 -d removal (CHIPSET = 15)
280
281 161
282 #else //(CHIPSET == 12) || (CHIPSET == 15) 162 #else //(CHIPSET == 12) || (CHIPSET == 15)
283 #include "inth/iq.h" 163 #include "inth/iq.h"
284 #include "inth/inth.h" 164 #include "inth/inth.h"
285 #endif 165 #endif
402 LF = LF +l1s.pw_mgr.histo[ind][0]; \ 282 LF = LF +l1s.pw_mgr.histo[ind][0]; \
403 HF = HF +l1s.pw_mgr.histo[ind][1]; \ 283 HF = HF +l1s.pw_mgr.histo[ind][1]; \
404 } 284 }
405 285
406 286
407
408 #if (CODE_VERSION!=SIMULATION) 287 #if (CODE_VERSION!=SIMULATION)
409 T_PWMGR_DEBUG l1_pwmgr_debug; 288 T_PWMGR_DEBUG l1_pwmgr_debug;
410 #endif // NOT SIMULATION 289 #endif // NOT SIMULATION
411 290
412 #if(CHIPSET == 15) 291
413 292 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */
414 /************************************************************/
415 /* Configure EMIF for optimal consumption */
416 /************************************************************/
417
418
419 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en)
420 {
421 UWORD16 Emif_config_Reg;
422 Emif_config_Reg = (pwd_en << EMIF_CONFIG_PWD_POS | pde << EMIF_CONFIG_PDE_POS | Prefetch_mode << EMIF_CONFIG_PREFETCH_POS | flush_prefetch << EMIF_CONFIG_FLUSH_PREFETCH_POS | wp << EMIF_CONFIG_WP_POS);
423 /*p_Emifreg -> EMIF_Config = (Emif_config_Reg & EMIF_CONFIG_REG_MASK );*/
424 EMIF_CONFIG = Emif_config_Reg;
425 } // End of EMIF_SetConfReg
426
427
428
429 #if (OP_L1_STANDALONE == 1) // API for Audio and MADC
430
431
432
433 T_AUDIO_OUTEN_REG audio_outen_pm;
434
435 // L1 Standalone function for Configuring Audio registers.
436 // Argument CLK_MASK checks if Audio path is active
437 // Argument SLEEP_CMD configures Audio registers for optimal consumption
438 // Argument WAKE_CMD reconfigure audio registers after wakeup
439
440 Uint8 madc_outen_check(Uint8 cmd) {
441 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE;
442 /* I2C array */
443 Bsp_Twl3029_I2cTransReqArray i2cTransArray;
444 Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray;
445
446 /* twl3029 I2C reg info struct */
447 BspTwl3029_I2C_RegisterInfo regInfo[8] ;
448 BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo;
449 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit;
450 Uint8 count = 0;//OMAPS90550-new
451
452
453 switch( cmd ) {
454
455 case CLK_MASK:
456 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET,
457 &shadow_pwronstatus);
458 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET));
459
460 if (ston_bit == 1) return DCXO_CLOCK;
461 else return NO_CLOCK;
462 // omaps00090550 break;
463
464 case SLEEP_CMD:
465 /* store the output enable 1 register */
466 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
467 &audio_outen_pm.outen1);
468
469 /* store the output enable 2 register */
470 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
471 &audio_outen_pm.outen2);
472
473 /* store the output enable 3 register */
474 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
475 &audio_outen_pm.outen3);
476
477
478 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
479 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
480 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++);
481 count++;
482
483 /* store the output enable 2 register */
484 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
485 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++);
486 count++;
487
488 /* store the output enable 3 register */
489 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
490 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++);
491 count++;
492
493
494 /* now request to I2C manager to write to Triton registers */
495 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
496 {
497 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
498 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
499 }
500
501 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
502 else return FAILURE;
503
504 // omaps00090550 break;
505
506 case WAKE_CMD:
507 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
508 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
509 audio_outen_pm.outen1,regInfoPtr++);
510 count++;
511
512 /* store the output enable 2 register */
513 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
514 audio_outen_pm.outen2,regInfoPtr++);
515 count++;
516
517 /* store the output enable 3 register */
518 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
519 audio_outen_pm.outen3,regInfoPtr++);
520 count++;
521
522
523
524 /* now request to I2C manager to write to Triton registers */
525 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
526 {
527 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
528 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
529 }
530
531 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
532 else return FAILURE;
533 // omaps00090550 break;
534 }
535 return SUCCESS;//omaps00090550
536 }
537 #else // Integrated build API for Audio and MADC
538
539 // Full PS build function for Configuring Audio registers.
540 // Argument CLK_MASK checks if Audio path is active
541 // Argument SLEEP_CMD configures Audio registers for optimal consumption
542 // Argument WAKE_CMD reconfigure audio registers after wakeup
543
544
545 T_AUDIO_OUTEN_REG audio_outen_pm;
546 BspTwl3029_I2C_RegData audio_ctrl3;
547
548 Uint8 audio_madc_sleep(Uint8 cmd) {
549 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE;
550 /* I2C array */
551 //Bsp_Twl3029_I2cTransReqArray i2cTransArray;
552 //Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray;
553
554 /* twl3029 I2C reg info struct */
555 //BspTwl3029_I2C_RegisterInfo regInfo[8] ;
556 //BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo;
557 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit;
558
559
560 Uint8 count = 0;
561
562
563 switch( cmd ) {
564
565 case CLK_MASK:
566 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET,
567 &shadow_pwronstatus);
568 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET));
569
570 if (ston_bit == 1) return DCXO_CLOCK;
571 else return NO_CLOCK;
572 //omaps00090550 break;
573
574 case SLEEP_CMD:
575 #if 0
576 /* store the output enable 1 register */
577 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
578 &audio_outen_pm.outen1);
579
580 /* store the output enable 2 register */
581 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
582 &audio_outen_pm.outen2);
583
584 /* store the output enable 3 register */
585 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
586 &audio_outen_pm.outen3);
587
588 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
589 &audio_ctrl3);
590
591 if( audio_outen_pm.outen1 )
592 {
593 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
594 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
595 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++);
596 count++;
597 }
598
599 if( audio_outen_pm.outen2 )
600 {
601
602 /* store the output enable 2 register */
603 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
604 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++);
605 count++;
606 }
607
608 if( audio_outen_pm.outen3 )
609 {
610 /* store the output enable 3 register */
611 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
612 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++);
613 count++;
614 }
615
616 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3)
617 is non-zero */
618 if( audio_ctrl3 & 0xf)
619 {
620 /* store the output enable 3 register */
621 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
622 BSP_TWL_3029_MAP_AUDIO_CTRL3_DEFAULT,regInfoPtr++);
623 count++;
624 }
625
626 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET,
627 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCR_OFFSET, regInfoPtr++);
628 count++;
629
630 //Turn off the USB leakage currrent
631
632 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++);
633 // count++;
634
635 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2, BSP_TWL3029_MAP_USB_PSM_EN_TEST_SET_OFFSET,0x80,regInfoPtr++);
636 //count++;
637
638 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x00,regInfoPtr++);
639 // count++;
640
641 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++);
642 //count++;
643
644 // now request to I2C manager to write to Triton registers
645 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked())
646 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
647 {
648 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
649 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
650 }
651
652 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
653 else return FAILURE;
654
655 #endif
656
657 //omaps00090550 break;
658
659 case WAKE_CMD:
660 #if 0
661
662 if( audio_outen_pm.outen1 )
663 {
664 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
665 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
666 audio_outen_pm.outen1,regInfoPtr++);
667 count++;
668 }
669
670 if( audio_outen_pm.outen2 )
671 {
672
673 /* store the output enable 2 register */
674 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
675 audio_outen_pm.outen2,regInfoPtr++);
676 count++;
677 }
678
679 if( audio_outen_pm.outen3 )
680 {
681 /* store the output enable 3 register */
682 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
683 audio_outen_pm.outen3,regInfoPtr++);
684 count++;
685 }
686
687 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3)
688 is non-zero */
689 if( audio_ctrl3 & 0xf)
690 {
691 /* store the output enable 3 register */
692 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
693 audio_ctrl3,regInfoPtr++);
694 count++;
695 }
696
697
698 //wake up mode: Enable MADC
699 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET,
700 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCS_OFFSET, regInfoPtr++);
701
702 count++; //TI_SH added to set the madc on correctly
703
704 //Enable the USB leakage current after wake up
705
706 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++);
707 // count++;
708
709 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x0F,regInfoPtr++);
710 // count++;
711
712 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_PSM_EN_TEST_CLR_OFFSET,0x80,regInfoPtr++);
713 //count++;
714
715 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++);
716 // count++;
717
718 // now request to I2C manager to write to Triton registers
719 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked())
720 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
721 {
722 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
723 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
724 }
725
726 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
727 else return FAILURE;
728 #endif
729 break;
730 }
731 return SUCCESS;
732 }
733 #endif // API for Audio and MADC
734
735
736
737 //Function to check status of Backlight Only Argument 0 is valid
738
739
740 Uint8 backlight_pwr_interface(Uint8 cmd)
741 {
742 BspTwl3029_I2C_RegData regData;
743
744
745 if(cmd == 0)
746 {
747 BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_PAGE0,PWDNSTATUS,&regData);
748 if((regData) & 0x70)
749 {
750 return(DCXO_CLOCK);
751 }
752 else
753 {
754 return(NO_CLOCK);
755 }
756
757 }
758 else
759 {
760 return(SUCCESS);
761 }
762 }
763
764 //Dummy Function for peripheral check to populate Function pointer table for unused APIs
765
766
767 Uint8 f_peripheral_interface_dummy(Uint8 cmd)
768 {
769 if(cmd == 0)
770 {
771 return(NO_CLOCK);
772 }
773 else
774 {
775 return(SUCCESS);
776 }
777
778 }
779
780 //Dummy Function for Application check to populate Function pointer table for unused APIs
781
782 Uint8 f_application_interface_dummy(Uint8 cmd)
783 {
784 if(cmd == 0)
785 {
786 return(PM_INACTIVE);
787 }
788 else
789 {
790 return(SUCCESS);
791 }
792 }
793
794 //Function not used as of now //OMAPS00090550
795 void Update_Sleep_Status( Uint8 ID, Uint8 state)
796 {
797 if(state)
798 {
799 SLEEP_STATE |= (state << ID); //omaps00090550 ! was present before
800 }
801 else
802 {
803 SLEEP_STATE &=((Uint8)~1 <<ID); //omaps00090550
804 }
805 }
806
807 //Function polls the status of the following peripherals to take
808 //Sleep Decision:
809 //UART, USB, I2C, LCD, Camera, Backlight, Audio Stereo path,
810 //Bluetooth and USIM.
811 //All peripherals either cause Deep Sleep or No Sleep.
812 //Only USIM can also cause Big Sleep.
813
814
815
816 UWORD32 Check_Peripheral_App(void)
817 {
818 #if (CODE_VERSION!=SIMULATION)
819 UWORD8 ret_value;
820 /* Check Peripherals */
821 ret_value = Peripheral_interface[UART_ID](CLK_MASK);
822 if(ret_value)
823 {
824 l1_pwmgr_debug.fail_id = UART_ID;
825 l1_pwmgr_debug.fail_ret_val = ret_value;
826 return(DO_NOT_SLEEP);
827 }
828 ret_value = Peripheral_interface[USB_ID](CLK_MASK);
829 if(ret_value)
830 {
831 l1_pwmgr_debug.fail_id = USB_ID;
832 l1_pwmgr_debug.fail_ret_val = ret_value;
833 return(DO_NOT_SLEEP);
834 }
835 ret_value = Peripheral_interface[I2C_ID](CLK_MASK);
836 if(ret_value)
837 {
838 l1_pwmgr_debug.fail_id = I2C_ID;
839 l1_pwmgr_debug.fail_ret_val = ret_value;
840 return(DO_NOT_SLEEP);
841 }
842 ret_value = Peripheral_interface[LCD_ID](CLK_MASK);
843 if(ret_value)
844 {
845 l1_pwmgr_debug.fail_id = LCD_ID;
846 l1_pwmgr_debug.fail_ret_val = ret_value;
847 return(DO_NOT_SLEEP);
848 }
849 ret_value = Peripheral_interface[CAMERA_ID](CLK_MASK);
850 if(ret_value)
851 {
852 l1_pwmgr_debug.fail_id = CAMERA_ID;
853 l1_pwmgr_debug.fail_ret_val = ret_value;
854 return(DO_NOT_SLEEP);
855 }
856 ret_value = Peripheral_interface[BACKLIGHT_ID](CLK_MASK);
857 if(ret_value)
858 {
859 l1_pwmgr_debug.fail_id = BACKLIGHT_ID;
860 l1_pwmgr_debug.fail_ret_val = ret_value;
861 return(DO_NOT_SLEEP);
862 }
863 ret_value = Peripheral_interface[MADC_AS_ID](CLK_MASK);
864 if(ret_value)
865 {
866 l1_pwmgr_debug.fail_id = MADC_AS_ID;
867 l1_pwmgr_debug.fail_ret_val = ret_value;
868 return(DO_NOT_SLEEP);
869 }
870 /* check battery charger */
871 ret_value = Peripheral_interface[BCI_ID](CLK_MASK);
872 if(ret_value)
873 {
874 l1_pwmgr_debug.fail_id = BCI_ID;
875 l1_pwmgr_debug.fail_ret_val = ret_value;
876 return(DO_NOT_SLEEP);
877 }
878
879 /* Check Applications */
880 ret_value = Application_interface[BT_Stack_ID](APP_ACTIVITY);
881 if(ret_value)
882 {
883 // L1_APPLICATION_OFFSET is added to distinguish Application interface
884 l1_pwmgr_debug.fail_id = BT_Stack_ID + (L1_PWMGR_APP_OFFSET);
885 l1_pwmgr_debug.fail_ret_val = ret_value;
886 return(DO_NOT_SLEEP);
887 }
888 ret_value = Peripheral_interface[USIM_ID](CLK_MASK);
889 if(ret_value)
890 {
891 l1_pwmgr_debug.fail_id = USIM_ID;
892 l1_pwmgr_debug.fail_ret_val = ret_value;
893 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SIM;
894 return(FRAME_STOP);
895 }
896 else
897 {
898 return(CLOCK_STOP);
899 }
900 #endif //NOT SIMULATION
901 }
902
903 //This function Configures DBB for optimal Power Consumption
904 //during Deep Sleep
905
906
907
908 void DBB_Configure_DS()
909 {
910 // FDP enabling and disabling of burst configuration in flash not required in Locosto
911 // Hardware Settings as per Power Bench
912
913 // Stop RNG oscillators
914 RNG_CONFIG &= 0xF03F;
915
916
917 /* Set GPIOs 19 to 22 as outputs to avoid floating pins */
918 GPIO1_CNTL_REG &= ~0x0078;
919
920 /* Set PD on VDR and VFSRX for VSP bus to avoid floating pins */
921 CONF_VDR |= 0x0008;
922 CONF_VFSRX |= 0x0008;
923
924 /* Set HASH in auto-idle */
925 SHA_MASK = 0x0001;
926
927 /* Set DES in auto-idle */
928 DES_MASK = 0x0001;
929
930 /* Set RNG in auto-idle */
931 RNG_MASK = 0x0001;
932
933
934 /* uart_in_pull_down(); */
935
936 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
937
938
939 temp_NAND_Reg1 = COMMAND_REG;
940 temp_NAND_Reg2 = CONTROL_REG;
941 temp_NAND_Reg3 = STATUS_IT_REG;
942
943 COMMAND_REG = 0x06;
944 CONTROL_REG = 0x0;
945 STATUS_IT_REG = 0x0;
946
947 #endif
948 // RANGA: All these bit fields should be replaced by macros
949 // Set DPLL in idle mode
950 // Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks
951 /* Set DPLL in idle mode */
952 /* Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks */
953 CLKM_CNTL_CLK_REG &= ~0x0010 ;
954 CLKM_CNTL_CLK_REG |= 0x000F ;
955
956 CNTL_APLL_DIV_CLK &= ~0x0001; /* Disable APLL */
957
958 // Statements below are not required for the current hardware version.
959 // This was done to solve the problem of DCXO taking 10 frames
960 // to wake-up from Deep Sleep in older hardware versions.
961
962 //DCXO_THRESH_L = 0xC040; // Setting DCXO Thresholds
963 //DCXO_THRESH_H = 0x051F; // to solve Deep Sleep problem
964 }
965
966 //This function Restores DBB after wakeup from Deep Sleep
967
968
969 void DBB_Wakeup_DS()
970 {
971 // FDP re-enabling and burst re-configuration are not required if FDP is disabled
972 // during deep-sleep
973
974 CLKM_CNTL_CLK_REG |= 0x0010 ; // Enable CPORT Clock
975
976 CNTL_APLL_DIV_CLK |= 0x0001; // Enable APLL clock
977
978 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
979
980 // Restoring NAND
981 COMMAND_REG = temp_NAND_Reg1;
982 CONTROL_REG = temp_NAND_Reg2;
983 STATUS_IT_REG = temp_NAND_Reg3;
984 // Restoring NAND
985 #endif
986
987
988 }
989
990
991 //This function shuts down APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0
992
993
994 void Disable_APC_BG() //omaps00090550
995 {
996 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK)
997 RHSW_ARM_CNF |= ARM_PERIPH_LOCK;
998 APCCTRL2 &= ~BGEN;
999 return;
1000 }
1001
1002 //This function enables APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0
1003
1004 void Enable_APC_BG() //omaps00090550
1005 {
1006 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK)
1007 RHSW_ARM_CNF |= ARM_PERIPH_LOCK;
1008 APCCTRL2 |= BGEN;
1009 return;
1010 }
1011
1012 #endif //CHIPSET = 15
1013
1014
1015
1016
1017
1018
1019
1020
1021 293
1022 294
1023 // l1ctl_pgm_clk32() 295 // l1ctl_pgm_clk32()
1024 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN. 296 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN.
1025 297
1294 #endif // End Trace gauging 566 #endif // End Trace gauging
1295 } 567 }
1296 } 568 }
1297 569
1298 570
1299
1300
1301 /* GAUGING_Handler() */ 571 /* GAUGING_Handler() */
1302 /* Description: update increment counter for 32Khz */ 572 /* Description: update increment counter for 32Khz */
1303 /* This interrupt function computes the ratio between */ 573 /* This interrupt function computes the ratio between */
1304 /* HF/32Khz gauging counters and program ULPD increment */ 574 /* HF/32Khz gauging counters and program ULPD increment */
1305 /* values. */ 575 /* values. */
1336 l1s.pw_mgr.gauging_task = INACTIVE; 606 l1s.pw_mgr.gauging_task = INACTIVE;
1337 607
1338 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE); 608 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE);
1339 #endif 609 #endif
1340 } 610 }
1341
1342
1343 611
1344 612
1345 // l1s_get_HWTimers_ticks() 613 // l1s_get_HWTimers_ticks()
1346 // Description: 614 // Description:
1347 // evaluate the loading of the HW Timers for dep sleep 615 // evaluate the loading of the HW Timers for dep sleep
2775 WORD32 timer_sec; 2043 WORD32 timer_sec;
2776 #endif 2044 #endif
2777 UWORD16 cntlreg; 2045 UWORD16 cntlreg;
2778 UWORD16 modereg; 2046 UWORD16 modereg;
2779 double duration; 2047 double duration;
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790 2048
2791 2049
2792 //WORD32 old;- OMAPS 90550 new 2050 //WORD32 old;- OMAPS 90550 new
2793 2051
2794 // read Hercules Timers & Watchdog 2052 // read Hercules Timers & Watchdog
3170 } 2428 }
3171 } 2429 }
3172 2430
3173 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END 2431 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
3174 #endif 2432 #endif
3175
3176
3177