FreeCalypso > hg > tcs211-l1-reconst

comparison chipsetsw/layer1/cfile/l1_cmplx.c @ 57:ef8ab5a0fe8f

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l1_cmplx.c: low-hanging fruit
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sun, 27 Mar 2016 06:37:24 +0000
parents b7046f3475b6
children fcdbd97411c4
comparison
equal deleted inserted replaced
56:b7046f3475b6 57:ef8ab5a0fe8f
2311 } 2311 }
2312 2312
2313 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled 2313 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
2314 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise 2314 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise
2315 2315
2316 #if 0 /* FreeCalypso TCS211 reconstruction */
2316 UWORD32 qual_acc_idle1[2]; 2317 UWORD32 qual_acc_idle1[2];
2318 #endif
2317 2319
2318 /*-------------------------------------------------------*/ 2320 /*-------------------------------------------------------*/
2319 /* l1s_ctrl_snb_dl() */ 2321 /* l1s_ctrl_snb_dl() */
2320 /*-------------------------------------------------------*/ 2322 /*-------------------------------------------------------*/
2321 /* */ 2323 /* */
7541 if (task == NP) 7543 if (task == NP)
7542 { 7544 {
7543 toa_tab[burst_id] = toa; 7545 toa_tab[burst_id] = toa;
7544 } 7546 }
7545 7547
7548 #if 0 /* FreeCalypso TCS211 reconstruction */
7546 // added Enhanced RSSI 7549 // added Enhanced RSSI
7547 if(l1s_dsp_com.dsp_ndb_ptr->a_cd[2] != 0xffff) 7550 if(l1s_dsp_com.dsp_ndb_ptr->a_cd[2] != 0xffff)
7548 { 7551 {
7549 qual_acc_idle1[0] += l1s_dsp_com.dsp_ndb_ptr->a_cd[2]; 7552 qual_acc_idle1[0] += l1s_dsp_com.dsp_ndb_ptr->a_cd[2];
7550 //RX Qual value reporting- total number of decoded bits 7553 //RX Qual value reporting- total number of decoded bits
7551 qual_acc_idle1[1] += 1; 7554 qual_acc_idle1[1] += 1;
7552 } 7555 }
7556 #endif
7553 7557
7554 #if (FF_L1_FAST_DECODING == 1) 7558 #if (FF_L1_FAST_DECODING == 1)
7555 /* Perform the reporting if 7559 /* Perform the reporting if
7556 - Burst is the 4th one (whether CRC is ok or not) 7560 - Burst is the 4th one (whether CRC is ok or not)
7557 - Fast decoding enabled and CRC already ok 7561 - Fast decoding enabled and CRC already ok
11969 #endif 11973 #endif
11970 #endif 11974 #endif
11971 11975
11972 } 11976 }
11973 11977
11978 #if (CHIPSET==15)
11974 /*-------------------------------------------------------*/ 11979 /*-------------------------------------------------------*/
11975 /* l1s_reset_tx_ptr() */ 11980 /* l1s_reset_tx_ptr() */
11976 /*-------------------------------------------------------*/ 11981 /*-------------------------------------------------------*/
11977 /* Parameters : */ 11982 /* Parameters : */
11978 /* Return : */ 11983 /* Return : */
11983 #define L1_DRP_TX_PTR_RESET_SET (0x00000020) 11988 #define L1_DRP_TX_PTR_RESET_SET (0x00000020)
11984 #define L1_DRP_TX_PTR_RESET_RESET (~(L1_DRP_TX_PTR_RESET_SET)) 11989 #define L1_DRP_TX_PTR_RESET_RESET (~(L1_DRP_TX_PTR_RESET_SET))
11985 11990
11986 void l1s_reset_tx_ptr(UWORD8 param1, UWORD8 param2) 11991 void l1s_reset_tx_ptr(UWORD8 param1, UWORD8 param2)
11987 { 11992 {
11988 #if (CHIPSET==15)
11989 volatile UWORD32 *ptr_drp_init32; 11993 volatile UWORD32 *ptr_drp_init32;
11990 ptr_drp_init32 = (UWORD32 *) (DRP_API_BASE_ADDRESS + DRP_REG_SRM_CW_ADDR); //0xFFFF1E00; 11994 ptr_drp_init32 = (UWORD32 *) (DRP_API_BASE_ADDRESS + DRP_REG_SRM_CW_ADDR); //0xFFFF1E00;
11991 11995
11992 // Set the TX_PTR_RESET bit to 1 to reset TX RD and WR pointers 11996 // Set the TX_PTR_RESET bit to 1 to reset TX RD and WR pointers
11993 (*ptr_drp_init32) = (*ptr_drp_init32)|(L1_DRP_TX_PTR_RESET_SET); 11997 (*ptr_drp_init32) = (*ptr_drp_init32)|(L1_DRP_TX_PTR_RESET_SET);
11994 11998
11995 // Reset the bit to zero as aslong as the bit is 1, pointers are in reset state 11999 // Reset the bit to zero as aslong as the bit is 1, pointers are in reset state
11996 (*ptr_drp_init32) = (*ptr_drp_init32)&(L1_DRP_TX_PTR_RESET_RESET); 12000 (*ptr_drp_init32) = (*ptr_drp_init32)&(L1_DRP_TX_PTR_RESET_RESET);
11997 #endif
11998 } 12001 }
11999 12002 #endif