comparison chipsetsw/layer1/tm_cfile/l1tm_func.c @ 223:f3a01488b437

l1tm_func.c: initial import from LoCosto source
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 14 Jan 2017 22:32:40 +0000
parents 6814a6bced4f
children a576fb23046e
comparison
equal deleted inserted replaced
222:a4899cf67fd1 223:f3a01488b437
1 /* dummy C source file */ 1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1TM_FUNC.C
4 *
5 * Filename l1tm_func.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #include "l1_macro.h"
11 #include "l1_confg.h"
12
13 #if TESTMODE
14 #define L1TM_FUNC_C
15
16 #include <string.h>
17 #include <math.h>
18 #include "abb.h"
19
20 #include "general.h"
21
22 #include "l1_types.h"
23 #include "sys_types.h"
24 #include "l1_const.h"
25 #include "l1_time.h"
26 #include "l1_signa.h"
27
28 #include "l1tm_defty.h"
29
30 #if (CODE_VERSION != SIMULATION)
31 #include "pld.h"
32 #endif
33
34
35 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) || (TRACE_TYPE==7) || (TRACE_TYPE==0)
36 #include "rvt_gen.h"
37 extern T_RVT_USER_ID tm_trace_user_id;
38 #endif
39
40 #if (AUDIO_TASK == 1)
41 #include "l1audio_const.h"
42 #include "l1audio_cust.h"
43 #include "l1audio_defty.h"
44 #endif
45
46 #if (L1_GTT == 1)
47 #include "l1gtt_const.h"
48 #include "l1gtt_defty.h"
49 #endif
50
51 #if (L1_MP3 == 1)
52 #include "l1mp3_defty.h"
53 #endif
54
55 #if (L1_MIDI == 1)
56 #include "l1midi_defty.h"
57 #endif
58
59 #include "l1_defty.h"
60 #include "cust_os.h"
61 #include "l1_msgty.h"
62 #include "l1_varex.h"
63 #include "l1_proto.h"
64
65 #include "mem.h"
66
67 #if (CODE_VERSION != SIMULATION)
68
69 #if (RF_FAM == 61)
70 #include "tpudrv61.h"
71 #include "l1_rf61.h"
72 #include "l1tm_tpu61.h"
73 #if (DRP_FW_EXT==1)
74 #include "l1_drp_inc.h"
75 #else
76 #include "drp_drive.h"
77 #endif
78 #endif
79
80 #if (RF_FAM == 60)
81 #include "tpudrv60.h"
82 #include "l1_rf60.h"
83 #include "l1tm_tpu60.h"
84 #include "drp_drive.h"
85 #endif
86
87 #if (RF_FAM==43)
88 #include "tpudrv43.h"
89 #include "l1_rf43.h"
90 #include "l1tm_tpu43.h"
91 #endif
92 #if (RF_FAM == 35)
93 #include "tpudrv35.h"
94 #include "l1_rf35.h"
95 #include "l1tm_tpu35.h"
96 #endif
97
98 #if (RF_FAM == 12)
99 #include "tpudrv12.h"
100 #include "l1_rf12.h"
101 #include "l1tm_tpu12.h"
102 #endif
103
104 #if (RF_FAM == 10)
105 #include "tpudrv10.h"
106 #include "l1_rf10.h"
107 #include "l1tm_tpu10.h"
108 #endif
109
110 #if (RF_FAM == 8)
111 #include "tpudrv8.h"
112 #include "l1_rf8.h"
113 #include "l1tm_tpu8.h"
114 #endif
115
116 #if (RF_FAM == 2)
117 #include "tpudrv2.h"
118 #include "l1_rf2.h"
119 #include "l1tm_tpu2.h"
120 #endif
121
122 #else
123
124 #if (RF_FAM == 2)
125 #include "l1_rf2.h"
126 #endif
127
128 #endif
129
130 #include <assert.h>
131 #include <string.h>
132
133 #include "l1tm_msgty.h"
134 #include "l1tm_signa.h"
135 #include "l1tm_varex.h"
136 #include "l1tm_ver.h"
137
138 #if L1_GPRS
139 #include "l1p_cons.h"
140 #include "l1p_msgt.h"
141 #include "l1p_deft.h"
142 #include "l1p_vare.h"
143 #include "l1p_sign.h"
144 #endif
145
146 #if ((L1_STEREOPATH == 1) && (OP_L1_STANDALONE == 1))
147 #include "sys_dma.h"
148 #endif
149
150 #if(L1_FF_MULTIBAND == 1)
151 extern UWORD8 tm_band;
152 #endif /*if (L1_FF_MULTIBAND == 1)*/
153
154
155 #if (DRP_FW_EXT==0)
156 #if (L1_DRP == 1)
157 #include "drp_drive.h"
158 #include "drp_defines.h"
159 #include "drp_api.h"
160 #include "drp_extern_dependencies.h"
161 #endif //L1_DRP
162
163 #if (RF_FAM == 61)
164 extern T_DRP_SW_DATA drp_sw_data_init;
165 extern T_DRP_SW_DATA drp_sw_data_calib;
166 extern T_DRP_SW_DATA drp_sw_data_calib_saved;
167 extern UINT16 g_pcb_config; //ompas00090550 #262 removal
168 #endif // DRP_FW_EXT==0
169 #endif
170
171 extern void gpio_39_toggle(UINT16 state);
172
173
174 // Prototypes from external functions
175 //------------------------------------
176 UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq);
177
178 void Cust_tm_rf_param_write (T_TM_RETURN *tm_return, WORD16 index, UWORD16 value);
179 void Cust_tm_rf_param_read (T_TM_RETURN *tm_return, WORD16 index);
180 void Cust_tm_rf_table_write (T_TM_RETURN *tm_return, WORD8 index, UWORD8 size, UWORD8 table[]);
181 void Cust_tm_rf_table_read (T_TM_RETURN *tm_return, WORD8 index);
182 void Cust_tm_rx_param_write (T_TM_RETURN *tm_return, WORD16 index, UWORD16 value);
183 void Cust_tm_rx_param_read (T_TM_RETURN *tm_return, WORD16 index);
184 void Cust_tm_tx_param_write (T_TM_RETURN *tm_return, WORD16 index, UWORD16 value, UWORD8 band);
185 void Cust_tm_tx_param_read (T_TM_RETURN *tm_return, WORD16 index, UWORD8 band);
186 void Cust_tm_tx_template_write (T_TM_RETURN *tm_return, WORD8 index, UWORD8 size, UWORD8 table[]);
187 void Cust_tm_tx_template_read (T_TM_RETURN *tm_return, WORD8 index);
188 void Cust_tm_special_param_write (T_TM_RETURN *tm_return, WORD16 index, UWORD16 value);
189 void Cust_tm_special_param_read (T_TM_RETURN *tm_return, WORD16 index);
190 void Cust_tm_special_table_write (T_TM_RETURN *tm_return, WORD8 index, UWORD8 size, UWORD8 table[]);
191 void Cust_tm_special_table_read (T_TM_RETURN *tm_return, WORD8 index);
192 void Cust_tm_special_enable (T_TM_RETURN *tm_return, WORD16 action);
193
194 #if (CODE_VERSION != SIMULATION)
195 void Cust_tm_tpu_table_write (T_TM_RETURN *tm_return, WORD8 index, UWORD8 size, UWORD8 table[]);
196 void Cust_tm_tpu_table_read (T_TM_RETURN *tm_return, WORD8 index);
197 #endif
198
199 #if (L1_TPU_DEV == 1)
200 void Cust_tm_flexi_tpu_table_write(T_TM_RETURN * tm_return, WORD8 index, UWORD8 size, WORD16 table[ ]);
201 void Cust_tm_flexi_tpu_table_read(T_TM_RETURN * tm_return, WORD8 index);
202
203 //Flexi ABB Delays
204 void Cust_tm_flexi_abb_write(T_TM_RETURN * tm_return, WORD8 index, UWORD8 size, WORD16 table[ ]);
205 void Cust_tm_flexi_abb_read(T_TM_RETURN * tm_return, WORD8 index);
206
207 #endif
208
209 // DRP Calibration
210 void l1tm_drp_calib_read(T_TESTMODE_PRIM * prim, T_TM_RETURN * tm_return);
211 void l1tm_drp_calib_write(T_TESTMODE_PRIM * prim, T_TM_RETURN * tm_return);
212
213 //------------------------------------
214 // Prototypes from external functions
215 //------------------------------------
216
217 void Cust_tm_init (void);
218 void l1tm_reset_rx_state (void);
219 void l1tm_reset_rx_stats (void);
220
221 #if L1_GPRS
222 void l1pa_reset_cr_freq_list (void);
223 #endif
224
225 //------------------------------------
226 // Prototypes from internal functions
227 //------------------------------------
228
229 void l1tm_initialize_var(void);
230 UWORD16 l1tm_convert_arfcn2l1ch(UWORD16 arfcn, UWORD8 *error_flag);
231 void l1tm_stats_read(T_TM_RETURN *tm_return, WORD16 type, UWORD16 bitmask);
232 void tm_transmit(T_TM_RETURN *tm_ret);
233 void l1tm_PRBS1_generate(UWORD16 *TM_ul_data);
234
235 #if ((L1_STEREOPATH == 1) && (OP_L1_STANDALONE == 1))
236 void l1tm_stereopath_DMA_handler(SYS_UWORD16 dma_status);
237 void l1tm_stereopath_fill_buffer(void* buffer_address);
238 UWORD16 l1tm_stereopath_get_pattern(UWORD16 sampling_freq, UWORD16 sin_freq_left,UWORD16 sin_freq_right, UWORD8 data_type);
239 #endif
240
241 /***********************************************************************/
242 /* TESTMODE 3.X */
243 /***********************************************************************/
244
245 static UWORD8 tx_param_band=0; // used in tx_param_write/read; default is GSM900
246
247
248
249
250 // RF,(ANALOG)or other hardware dependent functions
251 // - work done by tmrf.c functions for each product.
252
253 // TestMode functions that modify the state variables
254 // within the L1A - may need to allocate space
255 // dynamically if this is the first time calling
256 // these functions.
257
258 // TestMode functions that start L1A state machines
259 // may need to send L1A primitives to change L1A state.
260
261 void l1tm_rf_param_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
262 {
263 tm_return->index = prim->u.tm_params.index;
264 tm_return->size = 0;
265
266 switch (prim->u.tm_params.index)
267 {
268 #if (FF_REPEATED_SACCH == 1)
269 // Repeated SACCH mode
270 case REPEATED_SACCH_ENA_FLAG:
271 {
272 l1_config.repeat_sacch_enable = prim->u.tm_params.value;
273 #if (ETM_PROTOCOL == 1)
274 tm_return->status = -ETM_OK;
275 #else
276 tm_return->status = E_OK;
277 #endif
278 break;
279 }
280 #endif /* FF_REPEATED_SACCH */
281
282 #if (FF_REPEATED_DL_FACCH == 1)
283 // Repeated FACCH mode
284 case REPEATED_FACCHDL_ENA_FLAG:
285 {
286 l1_config.repeat_facch_dl_enable = prim->u.tm_params.value;
287 #if (ETM_PROTOCOL == 1)
288 tm_return->status = -ETM_OK;
289 #else
290 tm_return->status = E_OK;
291 #endif/*(ETM_PROTOCOL == 1)*/
292
293 break;
294 }
295 #endif /* FF_REPEATED_DL_FACCH == 1 */
296 case BCCH_ARFCN:
297 {
298 UWORD16 bcch_arfcn;
299 UWORD8 error_flag;
300
301 bcch_arfcn = l1tm_convert_arfcn2l1ch(prim->u.tm_params.value, &error_flag);
302
303 if (error_flag)
304 {
305 #if (ETM_PROTOCOL == 1)
306 tm_return->status = -ETM_INVAL;
307 #else
308 tm_return->status = E_INVAL;
309 #endif
310 }
311 else
312 {
313 l1_config.tmode.rf_params.bcch_arfcn = bcch_arfcn;
314
315 // now change on the fly
316 // no reason to check dedicated_active flag...
317 // we just set these 2 globals for FB/SB/BCCH tests
318 l1a_l1s_com.nsync.list[0].radio_freq = l1_config.tmode.rf_params.bcch_arfcn;
319 l1a_l1s_com.Scell_info.radio_freq = l1_config.tmode.rf_params.bcch_arfcn;
320 #if (ETM_PROTOCOL == 1)
321 tm_return->status = -ETM_OK;
322 #else
323 tm_return->status = E_OK;
324 #endif
325 }
326 break;
327 }
328 case TCH_ARFCN:
329 {
330 T_CHN_SEL *chan_sel;
331 UWORD16 tch_arfcn;
332 UWORD8 error_flag;
333
334 tch_arfcn = l1tm_convert_arfcn2l1ch(prim->u.tm_params.value, &error_flag);
335
336 if (error_flag)
337 #if (ETM_PROTOCOL == 1)
338 tm_return->status = -ETM_INVAL;
339 #else
340 tm_return->status = E_INVAL;
341 #endif
342 else
343 {
344 l1_config.tmode.rf_params.tch_arfcn = tch_arfcn;
345
346 // now change on the fly if necessary
347 if (l1_config.TestMode && l1tm.tmode_state.dedicated_active)
348 {
349 chan_sel = &(l1a_l1s_com.dedic_set.aset->achan_ptr->desc_ptr->chan_sel);
350 chan_sel->rf_channel.single_rf.radio_freq = l1_config.tmode.rf_params.tch_arfcn;
351 }
352 #if (ETM_PROTOCOL == 1)
353 tm_return->status = -ETM_OK;
354 #else
355 tm_return->status = E_OK;
356 #endif
357 }
358 break;
359 }
360 case MON_ARFCN:
361 {
362 UWORD16 mon_arfcn;
363 UWORD8 error_flag;
364
365 mon_arfcn = l1tm_convert_arfcn2l1ch(prim->u.tm_params.value, &error_flag);
366
367 if (error_flag)
368 #if (ETM_PROTOCOL == 1)
369 tm_return->status = -ETM_INVAL;
370 #else
371 tm_return->status = E_INVAL;
372 #endif
373 else
374 {
375 l1_config.tmode.rf_params.mon_arfcn = mon_arfcn;
376 #if (ETM_PROTOCOL == 1)
377 tm_return->status = -ETM_OK;
378 #else
379 tm_return->status = E_OK;
380 #endif
381 }
382 break;
383 }
384 #if L1_GPRS
385 case PDTCH_ARFCN:
386 {
387 UWORD16 pdtch_arfcn;
388 UWORD8 error_flag;
389
390 pdtch_arfcn = l1tm_convert_arfcn2l1ch(prim->u.tm_params.value, &error_flag);
391
392 if (error_flag)
393 #if (ETM_PROTOCOL == 1)
394 tm_return->status = -ETM_INVAL;
395 #else
396 tm_return->status = E_INVAL;
397 #endif
398 else
399 {
400 l1_config.tmode.rf_params.pdtch_arfcn = pdtch_arfcn;
401 #if (ETM_PROTOCOL == 1)
402 tm_return->status = -ETM_OK;
403 #else
404 tm_return->status = E_OK;
405 #endif
406 }
407 break;
408 }
409 #endif
410 case AFC_ENA_FLAG:
411 {
412 l1_config.afc_enable = prim->u.tm_params.value;
413 #if (ETM_PROTOCOL == 1)
414 tm_return->status = -ETM_OK;
415 #else
416 tm_return->status = E_OK;
417 #endif
418 break;
419 }
420 case AFC_DAC_VALUE:
421 {
422 WORD16 afc_value = prim->u.tm_params.value;
423 // 13-bit AFC DAC
424 #if(RF_FAM != 61)
425 if (afc_value<-4096 || afc_value>4095)
426 #else
427 if (afc_value<-8192 || afc_value>8191)
428 #endif
429 {
430 #if (ETM_PROTOCOL == 1)
431 tm_return->status = -ETM_INVAL;
432 #else
433 tm_return->status = E_INVAL;
434 #endif
435 break;
436 }
437
438 if (!l1_config.afc_enable)
439 {
440 // write AFC value to AFC DAC ASAP!! AFC DAC will be updated by any RX
441 // or TX test.
442 l1s.afc = afc_value;
443 }
444
445 #if (ETM_PROTOCOL == 1)
446 tm_return->status = -ETM_OK;
447 #else
448 tm_return->status = E_OK;
449 #endif
450 break;
451 }
452 #if L1_GPRS
453 case MULTISLOT_CLASS:
454 {
455 UWORD8 multislot_class;
456
457 multislot_class = prim->u.tm_params.value;
458
459 if ((multislot_class < 1) || (multislot_class > 12))
460 #if (ETM_PROTOCOL == 1)
461 tm_return->status = -ETM_INVAL;
462 #else
463 tm_return->status = E_INVAL;
464 #endif
465 else
466 {
467 l1_config.tmode.rf_params.multislot_class = multislot_class;
468 #if (ETM_PROTOCOL == 1)
469 tm_return->status = -ETM_OK;
470 #else
471 tm_return->status = E_OK;
472 #endif
473 }
474 break;
475 }
476 #endif // end of L1_GPRS
477 default:
478 {
479 Cust_tm_rf_param_write(tm_return,
480 prim->u.tm_params.index,
481 prim->u.tm_params.value);
482 break;
483 }
484 } // end switch
485 }
486
487 UWORD16 l1tm_convert_arfcn2l1ch(UWORD16 arfcn, UWORD8 *error_flag)
488 #if (L1_FF_MULTIBAND == 0)
489 {
490 /* Here, before we store the channel numbers to the l1_config structure,
491 we convert from ETSI to TI channel numbering system. The GGT
492 ALWAYS expects the ETSI numbering system as input and output.
493
494 We need to do the OPPOSITE of what is done in convert_l1_arfcn() in
495 tpudrvX.c
496
497 ***************************************
498 *** convert arfcn's from ETSI to TI ***
499 ***************************************
500 ** **
501 ** ETSI TI **
502 ** 0 GSM 174 **
503 ** 1 - 124 GSM 1 - 124 **
504 ** 975 - 1023 E-GSM 125 - 173 **
505 ** 512 - 885 DCS 174 - 548 **
506 ** **
507 *************************************** */
508
509 *error_flag = 0;
510
511 switch (l1_config.std.id)
512 {
513 case GSM:
514 case DCS1800:
515 case PCS1900:
516 case GSM850:
517 break;
518
519 case DUAL:
520 if ((arfcn >= 512) && (arfcn <= 885)) arfcn -= 337;
521 else if (arfcn > 124) *error_flag = 1; // invalid arfcn
522 break;
523
524 case DUALEXT:
525 if (arfcn == 0) arfcn = 174;
526 else if ((arfcn >= 975) && (arfcn <= 1023)) arfcn -= 850;
527 else if ((arfcn >= 512) && (arfcn <= 885)) arfcn -= 337;
528 else if ((arfcn >= 1) && (arfcn <= 124));
529 else *error_flag = 1; // invalide arfcn
530 break;
531
532 case DUAL_US: // GSM850:128-251 PCS1900:512-810
533 if ((arfcn >= 128) && (arfcn <= 251)) arfcn -= 127;
534 else if ((arfcn >= 512) && (arfcn <= 810)) arfcn -= 387;
535 else *error_flag = 1; // invalid arfcn
536 break;
537
538 default:
539 *error_flag = 1; // invalid std.id
540 break;
541 } // end switch
542 return arfcn;
543 }
544 #else // L1_FF_MULTIBAND = 1 below
545
546 {
547 *error_flag=0;
548 if(tm_band == RF_PCS1900)
549 {
550 arfcn = arfcn + 512;
551 }
552 return(arfcn);
553 #if 0
554 UWORD16 l1_radio_freq = 0;
555 UWORD8 effective_band_id = 0;
556 *error_flag = 1;
557 for (effective_band_id = 0; effective_band_id < RF_NB_SUBBANDS; effective_band_id ++)
558 {
559 if( multiband_conversion_data[effective_band_id].physical_band_id == tm_band)
560 {
561 if( (arfcn - multiband_conversion_data[effective_band_id].first_tpu_radio_freq) < multiband_conversion_data[effective_band_id].nbmax_carrier)
562 {
563 l1_radio_freq = arfcn - multiband_conversion_data[effective_band_id].first_tpu_radio_freq + multiband_conversion_data[effective_band_id].first_radio_freq;
564 *error_flag = 0;
565 return(l1_radio_freq);
566 }
567 }
568 }
569 return(l1_radio_freq);
570 #endif
571
572 }
573
574 #endif // #if (L1_FF_MULTIBAND == 0) else
575
576
577 void l1tm_rf_param_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
578 {
579 volatile UWORD16 value;
580
581 tm_return->index = prim->u.tm_params.index;
582
583 switch (prim->u.tm_params.index)
584 {
585 #if (FF_REPEATED_SACCH == 1 )
586 /* Repeated SACCH mode */
587 case REPEATED_SACCH_ENA_FLAG:
588 {
589 value = l1_config.repeat_sacch_enable;
590 break;
591 }
592 #endif /* FF_REPEATED_SACCH */
593
594 #if FF_REPEATED_DL_FACCH
595 // Repeated FACCH mode
596 case REPEATED_FACCHDL_ENA_FLAG:
597 {
598 value = l1_config.repeat_facch_dl_enable;
599 break;
600 }
601 #endif /* FF_REPEATED_DL_FACCH */
602
603
604 case BCCH_ARFCN:
605 {
606 // return ETSI value for channel number
607 value = Convert_l1_radio_freq(l1_config.tmode.rf_params.bcch_arfcn);
608 break;
609 }
610 case TCH_ARFCN:
611 {
612 // return ETSI value for channel number
613 value = Convert_l1_radio_freq(l1_config.tmode.rf_params.tch_arfcn);
614 break;
615 }
616 case MON_ARFCN:
617 {
618 // return ETSI value for channel number
619 value = Convert_l1_radio_freq(l1_config.tmode.rf_params.mon_arfcn);
620 break;
621 }
622 #if L1_GPRS
623 case PDTCH_ARFCN:
624 {
625 // return ETSI value for channel number
626 value = Convert_l1_radio_freq(l1_config.tmode.rf_params.pdtch_arfcn);
627 break;
628 }
629 #endif
630 case AFC_ENA_FLAG:
631 {
632 value = l1_config.afc_enable;
633 break;
634 }
635 case AFC_DAC_VALUE:
636 {
637 value = l1s.afc; // returned as F13.3
638 break;
639 }
640 #if L1_GPRS
641 case MULTISLOT_CLASS:
642 {
643 value = l1_config.tmode.rf_params.multislot_class;
644 break;
645 }
646 #endif
647 default:
648 {
649 Cust_tm_rf_param_read(tm_return, prim->u.tm_params.index);
650 return;
651 }
652 } // end switch
653
654 memcpy(tm_return->result, (UWORD8 *)&value, 2);
655 tm_return->size = 2;
656 #if (ETM_PROTOCOL == 1)
657 tm_return->status = -ETM_OK;
658 #else
659 tm_return->status = E_OK;
660 #endif
661 }
662
663 void l1tm_rf_table_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
664 {
665 Cust_tm_rf_table_write(tm_return,
666 prim->u.tm_table.index,
667 prim->str_len_in_bytes - 1, // subtract 8-bit index
668 prim->u.tm_table.table);
669 }
670
671 void l1tm_rf_table_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
672 {
673 Cust_tm_rf_table_read(tm_return, prim->u.tm_table.index);
674 }
675
676 void l1tm_rx_param_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
677 {
678 tm_return->index = prim->u.tm_params.index;
679 tm_return->size = 0;
680
681 switch (prim->u.tm_params.index)
682 {
683 case RX_AGC_GAIN:
684 {
685 WORD8 gain = prim->u.tm_params.value;
686
687 // It is up to the user to write a valid gain,
688 // one that falls within the range of gains in the current RF
689 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
690 // corresponds to the lna_off bit
691 l1_config.tmode.rx_params.agc = gain & ~0x01;
692 l1_config.tmode.rx_params.lna_off = gain & 0x01;
693 #if (ETM_PROTOCOL == 1)
694 tm_return->status = -ETM_OK;
695 #else
696 tm_return->status = E_OK;
697 #endif
698 break;
699 }
700 case RX_TIMESLOT:
701 {
702 if (prim->u.tm_params.value > 7)
703 {
704 #if (ETM_PROTOCOL == 1)
705 tm_return->status = -ETM_INVAL;
706 #else
707 tm_return->status = E_INVAL;
708 #endif
709 break;
710 }
711
712 l1_config.tmode.rx_params.slot_num = prim->u.tm_params.value;
713 if (l1_config.TestMode && l1tm.tmode_state.dedicated_active)
714 {
715 // currently CANNOT change RX slot on the fly!
716 }
717
718 #if (ETM_PROTOCOL == 1)
719 tm_return->status = -ETM_OK;
720 #else
721 tm_return->status = E_OK;
722 #endif
723 break;
724 }
725 case RX_PM_ENABLE:
726 {
727 l1_config.tmode.rx_params.pm_enable = prim->u.tm_params.value;
728
729 #if (ETM_PROTOCOL == 1)
730 tm_return->status = -ETM_OK;
731 #else
732 tm_return->status = E_OK;
733 #endif
734 break;
735 }
736 #if L1_GPRS
737 case RX_GPRS_SLOTS:
738 {
739 // At least one DL TS needs to be allocated
740 if (!prim->u.tm_params.value)
741 #if (ETM_PROTOCOL == 1)
742 tm_return->status = -ETM_INVAL;
743 #else
744 tm_return->status = E_INVAL;
745 #endif
746 else
747 {
748 l1_config.tmode.rx_params.timeslot_alloc = prim->u.tm_params.value;
749 #if (ETM_PROTOCOL == 1)
750 tm_return->status = -ETM_OK;
751 #else
752 tm_return->status = E_OK;
753 #endif
754 }
755 break;
756 }
757 case RX_GPRS_CODING:
758 {
759 UWORD8 coding_scheme;
760
761 coding_scheme = prim->u.tm_params.value;
762 if ((coding_scheme < 1) || (coding_scheme > 6) || (coding_scheme == 3))
763 #if (ETM_PROTOCOL == 1)
764 tm_return->status = -ETM_INVAL;
765 #else
766 tm_return->status = E_INVAL;
767 #endif
768 else
769 {
770 l1_config.tmode.rx_params.coding_scheme = prim->u.tm_params.value;
771 #if (ETM_PROTOCOL == 1)
772 tm_return->status = -ETM_OK;
773 #else
774 tm_return->status = E_OK;
775 #endif
776 }
777 break;
778 }
779 #endif
780 case RX_AGC_ENA_FLAG:
781 {
782 l1_config.agc_enable = prim->u.tm_params.value;
783 #if (ETM_PROTOCOL == 1)
784 tm_return->status = -ETM_OK;
785 #else
786 tm_return->status = E_OK;
787 #endif
788 break;
789 }
790 default:
791 {
792 Cust_tm_rx_param_write(tm_return,
793 prim->u.tm_params.index,
794 prim->u.tm_params.value);
795 break;
796 }
797 } // end switch
798 }
799
800 #if (L1_DRP == 1)
801 void l1tm_drp_sw_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
802 {
803 WORD8 error=0;
804 tm_return->cid=DRP_SW_WRITE;
805 tm_return->index = prim->u.tm_table.index;
806 tm_return->size = 0;
807
808 #if (ETM_PROTOCOL == 1)
809 tm_return->status = -ETM_OK;
810 #else
811 tm_return->status = E_OK;
812 #endif
813
814 switch (prim->u.tm_table.index)
815 {
816 case FFS_TO_SRM:
817 {
818 #if (OP_L1_STANDALONE ==0)
819 // Call function to load ref sw from FFS to SRM
820 error = drp_ref_sw_upload_from_ffs(prim->u.tm_table.table);
821 if(error < 0)
822 {
823 #if (ETM_PROTOCOL == 1)
824 tm_return->status = -ETM_FATAL;
825 #else
826 tm_return->status = E_INVAL;
827 #endif
828 }
829 else
830 {
831 #if (ETM_PROTOCOL == 1)
832 tm_return->status = -ETM_OK;
833 #else
834 tm_return->status = E_OK;
835 #endif
836 }
837 #else // OP_L1_STANDALONE
838 #if (ETM_PROTOCOL == 1)
839 tm_return->status = -ETM_NOSYS;
840 #else
841 tm_return->status = (UWORD8)(-E_NOSYS); //omaps00090550
842 #endif
843 #endif// OP_L1_STANDALONE
844 break;
845 }
846
847 default:
848 {
849 // nothing to do now.
850 break;
851 }
852 } // end switch
853 }
854 #endif
855
856 #if (L1_DRP == 1)
857
858 void l1tm_drp_calib_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
859 {
860 // Do Nothing Possible Future use. Intentionally left blank
861 }
862
863 void l1tm_drp_calib_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
864 {
865 INT32 error=0;//ompas00090550
866 #if (OP_L1_STANDALONE == 1)
867 UINT8 *ptrsrc, *ptrdst;
868 UINT16 indx, strsize;
869 #endif
870 UINT16 band;
871 volatile UINT16 * ptr_gpio, temp16;
872
873 #define GPIO2_LATCH_IN 0xfffe5800 // GPIO32-48 input register
874 #define GPIO2_LATCH_OUT 0xfffe5802 // GPIO32-48 output register
875 #define GPIO2_CNTL 0xfffe5804 // GPIO32-48 io config, 1=inp, 0= out
876
877 #define GPIO0_LATCH_IN 0xfffe4800 // GPIO0-15 input register
878 #define GPIO0_LATCH_OUT 0xfffe4802 // GPIO0-15 output register
879 #define GPIO0_CNTL 0xfffe4804 // GPIO0-15 io config, 1=inp, 0= out
880
881 tm_return->cid=DRP_CALIB_WRITE;
882 tm_return->index = prim->u.tm_params.index;
883 tm_return->size = 0;
884
885
886 #if (ETM_PROTOCOL == 1)
887 tm_return->status = -ETM_OK;
888 #else
889 tm_return->status = E_OK;
890 #endif
891
892 //#if (OP_L1_STANDALONE == 1)
893 #if 0
894 // Copy drp_sw_data_init into drp_sw_data_calib
895 strsize = sizeof(T_DRP_SW_DATA);
896 ptrsrc = (UINT8 *)(&drp_sw_data_init);
897 ptrdst = (UINT8 *)(&drp_sw_data_calib);
898
899 for(indx=0;indx < strsize;indx++)
900 *ptrdst++ = *ptrsrc++;
901 #endif
902
903 #if 0
904 // GPIO-47 is used for timing measurement.
905 // To enable GPIO - 47as an output, Bit 15 of GPIO2_CNTL = 0
906 ptr_gpio = (UINT16*)GPIO2_CNTL;
907 temp16 = *ptr_gpio;
908 temp16 &= ~(0x8000);
909 *ptr_gpio = temp16;
910
911 // GPIO47 = 1
912 ptr_gpio = (UINT16*)GPIO2_LATCH_OUT;
913 temp16 = *ptr_gpio;
914 temp16 |= 0x8000;
915 *ptr_gpio = temp16;
916 #endif
917 switch (tm_return->index)
918 {
919 case DRP_DUMMY: //Do Nothing Test Purposes
920 break;
921
922 case DRP_READ_FROM_FLASH: // Force the Update of drp_sw_data_calib
923 {
924 // Call function to load data sw from FFS to SRM TBD Use the new Function
925 error = drp_sw_data_calib_upload_from_ffs(&drp_sw_data_calib);
926
927 // error = drp_copy_ref_sw_to_drpsrm( (unsigned char *) &drp_ref_sw);
928
929 error = drp_copy_sw_data_to_drpsrm(&drp_sw_data_calib);
930
931 if(error < 0)
932 {
933 #if (ETM_PROTOCOL == 1)
934 tm_return->status = -ETM_FATAL;
935 #else
936 tm_return->status = E_INVAL;
937 #endif
938 }
939 else
940 {
941 #if (ETM_PROTOCOL == 1)
942 tm_return->status = -ETM_OK;
943 #else
944 tm_return->status = E_OK;
945 #endif
946 }
947
948 break;
949 }
950
951
952 case DRP_DCXO_CALIB:
953 {
954
955 #if (DRP_FW_EXT==1) //pinghua change it as 1
956 band = GSM_BAND;
957 if((g_pcb_config == RF_EU_DUALBAND) || (g_pcb_config == RF_EU_TRIBAND) || (g_pcb_config == RF_PCS1900_900_DUALBAND))
958 band = EGSM_BAND;
959
960 error = drp_dcxo_calib(band, &drp_sw_data_calib);
961 #else
962 error = drp_dcxo_calib(GSM_BAND, &drp_sw_data_calib);
963 #endif
964 if(error < 0)
965 {
966 #if (ETM_PROTOCOL == 1)
967 tm_return->status = -ETM_FATAL;
968 #else
969 tm_return->status = E_INVAL;
970 #endif
971 }
972 else
973 {
974 #if (ETM_PROTOCOL == 1)
975 tm_return->status = -ETM_OK;
976 #else
977 tm_return->status = E_OK;
978 #endif
979 }
980
981 break;
982 }
983
984
985 case DRP_TX_RX_COMMON:
986 {
987 error = drp_tx_rx_common_calib(&drp_sw_data_calib);
988
989 if(error < 0)
990 {
991 #if (ETM_PROTOCOL == 1)
992 tm_return->status = -ETM_FATAL;
993 #else
994 tm_return->status = E_INVAL;
995 #endif
996 }
997 else
998 {
999 #if (ETM_PROTOCOL == 1)
1000 tm_return->status = -ETM_OK;
1001 #else
1002 tm_return->status = E_OK;
1003 #endif
1004 }
1005 break;
1006 }
1007
1008
1009 case DRP_LNA_CFREQ:
1010 {
1011 error = drp_lna_cfreq_calib( (UWORD16) prim->u.tm_params.value, &drp_sw_data_calib);
1012 if(error < 0)
1013 {
1014 #if (ETM_PROTOCOL == 1)
1015 tm_return->status = -ETM_FATAL;
1016 #else
1017 tm_return->status = E_INVAL;
1018 #endif
1019 }
1020 else
1021 {
1022 #if (ETM_PROTOCOL == 1)
1023 tm_return->status = -ETM_OK;
1024 #else
1025 tm_return->status = E_OK;
1026 #endif
1027 }
1028 break;
1029 }
1030
1031
1032 case DRP_IQMC:
1033 {
1034 error = drp_iqmc_calib(prim->u.tm_params.value, &drp_sw_data_calib);
1035 if(error < 0)
1036 {
1037 #if (ETM_PROTOCOL == 1)
1038 tm_return->status = -ETM_FATAL;
1039 #else
1040 tm_return->status = E_INVAL;
1041 #endif
1042 }
1043 else
1044 {
1045 #if (ETM_PROTOCOL == 1)
1046 tm_return->status = -ETM_OK;
1047 #else
1048 tm_return->status = E_OK;
1049 #endif
1050 }
1051 break;
1052 }
1053
1054
1055 case DRP_MIXER_POLE:
1056 {
1057 error =drp_mixer_pole_calib(prim->u.tm_params.value, &drp_sw_data_calib);
1058 if(error < 0)
1059 {
1060 #if (ETM_PROTOCOL == 1)
1061 tm_return->status = -ETM_FATAL;
1062 #else
1063 tm_return->status = E_INVAL;
1064 #endif
1065 }
1066 else
1067 {
1068 #if (ETM_PROTOCOL == 1)
1069 tm_return->status = -ETM_OK;
1070 #else
1071 tm_return->status = E_OK;
1072 #endif
1073 }
1074 break;
1075 }
1076
1077 case DRP_SCF_POLE:
1078 {
1079 error = drp_scf_pole_calib(prim->u.tm_params.value, &drp_sw_data_calib);
1080 if(error < 0)
1081 {
1082 #if (ETM_PROTOCOL == 1)
1083 tm_return->status = -ETM_FATAL;
1084 #else
1085 tm_return->status = E_INVAL;
1086 #endif
1087 }
1088 else
1089 {
1090 #if (ETM_PROTOCOL == 1)
1091 tm_return->status = -ETM_OK;
1092 #else
1093 tm_return->status = E_OK;
1094 #endif
1095 }
1096 break;
1097 }
1098
1099
1100 case DRP_AFE_GAIN_1:
1101 {
1102 error = drp_afe_gain_calib1 (prim->u.tm_params.value, &drp_sw_data_calib);
1103 if(error < 0)
1104 {
1105 #if (ETM_PROTOCOL == 1)
1106 tm_return->status = -ETM_FATAL;
1107 #else
1108 tm_return->status = E_INVAL;
1109 #endif
1110 }
1111 else
1112 {
1113 #if (ETM_PROTOCOL == 1)
1114 tm_return->status = -ETM_OK;
1115 #else
1116 tm_return->status = E_OK;
1117 #endif
1118 }
1119 break;
1120 }
1121
1122
1123 case DRP_AFE_GAIN_2:
1124 {
1125 error = drp_afe_gain_calib2 (prim->u.tm_params.value, &drp_sw_data_calib);
1126 if(error < 0)
1127 {
1128 #if (ETM_PROTOCOL == 1)
1129 tm_return->status = -ETM_FATAL;
1130 #else
1131 tm_return->status = E_INVAL;
1132 #endif
1133 }
1134 else
1135 {
1136 #if (ETM_PROTOCOL == 1)
1137 tm_return->status = -ETM_OK;
1138 #else //OP_L1_STANDALONE == 1
1139 tm_return->status = E_OK;
1140 #endif
1141 }
1142 break;
1143 }
1144
1145
1146
1147 case DRP_WRITE_TO_FLASH:
1148 {
1149 #if (OP_L1_STANDALONE ==0)
1150 // Call function to load data sw from FFS to SRM TBD Use the new Function
1151 error = drp_sw_data_calib_upload_to_ffs(&drp_sw_data_calib);
1152
1153 // TBD the followign immediate error handling can be removed once the PS related FFS functionality is in.
1154 if (error < 0)
1155 {
1156 #if (ETM_PROTOCOL == 1)
1157 tm_return->status = -ETM_NOSYS;
1158 #else
1159 tm_return->status = E_NOSYS;//OMAPS00090550
1160 #endif
1161 return;
1162 }
1163
1164 #else // OP_L1_STANDALONE
1165
1166 if(error < 0)
1167 {
1168 #if (ETM_PROTOCOL == 1)
1169 tm_return->status = -ETM_FATAL;
1170 #else
1171 tm_return->status = E_INVAL;
1172 #endif
1173 }
1174 else
1175 {
1176 #if (ETM_PROTOCOL == 1)
1177 tm_return->status = -ETM_OK;
1178 #else
1179 tm_return->status = E_OK;
1180 #endif
1181 }
1182
1183 #endif //OP_L1_STANDALONE
1184 break;
1185 }
1186
1187 default:
1188 {
1189 // nothing to do now.
1190 }
1191 } // end switch
1192 #if 0
1193 // GPIO47 = 1
1194 ptr_gpio = (UINT16*)GPIO2_LATCH_OUT;
1195 temp16 = *ptr_gpio;
1196 temp16 &= ~(0x8000);
1197 *ptr_gpio = temp16;
1198 #endif
1199
1200 }
1201
1202 #endif //L1_DRP
1203
1204
1205
1206 void l1tm_rx_param_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1207 {
1208 volatile UWORD16 value;
1209
1210 tm_return->index = prim->u.tm_params.index;
1211
1212 switch (prim->u.tm_params.index)
1213 {
1214 case RX_AGC_GAIN:
1215 {
1216 value = l1_config.tmode.rx_params.agc | l1_config.tmode.rx_params.lna_off;
1217 break;
1218 }
1219 case RX_TIMESLOT:
1220 {
1221 value = l1_config.tmode.rx_params.slot_num;
1222 break;
1223 }
1224 case RX_AGC_ENA_FLAG:
1225 {
1226 value = l1_config.agc_enable;
1227 break;
1228 }
1229 case RX_PM_ENABLE:
1230 {
1231 value = l1_config.tmode.rx_params.pm_enable;
1232 break;
1233 }
1234 #if L1_GPRS
1235 case RX_GPRS_SLOTS:
1236 {
1237 value = l1_config.tmode.rx_params.timeslot_alloc;
1238 break;
1239 }
1240 case RX_GPRS_CODING:
1241 {
1242 value = l1_config.tmode.rx_params.coding_scheme;
1243 break;
1244 }
1245 #endif
1246 default:
1247 {
1248 Cust_tm_rx_param_read(tm_return, prim->u.tm_params.index);
1249 return;
1250 }
1251 } // end switch
1252
1253 memcpy(tm_return->result, (UWORD8 *)&value, 2);
1254 tm_return->size = 2;
1255 #if (ETM_PROTOCOL == 1)
1256 tm_return->status = -ETM_OK;
1257 #else
1258 tm_return->status = E_OK;
1259 #endif
1260 }
1261
1262 void l1tm_tx_param_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1263 {
1264 tm_return->index = prim->u.tm_params.index;
1265 tm_return->size = 0;
1266
1267 switch (prim->u.tm_params.index)
1268 {
1269 case TX_PWR_LEVEL:
1270 {
1271 UWORD8 temp_txpwr, temp_band;
1272
1273 if (prim->u.tm_params.value < 100) // GSM900
1274 {
1275 temp_txpwr = prim->u.tm_params.value;
1276 temp_band = 0;
1277 }
1278 else if (prim->u.tm_params.value < 200) // DCS1800
1279 {
1280 temp_txpwr = prim->u.tm_params.value - 100;
1281 temp_band = 1;
1282 }
1283 else if (prim->u.tm_params.value < 300) // PCS1900
1284 {
1285 temp_txpwr = prim->u.tm_params.value - 200;
1286 temp_band = 2;
1287 }
1288 else // force invalid values to return -ETM_INVAL or E_INVAL
1289 {
1290 temp_txpwr = 50;
1291 temp_band = 10;
1292 }
1293
1294 // Note that the pwr level is only checked for being within the range [0..31]
1295 // because all pwr levels should be testable.
1296 // For subfunctions [TX_APC_DAC..TX_DELAY_DOWN]:
1297 // temp_txpwr + 0 ==> GSM900
1298 // temp_txpwr + 100 ==> DCS1800
1299 // temp_txpwr + 200 ==> PCS1900
1300
1301 // Changing tx pwr level on the fly while in continuous mode is not supported.
1302 if (temp_txpwr > 31 || temp_band > 2 ||
1303 l1_config.tmode.rf_params.tmode_continuous == TM_CONTINUOUS)
1304 {
1305 #if (ETM_PROTOCOL == 1)
1306 tm_return->status = -ETM_INVAL;
1307 #else
1308 tm_return->status = E_INVAL;
1309 #endif
1310 break;
1311 }
1312
1313 l1_config.tmode.tx_params.txpwr = temp_txpwr;
1314 tx_param_band = temp_band;
1315
1316 // if in TX mode, change txpwr on the fly
1317 if ((l1_config.TestMode) &&
1318 (l1tm.tmode_state.dedicated_active) &&
1319 (l1_config.tmode.rf_params.down_up & TMODE_UPLINK))
1320 {
1321 // this causes 'direct' changing of TXPWR, which is OK in TestMode
1322 l1a_l1s_com.dedic_set.aset->new_target_txpwr = l1s.applied_txpwr = l1_config.tmode.tx_params.txpwr;
1323 }
1324
1325 #if (ETM_PROTOCOL == 1)
1326 tm_return->status = -ETM_OK;
1327 #else
1328 tm_return->status = E_OK;
1329 #endif
1330 break;
1331 }
1332 case TX_TIMING_ADVANCE:
1333 {
1334 l1_config.tmode.tx_params.timing_advance = prim->u.tm_params.value;
1335
1336 if (l1_config.TestMode && l1tm.tmode_state.dedicated_active)
1337 {
1338 // direct changing of Timing Advance
1339 l1a_l1s_com.dedic_set.aset->new_timing_advance = l1_config.tmode.tx_params.timing_advance;
1340 // new TA to take effect immediately
1341 l1a_l1s_com.dedic_set.aset->timing_advance = l1a_l1s_com.dedic_set.aset->new_timing_advance;
1342 }
1343 #if (ETM_PROTOCOL == 1)
1344 tm_return->status = -ETM_OK;
1345 #else
1346 tm_return->status = E_OK;
1347 #endif
1348 break;
1349 }
1350 case TX_PWR_SKIP:
1351 {
1352 l1_config.tmode.tx_params.txpwr_skip = prim->u.tm_params.value;
1353 #if (ETM_PROTOCOL == 1)
1354 tm_return->status = -ETM_OK;
1355 #else
1356 tm_return->status = E_OK;
1357 #endif
1358 break;
1359 }
1360 #if L1_GPRS
1361 case TX_GPRS_POWER0:
1362 case TX_GPRS_POWER1:
1363 case TX_GPRS_POWER2:
1364 case TX_GPRS_POWER3:
1365 case TX_GPRS_POWER4:
1366 case TX_GPRS_POWER5:
1367 case TX_GPRS_POWER6:
1368 case TX_GPRS_POWER7:
1369 {
1370 l1_config.tmode.tx_params.txpwr_gprs[prim->u.tm_params.index - TX_GPRS_POWER0] = prim->u.tm_params.value;
1371 #if (ETM_PROTOCOL == 1)
1372 tm_return->status = -ETM_OK;
1373 #else
1374 tm_return->status = E_OK;
1375 #endif
1376 break;
1377 }
1378 case TX_GPRS_SLOTS:
1379 {
1380 l1_config.tmode.tx_params.timeslot_alloc = prim->u.tm_params.value;
1381 #if (ETM_PROTOCOL == 1)
1382 tm_return->status = -ETM_OK;
1383 #else
1384 tm_return->status = E_OK;
1385 #endif
1386 break;
1387 }
1388 case TX_GPRS_CODING:
1389 {
1390 UWORD8 coding_scheme;
1391
1392 coding_scheme = prim->u.tm_params.value;
1393 if ((coding_scheme < 2) || (coding_scheme > 6) || (coding_scheme == 3))
1394 #if (ETM_PROTOCOL == 1)
1395 tm_return->status = -ETM_INVAL;
1396 #else
1397 tm_return->status = E_INVAL;
1398 #endif
1399 else
1400 {
1401 l1_config.tmode.tx_params.coding_scheme = prim->u.tm_params.value;
1402 #if (ETM_PROTOCOL == 1)
1403 tm_return->status = -ETM_OK;
1404 #else
1405 tm_return->status = E_OK;
1406 #endif
1407 }
1408 break;
1409 }
1410 #endif
1411 default:
1412 {
1413 Cust_tm_tx_param_write(tm_return,
1414 prim->u.tm_params.index,
1415 prim->u.tm_params.value,
1416 tx_param_band);
1417 break;
1418 }
1419 } // end switch
1420 }
1421
1422 void l1tm_tx_param_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1423 {
1424 tm_return->index = prim->u.tm_params.index;
1425
1426 Cust_tm_tx_param_read(tm_return,
1427 prim->u.tm_params.index,
1428 tx_param_band);
1429 }
1430
1431 void l1tm_tx_template_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1432 {
1433 Cust_tm_tx_template_write(tm_return,
1434 prim->u.tm_table.index,
1435 prim->str_len_in_bytes - 1, // subtract 8-bit index
1436 prim->u.tm_table.table);
1437 }
1438
1439 void l1tm_tx_template_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1440 {
1441 Cust_tm_tx_template_read(tm_return, prim->u.tm_table.index);
1442 }
1443
1444 void l1tm_special_param_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1445 {
1446 Cust_tm_special_param_write(tm_return,
1447 prim->u.tm_params.index,
1448 prim->u.tm_params.value);
1449 }
1450
1451 void l1tm_special_param_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1452 {
1453 Cust_tm_special_param_read(tm_return, prim->u.tm_params.index);
1454 }
1455
1456 void l1tm_special_table_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1457 {
1458 Cust_tm_special_table_write(tm_return,
1459 prim->u.tm_table.index,
1460 prim->str_len_in_bytes - 1,
1461 prim->u.tm_table.table);
1462 }
1463
1464 void l1tm_special_table_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1465 {
1466 Cust_tm_special_table_read(tm_return, prim->u.tm_table.index);
1467 }
1468
1469 void l1tm_special_enable(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1470 {
1471 Cust_tm_special_enable(tm_return, prim->u.tm_params.index);
1472 }
1473
1474 /*-------------------------------------------------------*/
1475 /* l1tm_initialize_var() */
1476 /*-------------------------------------------------------*/
1477 /* Parameters : */
1478 /* ------------- */
1479 /* Return : */
1480 /* ------------- */
1481 /* Description : */
1482 /* ------------- */
1483 /* This routine is used to switch to TestMode by re- */
1484 /* initializing the l1a, l1s and l1a_l1s_com global */
1485 /* structures. Re-initialization is kept at a minimum. */
1486 /*-------------------------------------------------------*/
1487 void l1tm_initialize_var(void)
1488 {
1489 UWORD32 i;
1490 UWORD8 task_id;
1491
1492
1493 // L1S tasks management...
1494 //-----------------------------------------
1495 for(task_id=0; task_id<NBR_DL_L1S_TASKS; task_id++)
1496 {
1497 l1s.task_status[task_id].new_status = NOT_PENDING;
1498 l1s.task_status[task_id].current_status = INACTIVE;
1499 }
1500 l1s.frame_count = 0;
1501 l1s.forbid_meas = 0;
1502
1503 // MFTAB management variables...
1504 //-----------------------------------------
1505 l1s.afrm = 0;
1506 l1s_clear_mftab(l1s.mftab.frmlst);
1507
1508 // Flag registers for RF task controle...
1509 //-----------------------------------------
1510 l1s.tpu_ctrl_reg = 0;
1511 l1s.dsp_ctrl_reg = 0;
1512
1513 //++++++++++++++++++++++++++++++++++++++++++
1514 // Reset "l1a" structure.
1515 //++++++++++++++++++++++++++++++++++++++++++
1516
1517 // Downlink tasks management...
1518 // Uplink tasks management...
1519 // Measurement tasks management...
1520 //-----------------------------------------
1521 for(i=0; i<NBR_L1A_PROCESSES; i++)
1522 {
1523 l1a.l1a_en_meas[i] = 0;
1524 l1a.state[i] = 0; // RESET state.
1525 }
1526
1527 // Flag for forward/delete message management.
1528 //---------------------------------------------
1529 l1a.l1_msg_forwarded = 0;
1530
1531
1532 //++++++++++++++++++++++++++++++++++++++++++
1533 // Reset "l1a_l1s_com" structure.
1534 //++++++++++++++++++++++++++++++++++++++++++
1535
1536 l1a_l1s_com.l1a_activity_flag = TRUE;
1537 l1a_l1s_com.time_to_next_l1s_task = 0;
1538
1539
1540 // sleep management configuration
1541 //===============================
1542 l1s.pw_mgr.mode_authorized = NO_SLEEP;
1543
1544 // L1S scheduler...
1545 //====================
1546
1547 // L1S tasks management...
1548 //-----------------------------------------
1549 for(i=0; i<NBR_DL_L1S_TASKS; i++)
1550 {
1551 l1a_l1s_com.task_param[i] = SEMAPHORE_RESET;
1552 l1a_l1s_com.l1s_en_task[i] = TASK_DISABLED;
1553 }
1554
1555 // Measurement tasks management...
1556 //-----------------------------------------
1557 l1a_l1s_com.meas_param = 0;
1558 l1a_l1s_com.l1s_en_meas = 0;
1559
1560 #if L1_GPRS
1561 // Set DSP scheduler mode
1562 l1a_l1s_com.dsp_scheduler_mode = GSM_SCHEDULER;
1563 // Packet measurement: Reset of the frequency list.
1564 //-------------------------------------------------
1565 l1pa_reset_cr_freq_list();
1566 // Initialize active list used in Neighbour Measurement Transfer Process
1567 l1pa_l1ps_com.cres_freq_list.alist = &(l1pa_l1ps_com.cres_freq_list.list[0]);
1568
1569 l1pa_l1ps_com.transfer.semaphore = TRUE;
1570 l1pa_l1ps_com.transfer.aset = &(l1pa_l1ps_com.transfer.set[0]);
1571 l1pa_l1ps_com.transfer.fset[0] = &(l1pa_l1ps_com.transfer.set[1]);
1572 l1pa_l1ps_com.transfer.fset[1] = &(l1pa_l1ps_com.transfer.set[2]);
1573
1574 for(i=0;i<3;i++)
1575 {
1576 l1pa_l1ps_com.transfer.set[i].SignalCode = 0;
1577 l1pa_l1ps_com.transfer.set[i].dl_tbf_synchro_timeslot = 0;
1578 l1pa_l1ps_com.transfer.set[i].dl_tbf_synchro_timeslot = 0;
1579 l1pa_l1ps_com.transfer.set[i].transfer_synchro_timeslot = 0;
1580 l1pa_l1ps_com.transfer.set[i].allocated_tbf = NO_TBF;
1581 l1pa_l1ps_com.transfer.set[i].assignment_command = NO_TBF;
1582 l1pa_l1ps_com.transfer.set[i].multislot_class = 0;
1583
1584 l1pa_l1ps_com.transfer.set[i].packet_ta.ta = 255;
1585 l1pa_l1ps_com.transfer.set[i].packet_ta.ta_index = 255;
1586 l1pa_l1ps_com.transfer.set[i].packet_ta.ta_tn = 255;
1587
1588 l1pa_l1ps_com.transfer.set[i].tsc = 0;
1589
1590 l1pa_l1ps_com.transfer.set[i].freq_param.chan_sel.h = 0;
1591 l1pa_l1ps_com.transfer.set[i].freq_param.chan_sel.
1592 rf_channel.single_rf.radio_freq = 0;
1593
1594 l1pa_l1ps_com.transfer.set[i].tbf_sti.present = FALSE;
1595
1596 l1pa_l1ps_com.transfer.set[i].mac_mode = 0;
1597
1598 l1pa_l1ps_com.transfer.set[i].ul_tbf_alloc->tfi = 255;
1599 l1pa_l1ps_com.transfer.set[i].dl_tbf_alloc.tfi = 255;
1600
1601 l1pa_l1ps_com.transfer.set[i].dl_pwr_ctl.p0 = 255;
1602 l1pa_l1ps_com.transfer.set[i].dl_pwr_ctl.bts_pwr_ctl_mode = 0;
1603 l1pa_l1ps_com.transfer.set[i].dl_pwr_ctl.pr_mode = 0;
1604 }
1605 #endif
1606
1607 // Init global test mode variables
1608 l1tm.tmode_state.dedicated_active = 0;
1609 #if L1_GPRS
1610 l1tm.tmode_state.packet_transfer_active = FALSE;
1611 #endif
1612
1613 // PRBS seed initialization with a random pattern
1614 l1tm.tmode_prbs.prbs1_seed = 0x5613;
1615 }
1616
1617 void l1tm_rf_enable(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
1618 {
1619 unsigned SignalCode =0;
1620 unsigned size = 0; //omaps00090550
1621 xSignalHeaderRec *msg;
1622 UWORD8 send_prim = FALSE; // Flag to send TestMode primitive...
1623 // Do not send primitive is the default; change it if necessary
1624 UWORD8 band;
1625 tm_return->index = 0; // don't include index in header
1626 #if (ETM_PROTOCOL == 1)
1627 tm_return->status = -ETM_OK;
1628 #else
1629 tm_return->status = E_OK;
1630 #endif
1631
1632 // Function only valid in TEST mode
1633 if (l1_config.TestMode == 0)
1634 {
1635 #if (ETM_PROTOCOL == 1)
1636 tm_return->status = -ETM_L1TESTMODE;
1637 #else
1638 tm_return->status = E_TESTMODE;
1639 #endif
1640 }
1641 else
1642 {
1643 // Reset all statistics
1644 l1tm_reset_rx_stats();
1645
1646 // Reset receive state counters, unless already in dedicated mode
1647 if (!l1tm.tmode_state.dedicated_active)
1648 l1tm_reset_rx_state();
1649
1650 // Reset monitor task
1651 l1_config.tmode.rf_params.mon_report = 0;
1652 l1_config.tmode.rf_params.mon_tasks = 0;
1653
1654 switch (prim->u.tm_params.index)
1655 {
1656 // Stop all RX and TX operations
1657 case STOP_ALL:
1658 {
1659 SignalCode = TMODE_STOP_RX_TX;
1660 size = sizeof(T_TMODE_STOP_RX_TX);
1661 l1tm.tmode_state.dedicated_active = 0;
1662 #if (RF_FAM == 61)
1663 // Reset the APC back to Automatic Mode
1664 l1ddsp_apc_set_automatic_mode();
1665 #endif
1666
1667 #if (RF_FAM == 35)
1668 pll_tuning.enable=0;
1669 #endif
1670 // Reset down_up flag only if not in continuous mode. If in continuous mode, down_up
1671 // will be reset after the proper TPU scenario is loaded.
1672 if (l1_config.tmode.rf_params.tmode_continuous != TM_CONTINUOUS)
1673 l1_config.tmode.rf_params.down_up = 0;
1674 send_prim = TRUE;
1675 break;
1676 }
1677 // RX with or without network synchronization first
1678 case RX_TCH:
1679 {
1680 // if already in UL-only
1681 if (l1tm.tmode_state.dedicated_active &&
1682 l1_config.tmode.rf_params.down_up == TMODE_UPLINK)
1683 {
1684 // cannot start to RX while already TXing
1685 #if (ETM_PROTOCOL == 1)
1686 tm_return->status = -ETM_AGAIN;
1687 #else
1688 tm_return->status = E_AGAIN;
1689 #endif
1690 }
1691 else
1692 {
1693 l1_config.tmode.rf_params.down_up = TMODE_DOWNLINK;
1694 SignalCode = TMODE_IMMED_ASSIGN_REQ;
1695 size = sizeof(T_TMODE_IMMED_ASSIGN_REQ);
1696 send_prim = TRUE;
1697 }
1698 break;
1699 }
1700 // TX NB's or AB's on TCH with or without network synch. first
1701 case TX_TCH:
1702 {
1703 // Normal burst TX
1704 if (l1_config.tmode.tx_params.burst_type == 0)
1705 {
1706 // if already in DL-only, add UL
1707 if (l1tm.tmode_state.dedicated_active &&
1708 l1_config.tmode.rf_params.down_up == TMODE_DOWNLINK)
1709 {
1710 l1_config.tmode.rf_params.down_up = (TMODE_DOWNLINK | TMODE_UPLINK);
1711 }
1712 else
1713 {
1714 l1_config.tmode.rf_params.down_up = TMODE_UPLINK;
1715 SignalCode = TMODE_IMMED_ASSIGN_REQ;
1716 size = sizeof(T_TMODE_IMMED_ASSIGN_REQ);
1717 send_prim = TRUE;
1718 }
1719 }
1720 // AB TX
1721 else if (l1_config.tmode.tx_params.burst_type == 1)
1722 {
1723 // cannot start RACH while already in dedicated mode
1724 if (l1tm.tmode_state.dedicated_active)
1725 {
1726 #if (ETM_PROTOCOL == 1)
1727 tm_return->status = -ETM_AGAIN;
1728 #else
1729 tm_return->status = E_AGAIN;
1730 #endif
1731 }
1732 else
1733 {
1734 SignalCode = TMODE_RA_START;
1735 size = sizeof(TMODE_RA_START);
1736 send_prim = TRUE;
1737 }
1738 }
1739 break;
1740 }
1741 // RX & TX on TCH with or without network synch. first
1742 case RX_TX_TCH:
1743 {
1744 // if NB TX
1745 if (l1_config.tmode.tx_params.burst_type == 0)
1746 {
1747 // if already in DL-only, add UL
1748 if (l1tm.tmode_state.dedicated_active &&
1749 l1_config.tmode.rf_params.down_up == TMODE_DOWNLINK)
1750 {
1751 l1_config.tmode.rf_params.down_up = (TMODE_DOWNLINK | TMODE_UPLINK);
1752 }
1753 // else if already in UL-only
1754 else if (l1tm.tmode_state.dedicated_active &&
1755 l1_config.tmode.rf_params.down_up == TMODE_UPLINK)
1756 {
1757 // cannot start to RX while already TXing
1758 #if (ETM_PROTOCOL == 1)
1759 tm_return->status = -ETM_AGAIN;
1760 #else
1761 tm_return->status = E_AGAIN;
1762 #endif
1763 }
1764 else
1765 {
1766 l1_config.tmode.rf_params.down_up = (TMODE_DOWNLINK | TMODE_UPLINK);
1767 SignalCode = TMODE_IMMED_ASSIGN_REQ;
1768 size = sizeof(T_TMODE_IMMED_ASSIGN_REQ);
1769 send_prim = TRUE;
1770 }
1771 }
1772 // else if AB TX
1773 else if (l1_config.tmode.tx_params.burst_type == 1)
1774 {
1775 // Cannot TX RACH and RX simultaneously
1776 #if (ETM_PROTOCOL == 1)
1777 tm_return->status = -ETM_AGAIN;
1778 #else
1779 tm_return->status = E_AGAIN;
1780 #endif
1781 }
1782 break;
1783 }
1784 // Continuous (all timeslots) reception on TCH
1785 case RX_TCH_CONT:
1786 {
1787 // if already in UL, DL or UL+DL
1788 if (l1tm.tmode_state.dedicated_active &&
1789 l1_config.tmode.rf_params.down_up != 0)
1790 {
1791 // cannot start to continously RX while already TXing or RXing
1792 #if (ETM_PROTOCOL == 1)
1793 tm_return->status = -ETM_AGAIN;
1794 #else
1795 tm_return->status = E_AGAIN;
1796 #endif
1797 }
1798 else
1799 {
1800 l1_config.tmode.rf_params.tmode_continuous = TM_START_RX_CONTINUOUS;
1801 l1_config.tmode.rf_params.down_up = TMODE_DOWNLINK;
1802 SignalCode = TMODE_IMMED_ASSIGN_REQ;
1803 size = sizeof(T_TMODE_IMMED_ASSIGN_REQ);
1804 send_prim = TRUE;
1805 }
1806 break;
1807 }
1808 // continuous (all timeslots) transmission
1809 case TX_TCH_CONT:
1810 {
1811 // PCS 1900 not supported yet.
1812 #if (L1_FF_MULTIBAND == 0)
1813 band = ((l1_config.tmode.rf_params.tch_arfcn >= 512) &&
1814 (l1_config.tmode.rf_params.tch_arfcn <= 885));
1815 #else
1816 band = ( ((l1_config.tmode.rf_params.tch_arfcn >= 512) &&
1817 (l1_config.tmode.rf_params.tch_arfcn <= 885)) ||
1818 ((l1_config.tmode.rf_params.tch_arfcn >= 1024) &&
1819 (l1_config.tmode.rf_params.tch_arfcn <= 1322)) );
1820 #endif
1821
1822 // if already in UL, DL or UL+DL
1823 if ((l1tm.tmode_state.dedicated_active && l1_config.tmode.rf_params.down_up != 0) ||
1824 (band == 0 && (l1_config.tmode.tx_params.txpwr < (5 + l1_config.tmode.tx_params.txpwr_skip))) ||
1825 (band == 1 && (l1_config.tmode.tx_params.txpwr < (0 + l1_config.tmode.tx_params.txpwr_skip))))
1826 {
1827 // cannot start to continously TX while already TXing or RXing
1828 // or while adc reading are enabled
1829 #if (ETM_PROTOCOL == 1)
1830 tm_return->status = -ETM_INVAL;
1831 #else
1832 tm_return->status = E_INVAL;
1833 #endif
1834 }
1835 else
1836 {
1837 #if (RF_FAM == 61)
1838 // Set APC in Manual Mode
1839 l1ddsp_apc_set_manual_mode();
1840 #endif
1841 l1_config.tmode.rf_params.tmode_continuous = TM_START_TX_CONTINUOUS;
1842 l1_config.tmode.rf_params.down_up = TMODE_UPLINK;
1843 SignalCode = TMODE_IMMED_ASSIGN_REQ;
1844 size = sizeof(T_TMODE_IMMED_ASSIGN_REQ);
1845 send_prim = TRUE;
1846 }
1847 break;
1848 }
1849 // Continuous BCCH
1850 case BCCH_LOOP:
1851 {
1852 SignalCode = TMODE_SCELL_NBCCH_REQ;
1853 size = sizeof(TMODE_SCELL_NBCCH_REQ);
1854 send_prim = TRUE;
1855 break;
1856 }
1857 // Continuous SB
1858 case SB_LOOP:
1859 {
1860 SignalCode = TMODE_SB_REQ;
1861 size = sizeof(T_TMODE_SB_REQ);
1862 send_prim = TRUE;
1863 break;
1864 }
1865 // Continuous FB1
1866 case FB1_LOOP:
1867 {
1868 SignalCode = TMODE_FB1_REQ;
1869 size = sizeof(T_TMODE_FB1_REQ);
1870 send_prim = TRUE;
1871 break;
1872 }
1873 // Continuous FB0
1874 case FB0_LOOP:
1875 {
1876 SignalCode = TMODE_FB0_REQ;
1877 size = sizeof(T_TMODE_FB0_REQ);
1878 send_prim = TRUE;
1879 break;
1880 }
1881 // TX + RX + MON on TCH
1882 case RX_TX_MON_TCH: // Stats collected from TCH Channel.
1883 case RX_TX_MON: // Stats collected from MON Channel (except rxlev).
1884 {
1885 // Normal burst uplink
1886 if (l1_config.tmode.tx_params.burst_type == 0)
1887 {
1888 // If already in dedicated mode, return error
1889 if (l1tm.tmode_state.dedicated_active)
1890 {
1891 #if (ETM_PROTOCOL == 1)
1892 tm_return->status = -ETM_AGAIN;
1893 #else
1894 tm_return->status = E_AGAIN;
1895 #endif
1896 }
1897 else
1898 {
1899 l1_config.tmode.rf_params.down_up = (TMODE_DOWNLINK | TMODE_UPLINK);
1900 l1_config.tmode.rf_params.mon_report = ((prim->u.tm_params.index & 0x08) >> 3);
1901 l1_config.tmode.rf_params.mon_tasks = 1; // enable MON tasks
1902 SignalCode = TMODE_IMMED_ASSIGN_REQ;
1903 size = sizeof(T_TMODE_IMMED_ASSIGN_REQ);
1904 send_prim = TRUE;
1905 }
1906 }
1907 // else if Access burst uplink
1908 else if (l1_config.tmode.tx_params.burst_type == 1)
1909 {
1910 // Cannot TX RACH and RX simultaneously
1911 #if (ETM_PROTOCOL == 1)
1912 tm_return->status = -ETM_AGAIN;
1913 #else
1914 tm_return->status = E_AGAIN;
1915 #endif
1916 }
1917 break;
1918 }
1919 case SINGLE_PM:
1920 {
1921 SignalCode = TMODE_RXLEV_REQ;
1922 size = sizeof(T_TMODE_RXLEV_REQ);
1923 send_prim = TRUE;
1924 break;
1925 }
1926 #if L1_GPRS
1927 // RX & TX on PDTCH with or without network synch. first
1928 case RX_TX_PDTCH:
1929 {
1930 UWORD8 bit_map = 0x80;
1931
1932 // set uplink + downlink
1933 if (l1_config.tmode.tx_params.timeslot_alloc)
1934 l1_config.tmode.rf_params.down_up = TMODE_DOWNLINK | TMODE_UPLINK;
1935 else
1936 l1_config.tmode.rf_params.down_up = TMODE_DOWNLINK;
1937
1938 while (bit_map)
1939 {
1940 if (bit_map & l1_config.tmode.stats_config.stat_gprs_slots)
1941 l1tm.tmode_stats.nb_dl_pdtch_slots ++;
1942
1943 bit_map>>=1;
1944 }
1945
1946 SignalCode = TMODE_PDTCH_ASSIGN_REQ;
1947 size = sizeof(T_TMODE_PDTCH_ASSIGN_REQ);
1948 send_prim = TRUE;
1949 break;
1950 }
1951 #endif
1952 #if L1_GPRS
1953 // RX & TX on PDTCH, FB on monitor arfcn
1954 case RX_TX_PDTCH_MON:
1955 {
1956 // set uplink + downlink
1957 if (l1_config.tmode.tx_params.timeslot_alloc)
1958 l1_config.tmode.rf_params.down_up = TMODE_DOWNLINK | TMODE_UPLINK;
1959 else
1960 l1_config.tmode.rf_params.down_up = TMODE_DOWNLINK;
1961
1962 l1_config.tmode.rf_params.mon_report = 1; // collect stats from MON channel
1963 l1_config.tmode.rf_params.mon_tasks = 1; // enable MON tasks
1964
1965 SignalCode = TMODE_PDTCH_ASSIGN_REQ;
1966 size = sizeof(T_TMODE_PDTCH_ASSIGN_REQ);
1967 send_prim = TRUE;
1968 break;
1969 }
1970 #endif
1971 #if (RF_FAM == 35)
1972 case RX_PLL_TUNING:
1973 {
1974 // if already in UL-only
1975 if (l1tm.tmode_state.dedicated_active &&
1976 l1_config.tmode.rf_params.down_up == TMODE_UPLINK)
1977 {
1978 // cannot start to RX while already TXing
1979 #if (ETM_PROTOCOL == 1)
1980 tm_return->status = -ETM_AGAIN;
1981 #else
1982 tm_return->status = E_AGAIN;
1983 #endif
1984 }
1985 else
1986 {
1987 pll_tuning.data[5] = 0;
1988 pll_tuning.index = 0;
1989
1990 pll_tuning.enable = 1;
1991
1992 l1_config.tmode.rf_params.down_up = TMODE_DOWNLINK;
1993 SignalCode = TMODE_IMMED_ASSIGN_REQ;
1994 size = sizeof(T_TMODE_IMMED_ASSIGN_REQ);
1995 send_prim = TRUE;
1996 }
1997 break;
1998 }
1999 #endif
2000 default:
2001 {
2002 #if (ETM_PROTOCOL == 1)
2003 tm_return->status = -ETM_INVAL;
2004 #else
2005 tm_return->status = E_BADINDEX;
2006 #endif
2007 break;
2008 }
2009 } //end switch
2010 } // end of else
2011
2012 if (send_prim == TRUE)
2013 {
2014 // Allocate result message.
2015 msg = os_alloc_sig(size);
2016 DEBUGMSG(status,NU_ALLOC_ERR)
2017 msg->SignalCode = SignalCode;
2018 os_send_sig(msg, L1C1_QUEUE);
2019 DEBUGMSG(status,NU_SEND_QUEUE_ERR)
2020 }
2021
2022 // always return a 0 in the result[], even if error
2023 tm_return->result[0] = 0;
2024 tm_return->size = 1;
2025 }
2026
2027
2028 void l1tm_stats_config_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
2029 {
2030 tm_return->index = prim->u.tm_params.index;
2031 tm_return->size = 0;
2032
2033 switch (prim->u.tm_params.index)
2034 {
2035 case LOOPS:
2036 {
2037 l1_config.tmode.stats_config.num_loops = prim->u.tm_params.value;
2038 #if (ETM_PROTOCOL == 1)
2039 tm_return->status = -ETM_OK;
2040 #else
2041 tm_return->status = E_OK;
2042 #endif
2043 break;
2044 }
2045 case AUTO_RESULT_LOOPS:
2046 {
2047 l1_config.tmode.stats_config.auto_result_loops = prim->u.tm_params.value;
2048 #if (ETM_PROTOCOL == 1)
2049 tm_return->status = -ETM_OK;
2050 #else
2051 tm_return->status = E_OK;
2052 #endif
2053 break;
2054 }
2055 case AUTO_RESET_LOOPS:
2056 {
2057 l1_config.tmode.stats_config.auto_reset_loops = prim->u.tm_params.value;
2058 #if (ETM_PROTOCOL == 1)
2059 tm_return->status = -ETM_OK;
2060 #else
2061 tm_return->status = E_OK;
2062 #endif
2063 break;
2064 }
2065 case STAT_TYPE:
2066 {
2067 l1_config.tmode.stats_config.stat_type = prim->u.tm_params.value;
2068 #if (ETM_PROTOCOL == 1)
2069 tm_return->status = -ETM_OK;
2070 #else
2071 tm_return->status = E_OK;
2072 #endif
2073 break;
2074 }
2075 case STAT_BITMASK:
2076 {
2077 l1_config.tmode.stats_config.stat_bitmask = prim->u.tm_params.value;
2078 #if (ETM_PROTOCOL == 1)
2079 tm_return->status = -ETM_OK;
2080 #else
2081 tm_return->status = E_OK;
2082 #endif
2083 break;
2084 }
2085 #if L1_GPRS
2086 case STAT_GPRS_SLOTS:
2087 {
2088 UWORD8 allocation, value;
2089
2090 value = prim->u.tm_params.value;
2091
2092 // Check for mismatch between DL TS allocation and stats bitmap
2093 allocation = value ^ l1_config.tmode.rx_params.timeslot_alloc;
2094
2095 if (value & allocation)
2096 #if (ETM_PROTOCOL == 1)
2097 tm_return->status = -ETM_INVAL;
2098 #else
2099 tm_return->status = E_INVAL;
2100 #endif
2101 else
2102 {
2103 l1_config.tmode.stats_config.stat_gprs_slots = value;
2104 #if (ETM_PROTOCOL == 1)
2105 tm_return->status = -ETM_OK;
2106 #else
2107 tm_return->status = E_OK;
2108 #endif
2109 }
2110 break;
2111 }
2112 #endif
2113 default:
2114 {
2115 #if (ETM_PROTOCOL == 1)
2116 tm_return->status = -ETM_INVAL;
2117 #else
2118 tm_return->status = E_BADINDEX;
2119 #endif
2120 break;
2121 }
2122 } // end switch
2123 }
2124
2125 void l1tm_stats_config_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
2126 {
2127 volatile UWORD16 value;
2128
2129 tm_return->index = prim->u.tm_params.index;
2130
2131 switch (prim->u.tm_params.index)
2132 {
2133 case LOOPS:
2134 {
2135 value = l1_config.tmode.stats_config.num_loops;
2136 break;
2137 }
2138 case AUTO_RESULT_LOOPS:
2139 {
2140 value = l1_config.tmode.stats_config.auto_result_loops;
2141 break;
2142 }
2143 case AUTO_RESET_LOOPS:
2144 {
2145 value = l1_config.tmode.stats_config.auto_reset_loops;
2146 break;
2147 }
2148 case STAT_TYPE:
2149 {
2150 value = l1_config.tmode.stats_config.stat_type;
2151 break;
2152 }
2153 case STAT_BITMASK:
2154 {
2155 value = l1_config.tmode.stats_config.stat_bitmask;
2156 break;
2157 }
2158 #if L1_GPRS
2159 case STAT_GPRS_SLOTS:
2160 {
2161 value = l1_config.tmode.stats_config.stat_gprs_slots;
2162 break;
2163 }
2164 #endif
2165 default:
2166 {
2167 #if (ETM_PROTOCOL == 1)
2168 tm_return->status = -ETM_INVAL;
2169 #else
2170 tm_return->status = E_BADINDEX;
2171 #endif
2172 tm_return->size = 0;
2173 return;
2174 }
2175 } // end switch
2176
2177 memcpy(tm_return->result, (UWORD8 *) &value, 2);
2178 tm_return->size = 2;
2179 #if (ETM_PROTOCOL == 1)
2180 tm_return->status = -ETM_OK;
2181 #else
2182 tm_return->status = E_OK;
2183 #endif
2184 }
2185
2186 void l1tm_statistics(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
2187 {
2188 l1tm_stats_read(tm_return,
2189 prim->u.tm_params.index,
2190 prim->u.tm_params.value);
2191 }
2192
2193 #if L1_GPRS
2194 void l1tm_rlc_uplink(UWORD8 tx, API *ul_data)
2195 {
2196 // Cast the ul_data_buffer
2197 typedef struct
2198 {
2199 API a_ul_data[4][29];
2200 }
2201 T_A_UL_DATA;
2202
2203 T_A_UL_DATA *ptr = (T_A_UL_DATA*) ul_data;
2204 UWORD8 i,j;
2205
2206 for (j=0; j<tx; j++)
2207 {
2208 ptr->a_ul_data[j][0] = l1_config.tmode.tx_params.coding_scheme;
2209
2210 for (i=0;i<l1_config.tmode.tx_params.rlc_buffer_size;i++)
2211 ptr->a_ul_data[j][i+1] = l1_config.tmode.tx_params.rlc_buffer[i];
2212 }
2213 }
2214 #endif
2215
2216 void l1tm_stats_read(T_TM_RETURN *tm_return, WORD16 type, UWORD16 bitmask)
2217 {
2218 extern T_L1A_L1S_COM l1a_l1s_com;
2219 extern T_L1S_GLOBAL l1s;
2220 volatile UWORD32 utemp = bitmask, temp_U32;
2221 volatile WORD32 temp = type;
2222 volatile WORD32 value_signed_int;
2223 volatile UWORD32 value_unsigned_int;
2224 volatile UWORD16 value_unsigned_short;
2225 UWORD8 j, offset=0; // offset is index of tm_return->result[]
2226 UWORD16 rssi, len;
2227 WORD32 count;
2228 WORD32 runs = l1tm.tmode_stats.loop_count;
2229
2230 #if L1_GPRS
2231 volatile UWORD16 value_array_unsigned_short[4];
2232 #endif
2233
2234 // Put type and bitmask in the front of tm_return->result[].
2235 // Use volatile vars for proper operation of memcpy().
2236 memcpy(&tm_return->result[offset], (UWORD8 *) &temp, 2);
2237 offset+=2;
2238 memcpy(&tm_return->result[offset], (UWORD8 *) &utemp, 2);
2239 offset+=2;
2240
2241 switch (type)
2242 {
2243 // Accumulated receive burst stats
2244 case ACCUMULATED_RX_STATS:
2245 {
2246 // all stats saved when collected from TCH
2247 if (l1tm.tmode_state.dedicated_active && (l1_config.tmode.rf_params.mon_report == 0))
2248 count = l1tm.tmode_stats.loop_count;
2249 #if L1_GPRS
2250 else if (l1tm.tmode_state.packet_transfer_active && (l1_config.tmode.rf_params.mon_report == 0))
2251 {
2252 // loop_count contains the number of blocks
2253 // Stats (PM, TOA, SNR, ANGLE) are accumulated over all frames and all time slots
2254 count = l1tm.tmode_stats.loop_count * l1tm.tmode_stats.nb_dl_pdtch_slots * 4;
2255
2256 // the count of runs vs. successes is accumulated over all time slots per block
2257 runs = l1tm.tmode_stats.loop_count * l1tm.tmode_stats.nb_dl_pdtch_slots;
2258 }
2259 #endif
2260 else count = l1tm.tmode_stats.flag_count; // only PASS stats saved
2261
2262 if (bitmask & RSSI) // rxlev: RSSI SF12.4 eventually (currently F7.1)
2263 {
2264 len = sizeof(l1tm.tmode_stats.rssi_fifo) / sizeof(l1tm.tmode_stats.rssi_fifo[0]);
2265 rssi = 0;
2266 for (j=0; j<len; j++)
2267 rssi += l1tm.tmode_stats.rssi_fifo[j];
2268 rssi /= len; // F7.1
2269 memcpy(&tm_return->result[offset], (UWORD8 *) &rssi, 2);
2270 offset+=2;
2271 }
2272 // pm: DSP MEAN power measurement UF10.6
2273 if (bitmask & DSP_PM)
2274 {
2275 if (count)
2276 value_unsigned_short = (UWORD16)(l1tm.tmode_stats.pm_sum) / count; //omaps00090550
2277 else value_unsigned_short = 0;
2278 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_short, 2);
2279 offset+=2;
2280 }
2281 // angle mean
2282 if (bitmask & ANGLE_MEAN)
2283 {
2284 if (count) // non-zero
2285 value_signed_int = (UWORD16)(l1tm.tmode_stats.angle_sum) / count; //omaps00090550
2286 else value_signed_int = 0;
2287 memcpy(&tm_return->result[offset], (UWORD8 *) &value_signed_int, 4);
2288 offset+=4;
2289 }
2290 // angle variance
2291 if (bitmask & ANGLE_VAR)
2292 {
2293 // VAR[X] = E[X^2] - (E[X])^2
2294 if (count) // non-zero
2295 {
2296 UWORD32 u32dvsor ;
2297 temp_U32 = l1tm.tmode_stats.angle_sum;
2298 u32dvsor = (temp_U32 /(UWORD32)count);
2299 temp_U32= u32dvsor;
2300 u32dvsor *= (temp_U32);
2301 u32dvsor *= (temp_U32);
2302 value_unsigned_int = l1tm.tmode_stats.angle_sq_sum / (UWORD32)count - u32dvsor;
2303 // temp_U32 = (UWORD16)(l1tm.tmode_stats.angle_sum) / (count); //omaps00090550
2304 // u32dvsor = count -((temp_U32) * (temp_U32 )) ;
2305
2306 // value_unsigned_int = (UWORD16)l1tm.tmode_stats.angle_sq_sum / u32dvsor ; //omaps00090550
2307
2308 /*
2309 temp_U32 = l1tm.tmode_stats.angle_sum / count;
2310 value_unsigned_int = l1tm.tmode_stats.angle_sq_sum / count - (temp_U32)*(temp_U32);
2311 */
2312
2313
2314
2315
2316 }
2317 else value_unsigned_int = 0;
2318 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2319 offset+=4;
2320 }
2321 // angle minimum
2322 if (bitmask & ANGLE_MIN)
2323 {
2324 value_signed_int = l1tm.tmode_stats.angle_min;
2325 memcpy(&tm_return->result[offset], (UWORD8 *) &value_signed_int, 4);
2326 offset+=4;
2327 }
2328 // angle maximum
2329 if (bitmask & ANGLE_MAX)
2330 {
2331 value_signed_int = l1tm.tmode_stats.angle_max;
2332 memcpy(&tm_return->result[offset], (UWORD8 *) &value_signed_int, 4);
2333 offset+=4;
2334 }
2335 // SNR mean
2336 if (bitmask & SNR_MEAN)
2337 {
2338 if (count) // non-zero
2339 value_unsigned_int = (UWORD16)(l1tm.tmode_stats.snr_sum) / count; //omaps00090550
2340 else value_unsigned_int = 0;
2341 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2342 offset+=4;
2343 }
2344 // SNR variance
2345 if (bitmask & SNR_VAR)
2346 {
2347 if (count) // non-zero
2348 {
2349 UWORD32 u32dvsor ;
2350 temp_U32 = l1tm.tmode_stats.angle_sum;
2351 u32dvsor = (temp_U32 /(UWORD32)count);
2352 temp_U32= u32dvsor;
2353 u32dvsor *= (temp_U32);
2354 u32dvsor *= (temp_U32);
2355 value_unsigned_int = l1tm.tmode_stats.angle_sq_sum / (UWORD32)count - u32dvsor;
2356
2357 }
2358 else
2359 value_unsigned_int = 0;
2360 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2361 offset+=4;
2362 }
2363 // TOA mean
2364 if (bitmask & TOA_MEAN)
2365 {
2366 if (count) // non-zero
2367 value_unsigned_int = (UWORD16)(l1tm.tmode_stats.toa_sum) / count; //omaps00090550
2368 else value_unsigned_int = 0;
2369 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2370 offset+=4;
2371 }
2372 // TOA variance
2373 if (bitmask & TOA_VAR)
2374 {
2375 if (count) // non-zero
2376 {
2377 UWORD32 u32dvsor ;
2378 temp_U32 = l1tm.tmode_stats.angle_sum;
2379 u32dvsor = (temp_U32 /(UWORD32)count);
2380 temp_U32= u32dvsor;
2381 u32dvsor *= (temp_U32);
2382 u32dvsor *= (temp_U32);
2383 value_unsigned_int = l1tm.tmode_stats.angle_sq_sum / (UWORD32)count - u32dvsor;
2384
2385 }
2386 else value_unsigned_int = 0;
2387 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2388 offset+=4;
2389 }
2390 // Frame # mod 26*51
2391 if (bitmask & FRAME_NUMBER)
2392 {
2393 value_unsigned_int = l1s.actual_time.fn;
2394 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2395 offset+=4;
2396 }
2397 // Tot # of runs executed so far
2398 if (bitmask & RUNS)
2399 {
2400 memcpy(&tm_return->result[offset], (UWORD8 *) &runs, 4);
2401 offset+=4;
2402 }
2403 // Tot # of successes so far
2404 if (bitmask & SUCCESSES)
2405 {
2406 memcpy(&tm_return->result[offset], (UWORD8 *) &l1tm.tmode_stats.flag_count, 4);
2407 offset+=4;
2408 }
2409 // BSIC
2410 if (bitmask & BSIC)
2411 {
2412 value_unsigned_short = l1tm.tmode_stats.bsic;
2413 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_short, 2);
2414 offset+=2;
2415 }
2416
2417 #if L1_GPRS
2418 if (bitmask & BLER)
2419 {
2420 UWORD8 j;
2421 if (count) // non-zero
2422 {
2423 float bler, remain_part;
2424 UWORD8 int_part, bitmap_remain;
2425 int i;
2426
2427 //compute bler for each block
2428 for (j=0; j<4; j++)
2429 {
2430 bler = ((float) (l1tm.tmode_stats.bler_crc[j] * 100)) / ((float) l1tm.tmode_stats.bler_total_blocks);
2431
2432 //conversion from floating to fixed format
2433 int_part = (UWORD8) bler;
2434 remain_part = bler - (float) int_part;
2435 bitmap_remain = 0;
2436
2437 i=5;
2438 while (i >= 0)
2439 {
2440 bitmap_remain |= (UWORD8) (remain_part *2) << i;
2441 if (((UWORD8) (remain_part *2)) >= 1)
2442 remain_part = (remain_part * 2) - 1;
2443 else
2444 remain_part = (remain_part * 2);
2445 i--;
2446 }
2447
2448 // Reporting the percentage of blocks in error (F10.6)
2449 value_array_unsigned_short[j] = bitmap_remain | (int_part << 6);
2450 }
2451 }
2452 // Reporting a BLER of 100, if no computation has been done
2453 else
2454 {
2455 for (j=0; j<4; j++)
2456 value_array_unsigned_short[j] = 100 << 6;
2457 }
2458 memcpy(&tm_return->result[offset], (UWORD8 *) &value_array_unsigned_short[0], 8);
2459 offset+=8;
2460 }
2461 #endif
2462
2463
2464 #if (ETM_PROTOCOL == 1)
2465 tm_return->status = -ETM_OK;
2466 #else
2467 tm_return->status = E_OK;
2468 #endif
2469 break;
2470 }
2471 // Most recent receive burst stats
2472 case MOST_RECENT_RX_STATS:
2473 {
2474 // rxlev: RSSI SF12.4 eventually (F7.1 currently)
2475 if (bitmask & RSSI)
2476 {
2477 value_unsigned_short = l1tm.tmode_stats.rssi_recent;
2478 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_short, 2);
2479 offset+=2;
2480 }
2481 // pm: most recent DSP power measurement UF10.6
2482 if (bitmask & DSP_PM)
2483 {
2484 memcpy(&tm_return->result[offset], &l1tm.tmode_stats.pm_recent, 2);
2485 offset+=2;
2486 }
2487 // most recent ANGLE value
2488 if (bitmask & ANGLE_MEAN)
2489 {
2490 value_signed_int = l1tm.tmode_stats.angle_recent;
2491 memcpy(&tm_return->result[offset], (UWORD8 *) &value_signed_int, 4);
2492 offset+=4;
2493 }
2494 // doesn't make sense.
2495 if (bitmask & ANGLE_VAR)
2496 {
2497 }
2498 // doesn't make sense.
2499 if (bitmask & ANGLE_MIN)
2500 {
2501 }
2502 // doesn't make sense.
2503 if (bitmask & ANGLE_MAX)
2504 {
2505 }
2506 // most recent SNR value
2507 if (bitmask & SNR_MEAN)
2508 {
2509 value_unsigned_int = l1tm.tmode_stats.snr_recent;
2510 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2511 offset+=4;
2512 }
2513 // doesn't make sense.
2514 if (bitmask & SNR_VAR)
2515 {
2516 }
2517 // most recent TOA value
2518 if (bitmask & TOA_MEAN)
2519 {
2520 value_unsigned_int = l1tm.tmode_stats.toa_recent;
2521 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2522 offset+=4;
2523 }
2524 // doesn't make sense.
2525 if (bitmask & TOA_VAR)
2526 {
2527 }
2528 // Frame # mod 26*51
2529 if (bitmask & FRAME_NUMBER)
2530 {
2531 value_unsigned_int = l1s.actual_time.fn;
2532 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_int, 4);
2533 offset+=4;
2534 }
2535 // must be '1'
2536 if (bitmask & RUNS)
2537 {
2538 }
2539 // most recent Success flag
2540 if (bitmask & SUCCESSES)
2541 {
2542 memcpy(&tm_return->result[offset], (UWORD8 *)&l1tm.tmode_stats.flag_recent, 4);
2543 offset+=4;
2544 }
2545 // BSIC
2546 if (bitmask & BSIC)
2547 {
2548 value_unsigned_short = l1tm.tmode_stats.bsic;
2549 memcpy(&tm_return->result[offset], (UWORD8 *) &value_unsigned_short, 2);
2550 offset+=2;
2551 }
2552 #if (ETM_PROTOCOL == 1)
2553 tm_return->status = -ETM_OK;
2554 #else
2555 tm_return->status = E_OK;
2556 #endif
2557 break;
2558 }
2559 default:
2560 {
2561 #if (ETM_PROTOCOL == 1)
2562 tm_return->status = -ETM_INVAL;
2563 #else
2564 tm_return->status = E_BADINDEX;
2565 #endif
2566 break;
2567 }
2568 } // end switch
2569
2570 tm_return->size = offset;
2571 tm_return->index = 0; // don't include index in header
2572 }
2573
2574 /*-------------------------------------------------------*/
2575 /* l1tm_fill_burst() */
2576 /*-------------------------------------------------------*/
2577 /* */
2578 /* Description: Prepare bursts for transmission in case */
2579 /* ------------ of UL test */
2580 /* */
2581 /* Simulation of IQ Swap does the following mapping: */
2582 /* */
2583 /* 00 -> 01 */
2584 /* 01 -> 00 */
2585 /* 10 -> 11 */
2586 /* 11 -> 10 */
2587 /* */
2588 /*-------------------------------------------------------*/
2589 #if (L1_FF_MULTIBAND == 1)
2590 extern const WORD8 rf_subband2band[];
2591 #endif
2592 void l1tm_fill_burst (UWORD16 pattern, UWORD16 *TM_ul_data)
2593 {
2594 UWORD32 i;
2595 UWORD8 swap_iq, swap_flag;
2596 UWORD16 gb_front, gb_end, tb_front, tb_end, even_bits, odd_bits;
2597 #if (L1_FF_MULTIBAND == 1)
2598 UWORD8 physical_band_id;
2599 #endif
2600 UWORD8 tsc_bits_in_first_word;
2601 UWORD16 tsc_front_mask,tsc_end_mask;
2602 extern T_RF rf;
2603
2604 // training sequences list......
2605 UWORD32 tsc[8]=
2606 {
2607 0x00970897,
2608 0x00B778B7,
2609 0x010EE90E,
2610 0x011ED11E,
2611 0x006B906B,
2612 0x013AC13A,
2613 0x029F629F,
2614 0x03BC4BBC
2615 };
2616 #if (L1_FF_MULTIBAND == 0)
2617
2618 if(((l1_config.std.id == DUAL) || (l1_config.std.id == DUALEXT) || (l1_config.std.id == DUAL_US)) &&
2619 (l1_config.tmode.rf_params.tch_arfcn >= l1_config.std.first_radio_freq_band2))
2620 {
2621 swap_iq = l1_config.std.swap_iq_band2;
2622 }
2623 else
2624 {
2625 swap_iq = l1_config.std.swap_iq_band1;
2626 }
2627
2628 #else // L1_FF_MULTIBAND = 1 below
2629
2630 physical_band_id =
2631 rf_subband2band[rf_convert_rffreq_to_l1subband(l1_config.tmode.rf_params.tch_arfcn)];
2632
2633 swap_iq = rf_band[physical_band_id].swap_iq;
2634
2635 #endif // #if (L1_FF_MULTIBAND == 0) else
2636
2637 // Swap IQ definitions...
2638 // 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX
2639 if (swap_iq & 0x2)
2640 {
2641 swap_flag = 1;
2642 }
2643 else
2644 {
2645 swap_flag = 0;
2646 }
2647
2648 //===========================================
2649 // define uplink patterns
2650 //===========================================
2651 if (pattern == 0) // 0's
2652 pattern = 0x0000;
2653 else if (pattern == 1) // 1's
2654 pattern = 0xffff;
2655 else if (pattern == 2) // 01's
2656 pattern = 0x5555;
2657
2658 // first replicate pattern through all buffer
2659 if ((pattern == 3) || (pattern == 4))
2660 {
2661 // fill the uplink burst with PRBS1
2662 l1tm_PRBS1_generate(TM_ul_data);
2663 }
2664 else if ((pattern != 12) && (pattern != 13))
2665 {
2666 for (i=0;i<=15;i++)
2667 TM_ul_data[i] = (pattern << 6);
2668 }
2669
2670 //===========================================
2671 // create front-end guard and tail bits masks
2672 //===========================================
2673 // guard bits mask
2674 gb_front = 0xFFC0 << (10 - rf.tx.guard_bits); // max. of 10, min. of 2 guard bits allowed
2675
2676 // check if guard bits > 7
2677 if (rf.tx.guard_bits > 7)
2678 {
2679 // tail bits mask
2680 tb_front = ~((UWORD16)(0xE000 << (10 - rf.tx.guard_bits))) & 0xFFC0; // tail bits placed in TM_ul_data[1] //oamps00090550
2681 // add tail bits to uplink data
2682 TM_ul_data[1] = TM_ul_data[1] & tb_front;
2683 // add guard bits to uplink data
2684 TM_ul_data[0] = gb_front;
2685 }
2686 else
2687 {
2688 // tail bits mask
2689 tb_front = ~((UWORD16)(0xE000 >> rf.tx.guard_bits) )& 0xFFC0; // 3 tail bits
2690 // add tail bits to uplink data
2691 TM_ul_data[0] = (TM_ul_data[0] | gb_front) & tb_front;
2692 }
2693
2694 //===========================================
2695 // create back-end guard and tail bits masks
2696 //===========================================
2697 // guard bits mask
2698 gb_end = (0xFFC0 >> (10 - (12 - rf.tx.guard_bits))) & 0xFFC0; // max. of 10, min. of 2 guard bits allowed
2699
2700 // check if guard bits < 5
2701 if (rf.tx.guard_bits < 5)
2702 {
2703 //tail bits mask
2704 tb_end = ~(UWORD16)((0x01C0 >> (rf.tx.guard_bits - 2))) & 0xFFC0; // tail bits placed in TM_ul_data[14]
2705 // add tail bits to uplink data
2706 TM_ul_data[14] = TM_ul_data[14] & tb_end;
2707 // add guard bits to uplink data
2708 TM_ul_data[15] = gb_end;
2709 }
2710 else
2711 {
2712 // tail bits mask
2713 tb_end = ~(UWORD16)((0x01C0 << (12 - rf.tx.guard_bits))) & 0xFFC0; // 3 tail bits
2714 // add tail bits to uplink data
2715 TM_ul_data[15] = (TM_ul_data[15] | gb_end) & tb_end;
2716 }
2717
2718 //===========================================
2719 // Insert the training sequence pattern .The location of TSC bits will
2720 // vary according to the value of guard bits used.
2721 //===========================================
2722 if ((pattern == 13)||(pattern==3))
2723 {
2724 // TM_ul_data[6] = (TM_ul_data[6] & 0xFE00) | ( (UWORD8) ((tsc[l1_config.tmode.tx_params.tsc]>>24) << 6 ) ); // tsc bits 1-2
2725 // TM_ul_data[7] = (TM_ul_data[7] & 0x0000) | ( (UWORD8) ((tsc[l1_config.tmode.tx_params.tsc]>>14) << 6 ) ); // tsc bits 3-12
2726 // TM_ul_data[8] = (TM_ul_data[8] & 0x0000) | ( (UWORD8) ((tsc[l1_config.tmode.tx_params.tsc]>>4 ) << 6 ) ); // tsc bits 13-22
2727 // TM_ul_data[9] = (TM_ul_data[9] & 0x07C0) | ( (UWORD8) ((tsc[l1_config.tmode.tx_params.tsc]>>0 ) << 12) ); // tsc bits 23-26
2728
2729 if (rf.tx.guard_bits <4) // TSC will be in [6],[7],[8]
2730 {
2731 tsc_bits_in_first_word = 9-rf.tx.guard_bits; // 7 bits when guard is 2, 6 bit when guard is 3
2732 tsc_front_mask = ((0xFFC0) << tsc_bits_in_first_word); // insert zeros from right
2733 //tsc_bits_in_last_word = 26 -10 -tsc_bits_in_first_word = (16-tsc_bits_in_first_word)
2734 tsc_end_mask = (((0xFFC0) >> (16-tsc_bits_in_first_word)) & 0xFFC0); //insert zeros from left
2735
2736 TM_ul_data[6] = (TM_ul_data[6] & tsc_front_mask)
2737 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc]>>(26-tsc_bits_in_first_word)) << 6 )) & (~tsc_front_mask) );
2738 TM_ul_data[7] = (TM_ul_data[7] & 0x0000)
2739 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc]<<(tsc_bits_in_first_word+6))>>16)) & (0xFFC0)); //next 10 bits of TSC
2740 TM_ul_data[8] = (TM_ul_data[8] & tsc_end_mask)
2741 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc] << (tsc_bits_in_first_word+6+10))>>16) )& (~tsc_end_mask));
2742 }
2743 else if ((rf.tx.guard_bits >=4) && (rf.tx.guard_bits <9) )// TSC will be in [6],[7],[8],[9]
2744 {
2745 tsc_bits_in_first_word = 9-rf.tx.guard_bits; // 5 bits when guard is 4, 1 bit when guard is 8
2746 tsc_front_mask = ((0xFFC0) << tsc_bits_in_first_word); // insert zeros from right
2747 //tsc_bits_in_last_word = 26 -10 -10 -tsc_bits_in_first_word = (6-tsc_bits_in_first_word)
2748 tsc_end_mask = (((0xFFC0) >> (6-tsc_bits_in_first_word)) & 0xFFC0); //insert zeros from left
2749
2750 TM_ul_data[6] = (TM_ul_data[6] & tsc_front_mask)
2751 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc]>>(26-tsc_bits_in_first_word)) << 6 )) & (~tsc_front_mask) );
2752 TM_ul_data[7] = (TM_ul_data[7] & 0x0000)
2753 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc]<<(tsc_bits_in_first_word+6))>>16)) & (0xFFC0) ); //next 10 bits of TSC
2754 TM_ul_data[8] = (TM_ul_data[8] & 0x0000)
2755 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc]<<(tsc_bits_in_first_word+6+10))>>16)) & (0xFFC0) ); //next 10 bits of TSC
2756 TM_ul_data[9] = (TM_ul_data[9] & tsc_end_mask)
2757 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc] << (tsc_bits_in_first_word+6+10+10))>>16) ) & (~tsc_end_mask));
2758 }
2759 else //(rf.tx.guard_bits>=9) : TSC will be in [7],[8],[9],
2760 {
2761 tsc_bits_in_first_word = 19-rf.tx.guard_bits; // 10 bits when guard is 9, 9 bits when guard is 10
2762 tsc_front_mask = ((0xFFC0) << tsc_bits_in_first_word); // insert zeros from right
2763 //tsc_bits_in_last_word = 26 -10 -tsc_bits_in_first_word = (16-tsc_bits_in_first_word)
2764 tsc_end_mask = (((0xFFC0) >> (16-tsc_bits_in_first_word)) & 0xFFC0); //insert zeros from left
2765
2766 TM_ul_data[7] = (TM_ul_data[7] & tsc_front_mask)
2767 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc]>>(26-tsc_bits_in_first_word)) << 6 )) & (~tsc_front_mask) );
2768 TM_ul_data[8] = (TM_ul_data[8] & 0x0000)
2769 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc]<<(tsc_bits_in_first_word+6))>>16)) & (0xFFC0) ); //next 10 bits of TSC
2770 TM_ul_data[9] = (TM_ul_data[9] & tsc_end_mask)
2771 | ( ((UWORD16) ((tsc[l1_config.tmode.tx_params.tsc] << (tsc_bits_in_first_word+6+10))>>16)) & (~tsc_end_mask));
2772 }
2773 }
2774
2775 // swap uplink data if IQ swap
2776 if(swap_flag)
2777 {
2778 for (i=0;i<=15;i++)
2779 {
2780 even_bits = TM_ul_data[i] & 0xAA80; // keep bits in even positions
2781 odd_bits = ~(TM_ul_data[i]) & 0x5540; // keep and complement bits in odd positions
2782 TM_ul_data[i] = even_bits | odd_bits; // swapped uplink data
2783 }
2784 }
2785 }
2786
2787
2788
2789 void l1a_tmode_send_ul_msg(T_TM_RETURN *tm_ret)
2790 {
2791 tm_transmit(tm_ret);
2792 }
2793
2794 /*******************************************************************************
2795 *
2796 * void tm_receive(void *inbuf, int size)
2797 *
2798 * Purpose : Parses TestMode data and copies it directly into TESTMODE_PRIM.
2799 * It forwards primitive to L1, except in the case of tm_init() which
2800 * gets executed in the CST.
2801 *
2802 * Arguments: In : command
2803 * Out:
2804 *
2805 * Returns : void
2806 *
2807 ******************************************************************************/
2808
2809 void tm_receive(UWORD8 *inbuf, UWORD16 size)
2810 {
2811 UWORD8 cksum, cid, error = 0;
2812 BOOL msg_used=FALSE;
2813
2814 #if (ETM_PROTOCOL == 1)
2815 UWORD8 mid = 0;
2816 #endif
2817
2818 UWORD8 *pmsg;
2819 xSignalHeaderRec *msg;
2820
2821 msg = os_alloc_sig(sizeof(T_TESTMODE_PRIM));
2822 msg->SignalCode = TESTMODE_PRIM;
2823
2824 // pmsg will be used to fill up the TestMode primitive with th
2825 // data, in consecutive order according to the definition of T_TESTMODE_PRIM.
2826 pmsg = (UWORD8 *)((T_TESTMODE_PRIM *)(msg->SigP));
2827
2828 #if (ETM_PROTOCOL == 1) // Use of ETM protocol
2829 #if (OP_L1_STANDALONE == 1)
2830 // Check MID
2831 *pmsg++ = mid = *inbuf++;
2832 if ((mid != ETM_RF) && (mid != ETM_CORE)) // check if coming from ETM RF or ETM CORE DLL
2833 error = -ETM_PACKET;
2834 #elif (OP_L1_STANDALONE == 0)
2835 *pmsg++ = mid = ETM_RF;
2836 #endif
2837
2838 // Copy CID/FID
2839 *pmsg++ = cid = *inbuf++;
2840 #if (OP_L1_STANDALONE == 1)
2841 // Copy data payload size (size minus MID byte and checksum byte)
2842 size -= 2;
2843 #endif
2844 *pmsg++ = --size; // Size of TM payload -1 for cid/fid
2845
2846 // Validate data payload size: check if longer than size of testmode
2847 // primitive minus cid, str_len_in_bytes, and two holes FIXME: This is a
2848 // really bad way of doing it!
2849 if (size > sizeof(T_TESTMODE_PRIM) - 4)
2850 error = -ETM_PACKET;
2851
2852 // The CID have been received. The data that follows are part of a
2853 // unique struct within the union of T_TESTMODE_PRIM, so we now
2854 // need to align at a 32-bit word boundary.
2855 *pmsg++ = 0;
2856
2857 // In a SSA integration the cksum is done in the etm_receive function
2858 #if (OP_L1_STANDALONE == 1)
2859 if (!error)
2860 {
2861 cksum = mid;
2862 cksum ^= cid;
2863
2864 while (size--)
2865 {
2866 cksum ^= *inbuf;
2867 *pmsg++ = *inbuf++;
2868 }
2869 if (cksum != *inbuf)
2870 error = -ETM_PACKET;
2871 }
2872 #elif (OP_L1_STANDALONE == 0)
2873 // Copy payload without cid/fid
2874 while (size--)
2875 {
2876 *pmsg++ = *inbuf++;
2877 }
2878 #endif
2879
2880 // At this point, all the data have been parsed and copied into
2881 // the TestMode primitive. Now we send the primitive to L1.
2882 if (!error)
2883 {
2884 os_send_sig(msg, L1C1_QUEUE);
2885 msg_used=TRUE;
2886 }
2887 else
2888 {
2889 UWORD8 mymsg[4];
2890
2891 // on error, return short error message; cid, error, checksum
2892 mymsg[0] = mid;
2893 mymsg[1] = cid; // the payload fid
2894 mymsg[2] = error; // status
2895 mymsg[3] = cid ^ error; // checksum
2896
2897 #if (TRACE_TYPE==0) || (TRACE_TYPE==1) || (TRACE_TYPE==4) || (TRACE_TYPE==7)
2898 rvt_send_trace_cpy((T_RVT_BUFFER) mymsg,
2899 tm_trace_user_id,
2900 4,
2901 RVT_BINARY_FORMAT);
2902 #endif
2903 }
2904
2905 #else // end of (ETM_PROTOCOL ==1)
2906
2907 // Copy CID
2908 *pmsg++ = cid = *inbuf++;
2909 // Copy data payload size (size minus CID byte and checksum byte)
2910 size -= 2;
2911 *pmsg++ = size;
2912
2913 // Validate data payload size: check if longer than size of testmode
2914 // primitive minus cid, str_len_in_bytes, and two holes FIXME: This is a
2915 // really bad way of doing it!
2916 if (size > sizeof(T_TESTMODE_PRIM) - 4)
2917 error = E_PACKET;
2918
2919 // The CID have been received. The data that follows are part of a
2920 // unique struct within the union of T_TESTMODE_PRIM, so we now
2921 // need to align at a 32-bit word boundary.
2922 pmsg += 2;
2923
2924 if (!error)
2925 {
2926 cksum = cid;
2927 while (size--)
2928 {
2929 cksum ^= *inbuf;
2930 *pmsg++ = *inbuf++;
2931 }
2932 if (cksum != *inbuf)
2933 error = E_CHECKSUM;
2934 }
2935
2936 // At this point, all the data have been parsed and copied into
2937 // the TestMode primitive. Now we send the primitive to L1.
2938 if (!error)
2939 {
2940 os_send_sig(msg, L1C1_QUEUE);
2941 msg_used=TRUE;
2942 }
2943 else
2944 {
2945 UWORD8 mymsg[3];
2946 // on error, return short error message; error, cid/fid, checksum
2947 mymsg[0] = cid;
2948 mymsg[1] = error;
2949 mymsg[2] = cid ^ error; // checksum
2950
2951 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) || (TRACE_TYPE==7) || (TRACE_TYPE==0)
2952 rvt_send_trace_cpy((T_RVT_BUFFER) mymsg, tm_trace_user_id,3, RVT_BINARY_FORMAT);
2953 #endif
2954 }
2955
2956 #endif // end of (ETM_PROTOCOL ==0)
2957
2958 // if the message allocated is not sent to L1A, it has to be deallocated
2959 if(msg_used==FALSE)
2960 os_free_sig(msg);
2961 }
2962
2963 void tm_transmit(T_TM_RETURN *tm_ret)
2964 {
2965 UWORD8 size, cksum;
2966 UWORD8 *pbuf, *ptmret;
2967 UWORD8 buf[TM_PAYLOAD_UPLINK_SIZE_MAX + TM_UPLINK_PACKET_OVERHEAD];
2968
2969 pbuf = &buf[0];
2970
2971 // move the header
2972 #if (ETM_PROTOCOL == 1)
2973 *pbuf++ = tm_ret->mid;
2974 cksum = tm_ret->mid;
2975 *pbuf++ = tm_ret->status;
2976 cksum ^= tm_ret->status;
2977 *pbuf++ = tm_ret->cid;
2978 cksum ^= tm_ret->cid;
2979
2980 // Include index if not equal to zero, and if not an error
2981 // Exception: in TX_TEMPLATE_READ we always include the index.
2982 if ((tm_ret->status == -ETM_OK) &&
2983 (tm_ret->index || tm_ret->cid == TX_TEMPLATE_READ)){
2984 *pbuf++ = tm_ret->index;
2985 cksum ^= tm_ret->index;
2986 }
2987
2988 #else
2989 *pbuf++ = tm_ret->cid;
2990 *pbuf++ = tm_ret->status;
2991 cksum = tm_ret->cid ^ tm_ret->status;
2992
2993 // Include index if not equal to zero, and if not an error
2994 // Exception: in TX_TEMPLATE_READ we always include the index.
2995 if ((tm_ret->status == E_OK) &&
2996 (tm_ret->index || tm_ret->cid == TX_TEMPLATE_READ)){
2997 *pbuf++ = tm_ret->index;
2998 cksum ^= tm_ret->index;
2999 }
3000 #endif
3001
3002 ptmret = (UWORD8 *) &tm_ret->result[0];
3003 size = (((tm_ret->size) > TM_PAYLOAD_UPLINK_SIZE_MAX) ? TM_PAYLOAD_UPLINK_SIZE_MAX: (tm_ret->size));
3004 while (size--) {
3005 *pbuf++ = *ptmret;
3006 cksum ^= *ptmret++;
3007 }
3008
3009 // move the checksum and append it to buf
3010 *pbuf++ = cksum;
3011
3012 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) || (TRACE_TYPE==7) || (TRACE_TYPE==0)
3013 rvt_send_trace_cpy(buf, tm_trace_user_id, pbuf - buf, RVT_BINARY_FORMAT);
3014 #endif
3015 }
3016
3017
3018 #if ((L1_STEREOPATH == 1) && (CODE_VERSION == NOT_SIMULATION) && (OP_L1_STANDALONE == 1))
3019 /*******************************************************************************
3020 *
3021 * UWORD16 l1tm_stereopath_get_pattern(UWORD16 sampling_freq, UWORD16 sin_freq_left,UWORD16 sin_freq_right, UWORD8 data_type)
3022 *
3023 * Purpose : this function is use to get a complete period of a sinusoide depending on
3024 * the sinusoide freq (L+R), the sampling freq and the type of samples (S8,S16,S32)
3025 *
3026 * Arguments: sampling_freq : sampling frequency
3027 * sin_freq_left : frequency of the left channel sinusoide
3028 * sin_freq_right : frequency of the right channel sinusoide
3029 * data_type : type of samples
3030 *
3031 * Returns : number of elements in the pattern
3032 *
3033 ******************************************************************************/
3034
3035 UWORD16 l1tm_stereopath_get_pattern(UWORD16 sampling_freq, UWORD16 sin_freq_left,UWORD16 sin_freq_right, UWORD8 data_type)
3036 {
3037 float max_sin_period;
3038 float my_time;
3039 UWORD16 i;
3040
3041 // get the lowest frequency to get the biggest period
3042 if (sin_freq_left > sin_freq_right)
3043 {
3044 max_sin_period = 1 / (float) sin_freq_right;
3045 }
3046 else
3047 {
3048 max_sin_period = 1 / (float) sin_freq_left;
3049 }
3050
3051 my_time = 0;
3052 i = 0;
3053
3054 if (data_type == AUDIO_SP_DATA_S8)
3055 {
3056 WORD8* my_ptr;
3057
3058 // cast the steropath_pattern to a pointer on 8 bits samples
3059 my_ptr = (WORD8*) l1tm.stereopath.stereopath_pattern;
3060
3061 // fill the pattern while the biggest period is not reached
3062 while (my_time < max_sin_period)
3063 {
3064 my_ptr[i++] = 0x7F * sin(2*3.1416*my_time*sin_freq_left);
3065 my_ptr[i++] = 0x7F * sin(2*3.1416*my_time*sin_freq_right);
3066
3067 my_time = i/2/((float) sampling_freq);
3068 }
3069 }
3070 else // S16
3071 {
3072 WORD16* my_ptr;
3073
3074 // cast the steropath_pattern to a pointer on 16 bits samples
3075 my_ptr = (WORD16*) l1tm.stereopath.stereopath_pattern;
3076
3077 // fill the pattern while the biggest period is not reached
3078 while (my_time < max_sin_period)
3079 {
3080 my_ptr[i++] = 0x7FFF * sin(2*3.1416*my_time*sin_freq_left);
3081 my_ptr[i++] = 0x7FFF * sin(2*3.1416*my_time*sin_freq_right);
3082
3083 my_time = i/2/((float) sampling_freq);
3084 }
3085
3086 }
3087
3088 return (i);
3089
3090 }
3091
3092 /*******************************************************************************
3093 *
3094 * void l1tm_stereopath_fill_buffer(void* buffer_address)
3095 *
3096 * Purpose : this function is use to fill a buffer with a predefined pattern
3097 *
3098 * Arguments: buffer_address : address of the buffer to fill
3099 *
3100 * Returns : none
3101 *
3102 ******************************************************************************/
3103
3104 void l1tm_stereopath_fill_buffer(void* buffer_address)
3105 {
3106 static UWORD16 my_counter = 0;
3107 UWORD16 copied_samples;
3108
3109 UWORD16 i;
3110
3111
3112 if (l1a_l1s_com.stereopath_drv_task.parameters.data_type == AUDIO_SP_DATA_S8)
3113 {
3114 WORD8* start_address;
3115 WORD8* my_ptr;
3116
3117 // l1tm.stereopath.stereopath_buffer_number is a variable used to know which half of the buffer we have to fill
3118 if (l1tm.stereopath.stereopath_buffer_number == 0)
3119 {
3120 // first half
3121 start_address = (WORD8*) buffer_address;
3122 l1tm.stereopath.stereopath_buffer_number = 1;
3123 }
3124 else
3125 {
3126 // second half, add the frame number to get the half buffer address
3127 start_address = ((WORD8*) buffer_address) + l1a_l1s_com.stereopath_drv_task.parameters.frame_number;
3128 l1tm.stereopath.stereopath_buffer_number = 0;
3129 }
3130
3131 // copied_samples is the number of samples copied to the half buffer
3132 copied_samples = 0;
3133 // cast the steropath_pattern to a pointer on 8 bits samples
3134 my_ptr = (WORD8*) l1tm.stereopath.stereopath_pattern;
3135
3136 if (l1a_l1s_com.stereopath_drv_task.parameters.frame_number > l1tm.stereopath.stereopath_nb_samples)
3137 {
3138 // size of the half buffer to fill is bigger than the predefined pattern
3139 // start to fill the buffer with the end of the not complete previous pattern (from current_sample to the last one)
3140 memcpy(start_address,my_ptr+l1tm.stereopath.stereopath_current_sample,l1tm.stereopath.stereopath_nb_samples-l1tm.stereopath.stereopath_current_sample);
3141 copied_samples = l1tm.stereopath.stereopath_nb_samples-l1tm.stereopath.stereopath_current_sample;
3142
3143 // while there is still enough place in the buffer to copy a complete pattern ...
3144 while (copied_samples<l1a_l1s_com.stereopath_drv_task.parameters.frame_number-l1tm.stereopath.stereopath_nb_samples)
3145 {
3146 // ... copy a complete pattern
3147 memcpy(start_address+copied_samples,my_ptr,l1tm.stereopath.stereopath_nb_samples);
3148 copied_samples += l1tm.stereopath.stereopath_nb_samples;
3149 }
3150
3151 // fill the rest of the buffer with a part of the pattern
3152 memcpy(start_address+copied_samples,my_ptr,l1a_l1s_com.stereopath_drv_task.parameters.frame_number-copied_samples);
3153 // save the last pattern sample copied in the buffer for next time (to get a continuous sound)
3154 l1tm.stereopath.stereopath_current_sample = l1a_l1s_com.stereopath_drv_task.parameters.frame_number-copied_samples;
3155
3156 }
3157 else
3158 {
3159 // size of the half buffer to fill is smaller than the predefined pattern
3160 // fill the buffer with a part of the pattern
3161 memcpy(start_address,my_ptr+l1tm.stereopath.stereopath_current_sample,l1a_l1s_com.stereopath_drv_task.parameters.frame_number);
3162 // save the last pattern sample copied in the buffer for next time (to get a continuous sound)
3163 l1tm.stereopath.stereopath_current_sample += l1a_l1s_com.stereopath_drv_task.parameters.frame_number;
3164
3165 if (l1tm.stereopath.stereopath_current_sample > l1tm.stereopath.stereopath_nb_samples)
3166 {
3167 l1tm.stereopath.stereopath_current_sample -= l1tm.stereopath.stereopath_nb_samples;
3168 }
3169 }
3170 }
3171 else // S16
3172 {
3173 WORD16* start_address;
3174 WORD16* my_ptr;
3175
3176 // l1tm.stereopath.stereopath_buffer_number is a variable used to know which half of the buffer we have to fill
3177 if (l1tm.stereopath.stereopath_buffer_number == 0)
3178 {
3179 // first half
3180 start_address = (WORD16*) buffer_address;
3181 l1tm.stereopath.stereopath_buffer_number = 1;
3182 }
3183 else
3184 {
3185 // second half, add the frame number to get the half buffer address
3186 start_address = ((WORD16*) buffer_address) + l1a_l1s_com.stereopath_drv_task.parameters.frame_number;
3187 l1tm.stereopath.stereopath_buffer_number = 0;
3188 }
3189
3190 // copied_samples is the number of samples copied to the half buffer
3191 copied_samples = 0;
3192 // cast the steropath_pattern to a pointer on 16 bits samples
3193 my_ptr = (WORD16*) l1tm.stereopath.stereopath_pattern;
3194
3195 if (l1a_l1s_com.stereopath_drv_task.parameters.frame_number > l1tm.stereopath.stereopath_nb_samples)
3196 {
3197 // size of the half buffer to fill is bigger than the predefined pattern
3198 // start to fill the buffer with the end of the not complete previous pattern (from current_sample to the last one)
3199 memcpy(start_address, my_ptr+l1tm.stereopath.stereopath_current_sample,(l1tm.stereopath.stereopath_nb_samples-l1tm.stereopath.stereopath_current_sample)*2);
3200 copied_samples = l1tm.stereopath.stereopath_nb_samples-l1tm.stereopath.stereopath_current_sample;
3201
3202 // while there is still enough place in the buffer to copy a complete pattern ...
3203 while (copied_samples<l1a_l1s_com.stereopath_drv_task.parameters.frame_number-l1tm.stereopath.stereopath_nb_samples)
3204 {
3205 // ... copy a complete pattern
3206 memcpy(start_address+copied_samples,my_ptr,l1tm.stereopath.stereopath_nb_samples*2);
3207 copied_samples += l1tm.stereopath.stereopath_nb_samples;
3208 }
3209
3210 // fill the rest of the buffer with a part of the pattern
3211 memcpy(start_address+copied_samples,my_ptr,(l1a_l1s_com.stereopath_drv_task.parameters.frame_number-copied_samples)*2);
3212 // save the last pattern sample copied in the buffer for next time (to get a continuous sound)
3213 l1tm.stereopath.stereopath_current_sample = l1a_l1s_com.stereopath_drv_task.parameters.frame_number-copied_samples;
3214
3215 }
3216 else
3217 {
3218 // size of the half buffer to fill is smaller than the predefined pattern
3219 // fill the buffer with a part of the pattern
3220 memcpy(start_address,my_ptr+l1tm.stereopath.stereopath_current_sample,l1a_l1s_com.stereopath_drv_task.parameters.frame_number);
3221 l1tm.stereopath.stereopath_current_sample += l1a_l1s_com.stereopath_drv_task.parameters.frame_number;
3222
3223 // save the last pattern sample copied in the buffer for next time (to get a continuous sound)
3224 if (l1tm.stereopath.stereopath_current_sample > l1tm.stereopath.stereopath_nb_samples)
3225 {
3226 l1tm.stereopath.stereopath_current_sample -= l1tm.stereopath.stereopath_nb_samples;
3227 }
3228
3229 }
3230 }
3231 }
3232
3233 /*******************************************************************************
3234 *
3235 * void l1tm_stereopath_DMA_handler(SYS_UWORD16 dma_status)
3236 *
3237 * Purpose : this function is the stereopath DMA interrupt handler
3238 *
3239 * Arguments: dma_status : type of interrupt
3240 *
3241 * Returns : none
3242 *
3243 ******************************************************************************/
3244 void l1tm_stereopath_DMA_handler(SYS_UWORD16 dma_status)
3245 {
3246 // stereopath DMA handler, check which type of interrupt it is
3247 if (F_DMA_COMPARE_CHANNEL_IT_STATUS_BLOCK(dma_status))
3248 {
3249 l1tm.stereopath.stereopath_block++;
3250 // Block --> fill a new buffer
3251 l1tm_stereopath_fill_buffer((void*) l1a_l1s_com.stereopath_drv_task.parameters.source_buffer_address);
3252 }
3253 if (F_DMA_COMPARE_CHANNEL_IT_STATUS_HALF_BLOCK(dma_status))
3254 {
3255 l1tm.stereopath.stereopath_half_block++;
3256 // Half Block --> fill a new buffer
3257 l1tm_stereopath_fill_buffer((void*) l1a_l1s_com.stereopath_drv_task.parameters.source_buffer_address);
3258 }
3259 if (F_DMA_COMPARE_CHANNEL_IT_STATUS_TIME_OUT_SRC(dma_status))
3260 l1tm.stereopath.stereopath_source_timeout++;
3261 if (F_DMA_COMPARE_CHANNEL_IT_STATUS_TIME_OUT_DST(dma_status))
3262 l1tm.stereopath.stereopath_dest_timeout++;
3263 if (F_DMA_COMPARE_CHANNEL_IT_STATUS_DROP(dma_status))
3264 l1tm.stereopath.stereopath_drop++;
3265 if (F_DMA_COMPARE_CHANNEL_IT_STATUS_FRAME(dma_status))
3266 l1tm.stereopath.stereopath_frame++;
3267 }
3268 #endif
3269
3270
3271
3272 #if (CODE_VERSION != SIMULATION)
3273 void l1tm_tpu_table_write(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
3274 {
3275 Cust_tm_tpu_table_write(tm_return,
3276 prim->u.tm_table.index,
3277 prim->str_len_in_bytes - 1, // subtract 8-bit index
3278 prim->u.tm_table.table);
3279 }
3280
3281 void l1tm_tpu_table_read(T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
3282 {
3283 Cust_tm_tpu_table_read(tm_return, prim->u.tm_table.index);
3284 }
3285 #endif // (CODE_VERSION != SIMULATION)
3286
3287 #if (L1_TPU_DEV == 1)
3288 /*******************************************************************
3289 * l1tm_flexi_tpu_table_write
3290 *
3291 * DESCRIPTION: The function would be called by the switch case in the etm_rf.
3292 *******************************************************************/
3293 void l1tm_flexi_tpu_table_write(T_TESTMODE_PRIM * prim, T_TM_RETURN * tm_return)
3294 {
3295 Cust_tm_flexi_tpu_table_write(tm_return,
3296 prim->u.tm_table16.index,
3297 prim->str_len_in_bytes - 1, // subtract 8-bit index
3298 prim->u.tm_table16.table);
3299 }
3300
3301 /*******************************************************************
3302 * l1tm_flexi_tpu_table_read
3303 *
3304 * DESCRIPTION: The function would be called by the switch case in the etm_rf.
3305 *******************************************************************/
3306 void l1tm_flexi_tpu_table_read (T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
3307 {
3308 Cust_tm_flexi_tpu_table_read(tm_return, prim->u.tm_table16.index);
3309 }
3310
3311 //Flexi ABB Delays
3312 /*******************************************************************
3313 * l1tm_flexi_abb_write
3314 *
3315 * DESCRIPTION: The function would be called by the switch case in the etm_rf.
3316 *******************************************************************/
3317 void l1tm_flexi_abb_write(T_TESTMODE_PRIM * prim, T_TM_RETURN * tm_return)
3318 {
3319 Cust_tm_flexi_abb_write(tm_return,
3320 prim->u.tm_table16.index,
3321 prim->str_len_in_bytes - 1, // subtract 8-bit index
3322 prim->u.tm_table16.table);
3323 }
3324
3325 /*******************************************************************
3326 * l1tm_flexi_abb_read
3327 *
3328 * DESCRIPTION: The function would be called by the switch case in the etm_rf.
3329 *******************************************************************/
3330 void l1tm_flexi_abb_read (T_TESTMODE_PRIM *prim, T_TM_RETURN *tm_return)
3331 {
3332 Cust_tm_flexi_abb_read(tm_return, prim->u.tm_table16.index);
3333 }
3334
3335
3336
3337 #endif // Flexible TPU
3338
3339 /*------------------------------------------------------------------*/
3340 /* l1tm_PRBS1_generate() */
3341 /*------------------------------------------------------------------*/
3342 /* */
3343 /* Parameters : UWORD16 *TM_ul_data */
3344 /* ------------- */
3345 /* point to the uplink burts table to be filled */
3346 /* with the PRBS 1 of bits */
3347 /* */
3348 /* Return : Void */
3349 /* ------------- */
3350 /* */
3351 /* Description : */
3352 /* ------------- */
3353 /* This algorithm generates a Pseudo Random Bit Sequence */
3354 /* using a method called method "Primitive Polynomial Modulo 2" */
3355 /* For a sequence length of (2^15-1) we a polynomial of order 15 */
3356 /* is used, the coefficients are [ 15, 1, 0 ] */
3357 /* The basic idea is to generate the new bit by XORing all the */
3358 /* coefficients of the polynomial except coeff 0 */
3359 /* i.e newbit = ( B15 XOR B1 ) */
3360 /* The following notation must be used for the bit numbering: */
3361 /* _______________________________________________________ */
3362 /*|B16|B15|B14|B13|B12|B11|B10|B9|B8|B7|B6|B5|B4|B3|B2|B1| */
3363 /*------------------------------------------------------------------*/
3364 /* */
3365 /* each word of the uplink buffer needs to be filled by new 10 bits */
3366 /*------------------------------------------------------------------*/
3367 void l1tm_PRBS1_generate(UWORD16 *TM_ul_data)
3368 {
3369 #define B15_MASK 0x4000
3370 #define B1_MASK 0x0001
3371 #define MASK_16BITS 0xFFFF
3372
3373 UWORD16 newbit =0x0000;
3374 UWORD8 index ,word;
3375
3376 //generate 16 words to fill Uplink table
3377 for (word=0;word<16;word++)
3378 {
3379 // generate new 10 bits from the sequence
3380 for (index =0; index< 10;index++)
3381 {
3382 // generate new bit , using the "Primitive Polynomial Modulo 2 " method with coeff. ( 15, 1, 0 )
3383 //XOR bit 15 with bit 1.
3384 newbit = (((l1tm.tmode_prbs.prbs1_seed& B15_MASK)>>14)^(l1tm.tmode_prbs.prbs1_seed & B1_MASK));
3385 // insert new bit in the sequence.
3386 l1tm.tmode_prbs.prbs1_seed = (l1tm.tmode_prbs.prbs1_seed << 1) | newbit;
3387 }
3388 TM_ul_data[word]=(UWORD16)((l1tm.tmode_prbs.prbs1_seed&MASK_16BITS)<<6);
3389 }
3390 }
3391
3392 #endif // TESTMODE
3393
3394