# HG changeset patch # User Mychaela Falconia # Date 1506925246 0 # Node ID 1ddbcdc0c1d5bbf84d1edfcbf8a48e30f9687252 # Parent 38ef7d6a62777534a8f6b3d9b8ae3009cf56053b l1p_cmpl.c: direct compilation passes, intram still fails diff -r 38ef7d6a6277 -r 1ddbcdc0c1d5 chipsetsw/layer1/p_cfile/l1p_cmpl.c --- a/chipsetsw/layer1/p_cfile/l1p_cmpl.c Mon Oct 02 06:01:18 2017 +0000 +++ b/chipsetsw/layer1/p_cfile/l1p_cmpl.c Mon Oct 02 06:20:46 2017 +0000 @@ -128,11 +128,11 @@ #endif #if(RF_FAM == 61) - #include "l1_rf61.h" + #include "l1_rf61.h" + #include "tpudrv61.h" #endif #include "l1_ctl.h" -#include "tpudrv61.h" /*-------------------------------------------------------*/ /* Prototypes of external functions used in this file. */ @@ -154,7 +154,7 @@ ); #endif /* RF_FAM == 61*/ #else /* L1_MADC_ON == 1*/ -void l1dmacro_rx_nb (UWORD16 arfcn, UWORD8 csf_filter_choice); +void l1dmacro_rx_nb (UWORD16 arfcn); #endif /* L1_MADC_ON == 1*/ void l1dmacro_afc (UWORD16 afc_value, UWORD8 win_id); @@ -277,9 +277,9 @@ UWORD16 dco_algo_ctl_nb = 0; UWORD8 if_ctl = 0; UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS; + // By default we choose the hardware filter + UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; #endif - // By default we choose the hardware filter - UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; #if (NEW_SNR_THRESHOLD == 1) UWORD8 saic_flag=0; #endif /* NEW_SNR_THRESHOLD */ @@ -815,10 +815,12 @@ // 1 whenever L1A makes some changes to the task parameters. { UWORD16 radio_freq; - // By default we choose the hardware filter - UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; + #if (RF_FAM == 61) + // By default we choose the hardware filter + UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; + #endif #if (NEW_SNR_THRESHOLD == 1) - UWORD8 saic_flag=0; + UWORD8 saic_flag=0; #endif /* NEW_SNR_THRESHOLD */ // Traces and debug. // ****************** @@ -2277,13 +2279,13 @@ WORD8 agc; UWORD8 lna_off; UWORD8 adc_active = INACTIVE; - #if (RF_FAM == 61) - UWORD16 dco_algo_ctl_nb = 0; - UWORD8 if_ctl = 0; - UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS; - #endif - // By default we choose the hardware filter - UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; + #if (RF_FAM == 61) + UWORD16 dco_algo_ctl_nb = 0; + UWORD8 if_ctl = 0; + UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS; + // By default we choose the hardware filter + UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; + #endif #if (NEW_SNR_THRESHOLD == 1) UWORD8 saic_flag = 0; @@ -2431,9 +2433,9 @@ lna_off, l1s.tpu_offset, l1s.tpu_offset, - FALSE,adc_active, - csf_filter_choice + FALSE,adc_active #if (RF_FAM == 61) + ,csf_filter_choice ,if_ctl #endif #if (NEW_SNR_THRESHOLD == 1) @@ -2876,16 +2878,16 @@ UWORD32 dsp_task; UWORD8 tsc; UWORD8 serving_cell; -#if (RF_FAM == 61) - UWORD16 dco_algo_ctl_nb=0; - UWORD8 if_ctl = 0; - UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS; -#endif - // By default we choose the hardware filter - UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; -#if (NEW_SNR_THRESHOLD == 1) - UWORD8 saic_flag=0; -#endif /* NEW_SNR_THRESHOLD */ + #if (RF_FAM == 61) + UWORD16 dco_algo_ctl_nb=0; + UWORD8 if_ctl = 0; + UWORD8 if_threshold = C_IF_ZERO_LOW_THRESHOLD_GPRS; + // By default we choose the hardware filter + UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER; + #endif + #if (NEW_SNR_THRESHOLD == 1) + UWORD8 saic_flag=0; + #endif /* NEW_SNR_THRESHOLD */ static WORD32 new_tpu_offset; static BOOL change_synchro; @@ -3047,7 +3049,7 @@ ); // RX window for NB. #endif /* RF_FAM == 61*/ #else /* L1_MADC_ON == 1*/ - l1dmacro_rx_nb (rx_radio_freq, csf_filter_choice); // RX window for NB. + l1dmacro_rx_nb (rx_radio_freq); // RX window for NB. #endif if (task == PBCCHS) @@ -3253,14 +3255,14 @@ l1s.tpu_offset, 1, 1, - TRUE,INACTIVE, - L1_SAIC_HARDWARE_FILTER - #if(RF_FAM == 61) + TRUE,INACTIVE + #if(RF_FAM == 61) + ,L1_SAIC_HARDWARE_FILTER ,if_ctl - #endif - #if (NEW_SNR_THRESHOLD == 1) + #endif + #if (NEW_SNR_THRESHOLD == 1) ,saic_flag - #endif /* NEW_SNR_THRESHOLD */ + #endif /* NEW_SNR_THRESHOLD */ ); // Set "CTRL_RX" flag in the controle flag registers.