# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1484429616 0
# Node ID 24f094deabe33b4e191727bdbc43fdfc9cd64674
# Parent  aea3c25486769d8f0bfe2e18f32dcc2e0974d64d
l1tm_async.c: l1a_tmode() reconstructed

diff -r aea3c2548676 -r 24f094deabe3 chipsetsw/layer1/tm_cfile/l1tm_async.c
--- a/chipsetsw/layer1/tm_cfile/l1tm_async.c	Sat Jan 14 21:00:14 2017 +0000
+++ b/chipsetsw/layer1/tm_cfile/l1tm_async.c	Sat Jan 14 21:33:36 2017 +0000
@@ -249,6 +249,15 @@
 
     switch (prim->cid)
     {
+      case TM_INIT:
+        l1tm_initialize(prim, &tm_ret);
+        break;
+      case TM_MODE_SET:
+        l1tm_mode_set(prim, &tm_ret);
+        break;
+      case VERSION_GET:
+        l1tm_version_get(prim, &tm_ret);
+        break;
       case RF_ENABLE:
         l1tm_rf_enable(prim, &tm_ret);
         break;
@@ -291,6 +300,27 @@
       case TX_TEMPLATE_READ:
         l1tm_tx_template_read(prim, &tm_ret);
         break;
+      case MEM_WRITE:
+        l1tm_mem_write(prim, &tm_ret);
+        break;
+      case MEM_READ:
+        l1tm_mem_read(prim, &tm_ret);
+        break;
+      case CODEC_WRITE:
+        l1tm_codec_write(prim, &tm_ret);
+        break;
+      case CODEC_READ:
+        l1tm_codec_read(prim, &tm_ret);
+        break;
+      case MISC_PARAM_WRITE:
+        l1tm_misc_param_write(prim, &tm_ret);
+        break;
+      case MISC_PARAM_READ:
+        l1tm_misc_param_read(prim, &tm_ret);
+        break;
+      case MISC_ENABLE:
+        l1tm_misc_enable(prim, &tm_ret);
+        break;
       case SPECIAL_PARAM_WRITE:
         l1tm_special_param_write(prim, &tm_ret);
         break;
@@ -319,6 +349,9 @@
         l1tm_tpu_table_read(prim, &tm_ret);
         break;
     #endif
+      case TM_FFS:
+        l1tm_ffs(prim, &tm_ret);
+        break;
     #if(L1_TPU_DEV == 1)
       case FLEXI_TPU_TABLE_WRITE:
         l1tm_flexi_tpu_table_write(prim, &tm_ret);