# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1506969618 0
# Node ID a7f15f8a2d8b7e5e9a26931e40da09b8835ae001
# Parent  028db3dad23b0196e6ef0f223ba290aff4728577
l1p_cmpl.c: l1ps_ctrl_pdtch() reconstructed

diff -r 028db3dad23b -r a7f15f8a2d8b chipsetsw/layer1/p_cfile/l1p_cmpl.c
--- a/chipsetsw/layer1/p_cfile/l1p_cmpl.c	Mon Oct 02 07:59:47 2017 +0000
+++ b/chipsetsw/layer1/p_cfile/l1p_cmpl.c	Mon Oct 02 18:40:18 2017 +0000
@@ -893,8 +893,8 @@
       UWORD8 tx_group_id    = 0;
       BOOL   pwr_programmed = FALSE;
       UWORD8 bit_mask       = 0x80;
-      WORD8  agc =0;  //omaps00090550
-      UWORD8 lna_off=0;  //omaps00090550;
+      WORD8  agc;
+      UWORD8 lna_off;
       BOOL   rx_done_flag;
       BOOL   adc_done = FALSE;
       UWORD8 adc_active = INACTIVE;
@@ -1189,7 +1189,7 @@
           // TX load = l1_config.params.tx_nb_load_split
           // original value of TX load (RACH) replaced by TX NB to take into account TX_NB|PRACH with max. TA
           l1s.tpu_win = (l1_config.params.rx_synth_load_split) +
-                        (ts * BP_SPLIT) +
+                        ((UWORD16)ts * BP_SPLIT) +
                         l1_config.params.tx_nb_load_split;