FreeCalypso > hg > tcs211-l1-reconst
changeset 204:2d691e51d678
l1_cust.c: passes compilation
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Wed, 08 Jun 2016 05:59:55 +0000 |
| parents | 5dbf46894dab |
| children | 1f1b89a59cf6 |
| files | chipsetsw/layer1/cust0/l1_cust.c chipsetsw/layer1/cust0/l1_rf12.c |
| diffstat | 2 files changed, 60 insertions(+), 56 deletions(-) [+] |
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--- a/chipsetsw/layer1/cust0/l1_cust.c Wed Jun 08 05:31:00 2016 +0000 +++ b/chipsetsw/layer1/cust0/l1_cust.c Wed Jun 08 05:59:55 2016 +0000 @@ -25,6 +25,8 @@ #include "buzzer.h" #include "serialswitch.h" +#include "abb.h" + #if TESTMODE #include "l1tm_defty.h" #endif @@ -641,62 +643,64 @@ #endif #if (ANLG_FAM == 1) - l1_config.params.debug1 = C_DEBUG1; // Enable f_tx delay of 400000 cyc DEBUG - l1_config.params.afcctladd = abb[ABB_AFCCTLADD]; // Value at reset - l1_config.params.vbur = abb[ABB_VBUR]; // Uplink gain amp 0dB, Sidetone gain to mute - l1_config.params.vbdr = abb[ABB_VBDR]; // Downlink gain amp 0dB, Volume control 0 dB - l1_config.params.bbctl = abb[ABB_BBCTL]; // value at reset - l1_config.params.apcoff = abb[ABB_APCOFF]; // value at reset - l1_config.params.bulioff = abb[ABB_BULIOFF]; // value at reset - l1_config.params.bulqoff = abb[ABB_BULQOFF]; // value at reset - l1_config.params.dai_onoff = abb[ABB_DAI_ON_OFF]; // value at reset - l1_config.params.auxdac = abb[ABB_AUXDAC]; // value at reset - l1_config.params.vbcr = abb[ABB_VBCR]; // VULSWITCH=0, VDLAUX=1, VDLEAR=1 - l1_config.params.apcdel = abb[ABB_APCDEL]; // value at reset + l1_config.params.debug1 = C_DEBUG1; // Enable f_tx delay of 400000 cyc DEBUG + l1_config.params.afcctladd = abb[ABB_AFCCTLADD]; // Value at reset + l1_config.params.vbuctrl = abb[ABB_VBUCTRL]; // Uplink gain amp 0dB, Sidetone gain to mute + l1_config.params.vbdctrl = abb[ABB_VBDCTRL]; // Downlink gain amp 0dB, Volume control 0 dB + l1_config.params.bbctrl = abb[ABB_BBCTRL]; // value at reset + l1_config.params.apcoff = abb[ABB_APCOFF]; // value at reset + l1_config.params.bulioff = abb[ABB_BULIOFF]; // value at reset + l1_config.params.bulqoff = abb[ABB_BULQOFF]; // value at reset + l1_config.params.dai_onoff = abb[ABB_DAI_ON_OFF]; // value at reset + l1_config.params.auxdac = abb[ABB_AUXDAC]; // value at reset + l1_config.params.vbctrl = abb[ABB_VBCTRL]; // VULSWITCH=0, VDLAUX=1, VDLEAR=1 + l1_config.params.apcdel1 = abb[ABB_APCDEL1]; // value at reset #endif #if (ANLG_FAM == 2) - l1_config.params.debug1 = C_DEBUG1; // Enable f_tx delay of 400000 cyc DEBUG - l1_config.params.afcctladd = abb[ABB_AFCCTLADD]; // Value at reset - l1_config.params.vbur = abb[ABB_VBUR]; // Uplink gain amp 0dB, Sidetone gain to mute - l1_config.params.vbdr = abb[ABB_VBDR]; // Downlink gain amp 0dB, Volume control 0 dB - l1_config.params.bbctl = abb[ABB_BBCTL]; // value at reset - l1_config.params.bulgcal = abb[ABB_BULGCAL]; // value at reset - l1_config.params.apcoff = abb[ABB_APCOFF]; // value at reset - l1_config.params.bulioff = abb[ABB_BULIOFF]; // value at reset - l1_config.params.bulqoff = abb[ABB_BULQOFF]; // value at reset - l1_config.params.dai_onoff = abb[ABB_DAI_ON_OFF]; // value at reset - l1_config.params.auxdac = abb[ABB_AUXDAC]; // value at reset - l1_config.params.vbcr = abb[ABB_VBCR]; // VULSWITCH=0, VDLAUX=1, VDLEAR=1 - l1_config.params.vbcr2 = abb[ABB_VBCR2]; // MICBIASEL=0, VDLHSO=0, MICAUX=0 - l1_config.params.apcdel = abb[ABB_APCDEL]; // value at reset - l1_config.params.apcdel2 = abb[ABB_APCDEL2]; // value at reset - #endif + l1_config.params.debug1 = C_DEBUG1; // Enable f_tx delay of 400000 cyc DEBUG + l1_config.params.afcctladd = abb[ABB_AFCCTLADD]; // Value at reset + l1_config.params.vbuctrl = abb[ABB_VBUCTRL]; // Uplink gain amp 0dB, Sidetone gain to mute + l1_config.params.vbdctrl = abb[ABB_VBDCTRL]; // Downlink gain amp 0dB, Volume control 0 dB + l1_config.params.bbctrl = abb[ABB_BBCTRL]; // value at reset + l1_config.params.bulgcal = abb[ABB_BULGCAL]; // value at reset + l1_config.params.apcoff = abb[ABB_APCOFF]; // value at reset + l1_config.params.bulioff = abb[ABB_BULIOFF]; // value at reset + l1_config.params.bulqoff = abb[ABB_BULQOFF]; // value at reset + l1_config.params.dai_onoff = abb[ABB_DAI_ON_OFF]; // value at reset + l1_config.params.auxdac = abb[ABB_AUXDAC]; // value at reset + l1_config.params.vbctrl1 = abb[ABB_VBCTRL1]; // VULSWITCH=0, VDLAUX=1, VDLEAR=1 + l1_config.params.vbctrl2 = abb[ABB_VBCTRL2]; // MICBIASEL=0, VDLHSO=0, MICAUX=0 + l1_config.params.apcdel1 = abb[ABB_APCDEL1]; // value at reset + l1_config.params.apcdel2 = abb[ABB_APCDEL2]; // value at reset + #endif #if (ANLG_FAM == 3) - l1_config.params.debug1 = C_DEBUG1; // Enable f_tx delay of 400000 cyc DEBUG - l1_config.params.afcctladd = abb[ABB_AFCCTLADD]; // Value at reset - l1_config.params.vbur = abb[ABB_VBUR]; // Uplink gain amp 0dB, Sidetone gain to mute - l1_config.params.vbdr = abb[ABB_VBDR]; // Downlink gain amp 0dB, Volume control 0 dB - l1_config.params.bbctl = abb[ABB_BBCTL]; // value at reset - l1_config.params.bulgcal = abb[ABB_BULGCAL]; // value at reset + l1_config.params.debug1 = C_DEBUG1; // Enable f_tx delay of 400000 cyc DEBUG + l1_config.params.afcctladd = abb[ABB_AFCCTLADD]; // Value at reset + l1_config.params.vbuctrl = abb[ABB_VBUCTRL]; // Uplink gain amp 0dB, Sidetone gain to mute + l1_config.params.vbdctrl = abb[ABB_VBDCTRL]; // Downlink gain amp 0dB, Volume control 0 dB + l1_config.params.bbctrl = abb[ABB_BBCTRL]; // value at reset + l1_config.params.bulgcal = abb[ABB_BULGCAL]; // value at reset l1_config.params.apcoff = abb[ABB_APCOFF]; // X2 Slope 128 and APCSWP disabled l1_config.params.bulioff = abb[ABB_BULIOFF]; // value at reset l1_config.params.bulqoff = abb[ABB_BULQOFF]; // value at reset l1_config.params.dai_onoff = abb[ABB_DAI_ON_OFF]; // value at reset l1_config.params.auxdac = abb[ABB_AUXDAC]; // value at reset - l1_config.params.vbcr = abb[ABB_VBCR]; // VULSWITCH=0 - l1_config.params.vbcr2 = abb[ABB_VBCR2]; // MICBIASEL=0, VDLHSO=0, MICAUX=0 - l1_config.params.apcdel = abb[ABB_APCDEL]; // value at reset - l1_config.params.apcdel2 = abb[ABB_APCDEL2]; // value at reset + l1_config.params.vbctrl1 = abb[ABB_VBCTRL1]; // VULSWITCH=0 + l1_config.params.vbctrl2 = abb[ABB_VBCTRL2]; // MICBIASEL=0, VDLHSO=0, MICAUX=0 + l1_config.params.apcdel1 = abb[ABB_APCDEL1]; // value at reset + l1_config.params.apcdel2 = abb[ABB_APCDEL2]; // value at reset l1_config.params.vbpop = abb[ABB_VBPOP]; // HSOAUTO enabled l1_config.params.vau_delay_init = abb[ABB_VAUDINITD]; // 2 TDMA Frames between VDL "ON" and VDLHSO "ON" - l1_config.params.vaud_cfg = abb[ABB_VAUDCR]; // value at reset - l1_config.params.vauo_onoff = abb[ABB_VAUOCR]; // speech on AUX and EAR - l1_config.params.vaus_vol = abb[ABB_VAUSCR]; // value at reset + l1_config.params.vaud_cfg = abb[ABB_VAUDCTRL]; // value at reset + l1_config.params.vauo_onoff = abb[ABB_VAUOCTRL]; // speech on AUX and EAR + l1_config.params.vaus_vol = abb[ABB_VAUSCTRL]; // value at reset l1_config.params.vaud_pll = abb[ABB_VAUDPLL]; // value at reset #endif - - // global variable for access to deep sleep time - l1_config.params.sleep_time = 0; + + #if 0 /* present in MV100 version, but not in TCS211 */ + // global variable for access to deep sleep time + l1_config.params.sleep_time = 0; + #endif }
--- a/chipsetsw/layer1/cust0/l1_rf12.c Wed Jun 08 05:31:00 2016 +0000 +++ b/chipsetsw/layer1/cust0/l1_rf12.c Wed Jun 08 05:59:55 2016 +0000 @@ -1,13 +1,13 @@ #if (OP_L1_STANDALONE == 1) // Define the correct enumeration of PA. Consult tpudrv12.h for the enumeration. #if ((BOARD == 40) || (BOARD == 41) || (BOARD == 45)) // EvaRita + D-sample or EvaConso - #define PA 3 + #define RF_PA 3 #else - #define PA 0 + #define RF_PA 0 #endif #else #include "rf.cfg" -//#define PA 3 // Hitachi +//#define RF_PA 3 // Hitachi #endif T_RF rf = @@ -462,7 +462,7 @@ }, { //TX structure {// gsm900 T_LEVEL_TX -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi {550, 0, 0}, // 0 {550, 0, 0}, // 1 {550, 0, 0}, // 2 @@ -532,7 +532,7 @@ }, {// Channel Calibration Tables {// arfcn, tx_chan_cal -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi { 21, 128 }, // Calibration Table 0 { 41, 128 }, { 62, 128 }, @@ -585,7 +585,7 @@ } }, { // GSM Power Ramp Values -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi { {// Ramp-Up #0 profile - Power Level 5 0,0,6,0,11,7,1,0,0,11,0,26,23,22,16,5 @@ -807,7 +807,7 @@ }, { //TX structure {// dcs1800 T_LEVEL_TX -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi {720, 0, 0}, // 0 Highest power {637, 1, 0}, // 1 {570, 2, 0}, // 2 @@ -917,7 +917,7 @@ } }, { // DCS Power Ramp Values -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi { {// Ramp-Up #0 profile - Power Level 0 0,0,0,10,16,0,0,0,6,0,0,0,19,31,31,15 @@ -1148,7 +1148,7 @@ }, { //TX structure {// gsm850 T_LEVEL_TX -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi {560, 0, 0}, // 0 {560, 0, 0}, // 1 {560, 0, 0}, // 2 @@ -1259,7 +1259,7 @@ } }, { // gsm850 Power Ramp Values -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi { {// Ramp-Up #0 profile - Power Level 5 8,0,0,0,0,0,6,0, @@ -1513,7 +1513,7 @@ }, { //TX structure {// pcs1900 T_LEVEL_TX -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi {915, 0, 0}, // 0 Highest power {715, 1, 0}, // 1 {570, 2, 0}, // 2 @@ -1624,7 +1624,7 @@ } }, { // PCS Power Ramp Values -#if (PA == 3) // Hitachi +#if (RF_PA == 3) // Hitachi { {// Ramp-Up #0 profile - Power Level 0 0,0,0,0,6,2,0,1,