FreeCalypso > hg > tcs211-l1-reconst

changeset 202:47ac87c0bc1b

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l1_cust.c & l1_rf12.c: s/ANALOG/ANLG_FAM/
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 08 Jun 2016 05:25:23 +0000
parents fc26218d598a
children 5dbf46894dab
files chipsetsw/layer1/cust0/l1_cust.c chipsetsw/layer1/cust0/l1_rf12.c
diffstat 2 files changed, 9 insertions(+), 9 deletions(-) [+]
line wrap: on
line diff
--- a/chipsetsw/layer1/cust0/l1_cust.c	Wed Jun 08 05:22:55 2016 +0000
+++ b/chipsetsw/layer1/cust0/l1_cust.c	Wed Jun 08 05:25:23 2016 +0000
@@ -48,7 +48,7 @@
   #include "l1_ctl.h"
 #endif
 
-#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
   #include "spi_drv.h"
 #endif
 
@@ -640,7 +640,7 @@
     #endif
   #endif
 
-  #if (ANALOG == 1)
+  #if (ANLG_FAM == 1)
     l1_config.params.debug1           = C_DEBUG1;             // Enable f_tx delay of 400000 cyc DEBUG     
     l1_config.params.afcctladd        = abb[ABB_AFCCTLADD];	  // Value at reset              
     l1_config.params.vbur             = abb[ABB_VBUR];		  // Uplink gain amp 0dB, Sidetone gain to mute
@@ -654,7 +654,7 @@
     l1_config.params.vbcr             = abb[ABB_VBCR];		  // VULSWITCH=0, VDLAUX=1, VDLEAR=1
     l1_config.params.apcdel           = abb[ABB_APCDEL];	  // value at reset
   #endif
-  #if (ANALOG == 2)
+  #if (ANLG_FAM == 2)
     l1_config.params.debug1           = C_DEBUG1;             // Enable f_tx delay of 400000 cyc DEBUG      
     l1_config.params.afcctladd        = abb[ABB_AFCCTLADD];	  // Value at reset              
     l1_config.params.vbur             = abb[ABB_VBUR];		  // Uplink gain amp 0dB, Sidetone gain to mute
@@ -671,7 +671,7 @@
     l1_config.params.apcdel           = abb[ABB_APCDEL];	  // value at reset
     l1_config.params.apcdel2          = abb[ABB_APCDEL2];    // value at reset    
   #endif													 
-  #if (ANALOG == 3)
+  #if (ANLG_FAM == 3)
     l1_config.params.debug1           = C_DEBUG1;               // Enable f_tx delay of 400000 cyc DEBUG      
     l1_config.params.afcctladd        = abb[ABB_AFCCTLADD];     // Value at reset              
     l1_config.params.vbur             = abb[ABB_VBUR];          // Uplink gain amp 0dB, Sidetone gain to mute
@@ -831,7 +831,7 @@
   index_up   = rf_band[band].tx.levels[txpwr_ramp_up].ramp_index;
   index_down = rf_band[band].tx.levels[txpwr_ramp_down].ramp_index;
 
-  #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
+  #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
     for (j=0; j<16; j++)
     {
       a_ramp[j]=((rf_band[band].tx.ramp_tables[index_down].ramp_down[j])<<11) |
@@ -849,7 +849,7 @@
 /* Functionality :                                       */
 /*-------------------------------------------------------*/
 
-#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq)
 {  
 
--- a/chipsetsw/layer1/cust0/l1_rf12.c	Wed Jun 08 05:22:55 2016 +0000
+++ b/chipsetsw/layer1/cust0/l1_rf12.c	Wed Jun 08 05:25:23 2016 +0000
@@ -1843,7 +1843,7 @@
 /*------------------------------------------*/
 /* ABB Initialization words
 /*------------------------------------------*/
-#if (ANALOG == 1)
+#if (ANLG_FAM == 1)
   UWORD16 abb[ABB_TABLE_SIZE] =
   {
     C_AFCCTLADD,  // Value at reset
@@ -1858,7 +1858,7 @@
     C_VBCR,       // VULSWITCH=0, VDLAUX=1, VDLEAR=1
     C_APCDEL      // value at reset
 };
-#elif (ANALOG == 2)
+#elif (ANLG_FAM == 2)
   UWORD16 abb[ABB_TABLE_SIZE] =
   {
     C_AFCCTLADD,
@@ -1877,7 +1877,7 @@
     C_APCDEL2
   };
 
-#elif (ANALOG == 3)
+#elif (ANLG_FAM == 3)
   UWORD16 abb[ABB_TABLE_SIZE] =
   {
     C_AFCCTLADD,