--- a/chipsetsw/layer1/cfile/l1_init.c	Fri Apr 08 04:09:42 2016 +0000
+++ b/chipsetsw/layer1/cfile/l1_init.c	Fri Apr 08 04:42:08 2016 +0000
@@ -201,10 +201,13 @@
   #include "bspTwl3029_Aud_Map.h"
   #include "bspTwl3029_Madc.h"
 #endif
+
+#if (RF_FAM == 61)
 //OMAPS148175
 #include "l1_drp_if.h"
 #include "drp_main.h" 
-//
+#endif
+
 #if (ANLG_FAM == 11)
 #if (L1_MADC_ON == 1)
 extern BspTwl3029_MadcResults l1_madc_results;
@@ -239,7 +242,7 @@
    extern void l1_api_dump(void);
 #endif
 
-  #if (TRACE_TYPE==3)
+#if (TRACE_TYPE==3)
     void reset_stats();
 #endif // TRACE_TYPE
 
@@ -263,10 +266,6 @@
    extern void L1_trace_string(char *s);
 #endif
 
-#if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
-   extern void L1_trace_string(char *s);
-#endif
-
 #if (RF_FAM == 60 || RF_FAM == 61)
   extern const UWORD8  drp_ref_sw[] ;
 extern T_DRP_REGS_STR  *drp_regs;
@@ -356,7 +355,7 @@
 
     (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL;
 
-    #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
+    #if (DSP >= 33)
       l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
     #else
       l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
@@ -414,7 +413,7 @@
 
 #endif
 
-#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
+#if (DSP >= 33)
   // Initialize V42b variables
   l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0       = 0;
   l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1       = 0;
@@ -449,7 +448,7 @@
       // Initialize the poll response buffer to "no poll request"
       l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0]     = CS_NONE_TYPE;
     #else // L1_GPRS
-      #if ((DSP == 31) || (DSP == 32) || (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39))
+      #if (DSP >= 31)
         l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER;
       #endif
     #endif // L1_GPRS
@@ -475,14 +474,14 @@
       #endif // DSP
     #endif // DCO_ALGO
 
-    #if ((DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38)) || (DSP == 39)
+    #if (DSP >= 34)
       l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0;
       l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0;
       l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0;
       l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0;
     #endif
 
-    #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
+    #if (DSP >= 35)
       l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs      = 400; // thresh detection ONSET AFS
       l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs  = 150; // thresh detection SID_FIRST AFS
       l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs    = 450; // thresh detection RATSCCH AFS
@@ -522,7 +521,7 @@
     #endif
 
     #if (CHIPSET == 12) || (CHIPSET == 15)
-      #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
+      #if (DSP >= 35)
         l1s_dsp_com.dsp_ndb_ptr->d_cport_init  = 0;
       #endif
     #endif
@@ -586,15 +585,15 @@
 
   // Intialize the AFC
   #if (DSP == 38) || (DSP == 39)
-	#if (CODE_VERSION != SIMULATION)
-		l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS;
-	#endif
-  #endif
+    #if (CODE_VERSION != SIMULATION)
+      l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS;
+    #endif
 
-  #if (L1_DRP_IQ_SCALING == 1)
+    #if (L1_DRP_IQ_SCALING == 1)
       l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1;
-  #else
+    #else
       l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0;
+    #endif
   #endif
 
 }
@@ -702,7 +701,7 @@
 void l1_abb_power_on(void)
 {
   #if (CODE_VERSION != SIMULATION)
-      #if (CHIPSET == 12)
+      #if (CHIPSET != 15)
     T_SPI_DEV *Abb;
     T_SPI_DEV init_spi_device;
     UWORD16 Abb_Status;
@@ -778,7 +777,7 @@
       // APCDEL1 will be initialized on rach only ....
       dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
 
-      #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
+      #if (DSP >= 33)
         // To increase the robustness the IOTA register are reseted to 0
         // if OMEGA, NAUSICA is used
         dsp_ndb_ptr->d_bulgcal     = 0x0000;
@@ -949,8 +948,10 @@
   l1s.pw_mgr.modules_status    = 0;            // all clocks ON
   l1s.pw_mgr.paging_scheduled  = FALSE;
 
+#if 0	/* not present in TCS211 */
   // variable for afc bypass mode
   l1s.pw_mgr.afc_bypass_mode   = AFC_BYPASS_MODE;
+#endif
 
   // 32 Khz gauging ....
   l1s.pw_mgr.gaug_count        = 0;