FreeCalypso > hg > tcs211-l1-reconst
changeset 16:e4d6bb87f308
pdt_2091.mak regenerated to rebuild L1 core libs from source
| author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
|---|---|
| date | Wed, 21 Oct 2015 03:11:03 +0000 |
| parents | 6814a6bced4f |
| children | 7f42cf4bca79 |
| files | g23m/__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib g23m/__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib g23m/pdt_2091.mak g23m/system/busyb/deliverydefs/dlvcfg0.xml |
| diffstat | 4 files changed, 4844 insertions(+), 7 deletions(-) [+] |
line wrap: on
line diff
Binary file g23m/__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib has changed
Binary file g23m/__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib has changed
--- a/g23m/pdt_2091.mak Wed Oct 21 01:57:01 2015 +0000 +++ b/g23m/pdt_2091.mak Wed Oct 21 03:11:03 2015 +0000 @@ -1,10 +1,10 @@ ############################################### ## MAKEFILE FOR all ## DEFINED IN TARGETSET Entities -## X:/leo2moko-debug/g23m/system/busyb/unbusy_targetset.xml +## X:/tcs211-l1-reconst/g23m/system/busyb/unbusy_targetset.xml ## BASED ON CONFIGURATION dlv_leonardo_rev5_gprs 2091 ## USING TOOLSET Tools -## generated 6/1/15 6:41 AM +## generated 10/21/15 1:59 AM ## by BuSyB Version 1.2.0 ## for DTD Version 1.19 ############################################### @@ -24,6 +24,10 @@ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/cnf \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/gdi \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/drivers \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + ../chipsetsw/layer1/cfile \ + ../chipsetsw/layer1/p_cfile \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/riviera \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/atp \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/audio \ @@ -348,6 +352,82 @@ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/drivers/abb_core_inth.obj \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/drivers/niq32.obj \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/drivers_flash.lib \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_pwmgr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_afunc.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_trace.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_cmplx.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_stats.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_afunc.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_drive.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_back.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_abb.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_drive.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_back.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_baudot_functions.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_encoder.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_poly.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_receiver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_transmitter.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_interleaver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/m_sequence.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ucs_functions.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_deinterleaver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/fifo.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/init_interleaver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_afunc.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_apihisr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/tty_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_mms_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_sch_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/e2_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/speech_acoustic_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/gprs_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/patch_file36_10_dyn_dwl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/leadboot.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_afun.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_asyn.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_cmpl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_small.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib \ + ../chipsetsw/layer1/cfile/l1_cmplx_intram.c \ + ../chipsetsw/layer1/cfile/l1_sync_intram.c \ + ../chipsetsw/layer1/p_cfile/l1p_cmpl_intram.c \ + ../chipsetsw/layer1/p_cfile/l1p_sync_intram.c \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_drive.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_mfmgr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_ctl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/viterbi.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/wait_for_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/dl1_com.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_api_hisr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_ctl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_driv.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/macs.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_cmplx_intram.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_sync_intram.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_cmpl_intram.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_sync_intram.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/riviera/rvf_buffer.obj \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/riviera/rvf_msg.obj \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/riviera/rvf_task.obj \ @@ -532,6 +612,7 @@ ../gpf/tools/bin/rm.exe \ $(PATH_CC_1_22e)//ar470 \ $(PATH_CC_1_22e)//cl470 \ + ../chipsetsw/layer1/tools/gen_intram.pl \ system/busyb/tools/make_cmd.pl BSB_PATHES_ALL = NEXGEN_NGOS_INCLUDE nexgen/coreip/ngos \ @@ -834,7 +915,7 @@ RVTOOL_DIR ../chipsetsw/tools/RivieraTool \ G23_SRC_ACI_DTI_MNG condat/ms/src/aci_dti_mng \ OUT_BIN_MAPFILE __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/bin/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0.map \ - DRIVE_X ../../leo2moko-debug \ + DRIVE_X ../../tcs211-l1-reconst \ G23_SRC_SMI condat/ms/src/smi \ MS condat/ms \ OUT_LIB_MIC __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/mic \ @@ -1106,7 +1187,7 @@ L23_GDI_LIB_DLV 0 \ L23_CUST_LIB_DLV 0 \ GPF_LIB_DLV 1 \ - L1_LIB_DLV 1 \ + L1_LIB_DLV 0 \ L1_CUST_LIB_DLV 1 \ L1_TPU_LIB_DLV 1 \ INIT_LIB_DLV 1 \ @@ -1484,6 +1565,72 @@ ../chipsetsw/drivers/drv_core/abb/abb.c \ ../chipsetsw/drivers/drv_core/abb/abb_core_inth.c \ ../chipsetsw/drivers/drv_core/inth/niq32.c \ + ../chipsetsw/layer1/cfile/l1_pwmgr.c \ + ../chipsetsw/layer1/cfile/l1_afunc.c \ + ../chipsetsw/layer1/cfile/l1_trace.c \ + ../chipsetsw/layer1/cfile/l1_init.c \ + ../chipsetsw/layer1/cfile/l1_sync.c \ + ../chipsetsw/layer1/cfile/l1_cmplx.c \ + ../chipsetsw/layer1/tm_cfile/l1tm_async.c \ + ../chipsetsw/layer1/tm_cfile/l1tm_func.c \ + ../chipsetsw/layer1/tm_cfile/l1tm_stats.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_async.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_afunc.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_init.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_drive.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_back.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_abb.c \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_async.c \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_sync.c \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_func.c \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_drive.c \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_init.c \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_back.c \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_baudot_functions.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/conv_encoder.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/conv_poly.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/ctm_receiver.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/ctm_transmitter.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/diag_interleaver.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/m_sequence.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/ucs_functions.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/diag_deinterleaver.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/fifo.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/init_interleaver.c \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_afunc.c \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_async.c \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_init.c \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_sync.c \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_apihisr.c \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_func.c \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/tty_patch_file36_10.c \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/amr_mms_patch_file36_10.c \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/amr_sch_patch_file36_10.c \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/e2_patch_file36_10.c \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/speech_acoustic_patch_file36_10.c \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/gprs_patch_file36_10.c \ + ../chipsetsw/layer1/dsp1/patch_file36_10_dyn_dwl.c \ + ../chipsetsw/layer1/dsp1/leadboot.c \ + ../chipsetsw/layer1/p_cfile/l1p_afun.c \ + ../chipsetsw/layer1/p_cfile/l1p_asyn.c \ + ../chipsetsw/layer1/p_cfile/l1p_cmpl.c \ + ../chipsetsw/layer1/p_cfile/l1p_sync.c \ + ../chipsetsw/layer1/cfile/l1_small.c \ + ../chipsetsw/layer1/cfile/l1_async.c \ + ../chipsetsw/layer1/cfile/l1_func.c \ + ../chipsetsw/layer1/cfile/l1_drive.c \ + ../chipsetsw/layer1/cfile/l1_mfmgr.c \ + ../chipsetsw/layer1/cfile/l1_ctl.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_func.c \ + ../chipsetsw/layer1/audio_cfile/l1audio_sync.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/viterbi.c \ + ../chipsetsw/layer1/gtt_cfile/ctm/wait_for_sync.c \ + ../chipsetsw/layer1/dl1/dl1_com.c \ + ../chipsetsw/layer1/cfile/l1_api_hisr.c \ + ../chipsetsw/layer1/p_cfile/l1p_ctl.c \ + ../chipsetsw/layer1/p_cfile/l1p_func.c \ + ../chipsetsw/layer1/p_cfile/l1p_driv.c \ + ../chipsetsw/layer1/cmacs/macs.c \ ../chipsetsw/riviera/rvf/rvf_buffer.c \ ../chipsetsw/riviera/rvf/rvf_msg.c \ ../chipsetsw/riviera/rvf/rvf_task.c \ @@ -1621,9 +1768,7 @@ ../chipsetsw/system/template/gsm_ds_k5a3281.template \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/bootloader.lib \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/tpudrv.lib \ - __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib \ __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_custom_int.lib \ - __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib \ ../chipsetsw/os/nucleus/v1_22e/nucleus_int_ram_nodbg.lib \ ../chipsetsw/system/rtslib/v1_22e/rts16le_int_ram.lib \ ../gpf/LIB/osx_na7_db.lib \ @@ -23087,6 +23232,4690 @@ +# TargetName=l1_ext +# +# TargetType=obj +# TargetDir=__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ +# +# Using Tool: CC2 +# mode: One to One +# command: cc_ti +# modifier: n/a +# descr.: TI C/C++ Compiler +# exec.: $(PATH_CC_1_22e)//cl470 +# +# SOURCES: +# ../chipsetsw/layer1/cfile/l1_pwmgr.c +# ../chipsetsw/layer1/cfile/l1_afunc.c +# ../chipsetsw/layer1/cfile/l1_trace.c +# ../chipsetsw/layer1/cfile/l1_init.c +# ../chipsetsw/layer1/cfile/l1_sync.c +# ../chipsetsw/layer1/cfile/l1_cmplx.c +# ../chipsetsw/layer1/tm_cfile/l1tm_async.c +# ../chipsetsw/layer1/tm_cfile/l1tm_func.c +# ../chipsetsw/layer1/tm_cfile/l1tm_stats.c +# ../chipsetsw/layer1/audio_cfile/l1audio_async.c +# ../chipsetsw/layer1/audio_cfile/l1audio_afunc.c +# ../chipsetsw/layer1/audio_cfile/l1audio_init.c +# ../chipsetsw/layer1/audio_cfile/l1audio_drive.c +# ../chipsetsw/layer1/audio_cfile/l1audio_back.c +# ../chipsetsw/layer1/audio_cfile/l1audio_abb.c +# ../chipsetsw/layer1/gtt_cfile/l1gtt_async.c +# ../chipsetsw/layer1/gtt_cfile/l1gtt_sync.c +# ../chipsetsw/layer1/gtt_cfile/l1gtt_func.c +# ../chipsetsw/layer1/gtt_cfile/l1gtt_drive.c +# ../chipsetsw/layer1/gtt_cfile/l1gtt_init.c +# ../chipsetsw/layer1/gtt_cfile/l1gtt_back.c +# ../chipsetsw/layer1/gtt_cfile/l1gtt_baudot_functions.c +# ../chipsetsw/layer1/gtt_cfile/ctm/conv_encoder.c +# ../chipsetsw/layer1/gtt_cfile/ctm/conv_poly.c +# ../chipsetsw/layer1/gtt_cfile/ctm/ctm_receiver.c +# ../chipsetsw/layer1/gtt_cfile/ctm/ctm_transmitter.c +# ../chipsetsw/layer1/gtt_cfile/ctm/diag_interleaver.c +# ../chipsetsw/layer1/gtt_cfile/ctm/m_sequence.c +# ../chipsetsw/layer1/gtt_cfile/ctm/ucs_functions.c +# ../chipsetsw/layer1/gtt_cfile/ctm/diag_deinterleaver.c +# ../chipsetsw/layer1/gtt_cfile/ctm/fifo.c +# ../chipsetsw/layer1/gtt_cfile/ctm/init_interleaver.c +# ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_afunc.c +# ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_async.c +# ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_init.c +# ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_sync.c +# ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_apihisr.c +# ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_func.c +# ../chipsetsw/layer1/dsp1/Dyn_dwnld/tty_patch_file36_10.c +# ../chipsetsw/layer1/dsp1/Dyn_dwnld/amr_mms_patch_file36_10.c +# ../chipsetsw/layer1/dsp1/Dyn_dwnld/amr_sch_patch_file36_10.c +# ../chipsetsw/layer1/dsp1/Dyn_dwnld/e2_patch_file36_10.c +# ../chipsetsw/layer1/dsp1/Dyn_dwnld/speech_acoustic_patch_file36_10.c +# ../chipsetsw/layer1/dsp1/Dyn_dwnld/gprs_patch_file36_10.c +# ../chipsetsw/layer1/dsp1/patch_file36_10_dyn_dwl.c +# ../chipsetsw/layer1/dsp1/leadboot.c +# ../chipsetsw/layer1/p_cfile/l1p_afun.c +# ../chipsetsw/layer1/p_cfile/l1p_asyn.c +# ../chipsetsw/layer1/p_cfile/l1p_cmpl.c +# ../chipsetsw/layer1/p_cfile/l1p_sync.c +# +# RESULTS: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_pwmgr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_afunc.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_trace.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_cmplx.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_stats.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_afunc.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_drive.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_back.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_abb.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_drive.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_back.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_baudot_functions.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_encoder.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_poly.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_receiver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_transmitter.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_interleaver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/m_sequence.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ucs_functions.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_deinterleaver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/fifo.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/init_interleaver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_afunc.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_apihisr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/tty_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_mms_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_sch_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/e2_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/speech_acoustic_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/gprs_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/patch_file36_10_dyn_dwl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/leadboot.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_afun.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_asyn.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_cmpl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_sync.obj +# +# RULES: + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_pwmgr.obj: \ + ../chipsetsw/layer1/cfile/l1_pwmgr.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_afunc.obj: \ + ../chipsetsw/layer1/cfile/l1_afunc.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_trace.obj: \ + ../chipsetsw/layer1/cfile/l1_trace.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_init.obj: \ + ../chipsetsw/layer1/cfile/l1_init.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_sync.obj: \ + ../chipsetsw/layer1/cfile/l1_sync.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_cmplx.obj: \ + ../chipsetsw/layer1/cfile/l1_cmplx.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_async.obj: \ + ../chipsetsw/layer1/tm_cfile/l1tm_async.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_func.obj: \ + ../chipsetsw/layer1/tm_cfile/l1tm_func.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_stats.obj: \ + ../chipsetsw/layer1/tm_cfile/l1tm_stats.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_async.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_async.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_afunc.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_afunc.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_init.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_init.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_drive.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_drive.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_back.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_back.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_abb.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_abb.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_async.obj: \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_async.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_sync.obj: \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_sync.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_func.obj: \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_func.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_drive.obj: \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_drive.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_init.obj: \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_init.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_back.obj: \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_back.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_baudot_functions.obj: \ + ../chipsetsw/layer1/gtt_cfile/l1gtt_baudot_functions.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_encoder.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/conv_encoder.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_poly.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/conv_poly.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_receiver.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/ctm_receiver.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_transmitter.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/ctm_transmitter.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_interleaver.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/diag_interleaver.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/m_sequence.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/m_sequence.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ucs_functions.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/ucs_functions.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_deinterleaver.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/diag_deinterleaver.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/fifo.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/fifo.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/init_interleaver.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/init_interleaver.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_afunc.obj: \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_afunc.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_async.obj: \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_async.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_init.obj: \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_init.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_sync.obj: \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_sync.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_apihisr.obj: \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_apihisr.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_func.obj: \ + ../chipsetsw/layer1/dyn_dwl_cfile/l1_dyn_dwl_func.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/tty_patch_file36_10.obj: \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/tty_patch_file36_10.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_mms_patch_file36_10.obj: \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/amr_mms_patch_file36_10.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_sch_patch_file36_10.obj: \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/amr_sch_patch_file36_10.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/e2_patch_file36_10.obj: \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/e2_patch_file36_10.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/speech_acoustic_patch_file36_10.obj: \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/speech_acoustic_patch_file36_10.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/gprs_patch_file36_10.obj: \ + ../chipsetsw/layer1/dsp1/Dyn_dwnld/gprs_patch_file36_10.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/patch_file36_10_dyn_dwl.obj: \ + ../chipsetsw/layer1/dsp1/patch_file36_10_dyn_dwl.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/leadboot.obj: \ + ../chipsetsw/layer1/dsp1/leadboot.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_afun.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_afun.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_asyn.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_asyn.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_cmpl.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_cmpl.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_sync.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_sync.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + + +# TargetName=l1_ext +# +# TargetType=obj +# TargetDir=__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ +# +# Using Tool: CC2 +# mode: One to One +# command: cc_ti +# modifier: n/a +# descr.: TI C/C++ Compiler +# exec.: $(PATH_CC_1_22e)//cl470 +# +# SOURCES: +# ../chipsetsw/layer1/cfile/l1_small.c +# +# RESULTS: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_small.obj +# +# RULES: + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_small.obj: \ + ../chipsetsw/layer1/cfile/l1_small.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mw \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + + +# TargetName=l1_ext +# +# TargetType=obj +# TargetDir=__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ +# +# Using Tool: CC2 +# mode: One to One +# command: cc_ti +# modifier: n/a +# descr.: TI C/C++ Compiler +# exec.: $(PATH_CC_1_22e)//cl470 +# +# SOURCES: +# ../chipsetsw/layer1/cfile/l1_async.c +# +# RESULTS: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_async.obj +# +# RULES: + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_async.obj: \ + ../chipsetsw/layer1/cfile/l1_async.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -mw \ + -o1 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext \ + $< + + +# TargetName=l1_ext +# +# TargetType=lib +# TargetDir=__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/ +# +# Using Tool: AR2 +# mode: Single Run +# command: ar_ti +# modifier: n/a +# descr.: TI Archiver +# exec.: $(PATH_CC_1_22e)//ar470 r +# +# SOURCES: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_pwmgr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_afunc.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_trace.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_cmplx.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_stats.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_afunc.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_drive.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_back.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_abb.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_drive.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_back.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_baudot_functions.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_encoder.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_poly.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_receiver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_transmitter.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_interleaver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/m_sequence.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ucs_functions.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_deinterleaver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/fifo.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/init_interleaver.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_afunc.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_async.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_init.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_apihisr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/tty_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_mms_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_sch_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/e2_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/speech_acoustic_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/gprs_patch_file36_10.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/patch_file36_10_dyn_dwl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/leadboot.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_afun.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_asyn.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_cmpl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_small.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_async.obj +# +# RESULTS: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib +# +# RULES: + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib: \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_pwmgr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_afunc.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_trace.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_cmplx.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_stats.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_afunc.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_drive.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_back.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_abb.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_drive.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_back.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_baudot_functions.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_encoder.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_poly.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_receiver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_transmitter.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_interleaver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/m_sequence.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ucs_functions.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_deinterleaver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/fifo.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/init_interleaver.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_afunc.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_async.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_init.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_apihisr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/tty_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_mms_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_sch_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/e2_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/speech_acoustic_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/gprs_patch_file36_10.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/patch_file36_10_dyn_dwl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/leadboot.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_afun.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_asyn.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_cmpl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_small.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_async.obj + $(PATH_CC_1_22e)//ar470 r \ +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib \ + $^ + + +l1_ext: \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib + +clean_l1_ext: + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_ext.lib + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_pwmgr.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_afunc.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_trace.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_init.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_sync.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_cmplx.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_async.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_func.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1tm_stats.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_async.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_afunc.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_init.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_drive.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_back.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1audio_abb.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_async.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_sync.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_func.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_drive.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_init.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_back.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1gtt_baudot_functions.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_encoder.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/conv_poly.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_receiver.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ctm_transmitter.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_interleaver.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/m_sequence.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/ucs_functions.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/diag_deinterleaver.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/fifo.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/init_interleaver.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_afunc.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_async.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_init.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_sync.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_apihisr.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_dyn_dwl_func.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/tty_patch_file36_10.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_mms_patch_file36_10.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/amr_sch_patch_file36_10.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/e2_patch_file36_10.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/speech_acoustic_patch_file36_10.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/gprs_patch_file36_10.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/patch_file36_10_dyn_dwl.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/leadboot.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_afun.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_asyn.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_cmpl.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1p_sync.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_small.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_ext/l1_async.obj + + + +# TargetName=l1_cmplx_intram +# +# TargetType=c +# TargetDir=../chipsetsw/layer1/cfile/ +# +# Using Tool: GEN_INTRAM +# mode: Single Run +# command: gen_intram +# modifier: n/a +# descr.: TI Perl script to convert .c -> .intram +# exec.: perl ../chipsetsw/layer1/tools/gen_intram.pl +# +# SOURCES: +# ../chipsetsw/layer1/cfile/l1_cmplx.c +# +# RESULTS: +# ../chipsetsw/layer1/cfile/l1_cmplx_intram.c +# +# RULES: + +../chipsetsw/layer1/cfile/l1_cmplx_intram.c: \ + ../chipsetsw/layer1/cfile/l1_cmplx.c + perl ../chipsetsw/layer1/tools/gen_intram.pl \ + $< + + +l1_cmplx_intram: \ + ../chipsetsw/layer1/cfile/l1_cmplx_intram.c + +clean_l1_cmplx_intram: + $(BSB_REMOVE) ../chipsetsw/layer1/cfile/l1_cmplx_intram.c + + + +# TargetName=l1_sync_intram +# +# TargetType=c +# TargetDir=../chipsetsw/layer1/cfile/ +# +# Using Tool: GEN_INTRAM +# mode: Single Run +# command: gen_intram +# modifier: n/a +# descr.: TI Perl script to convert .c -> .intram +# exec.: perl ../chipsetsw/layer1/tools/gen_intram.pl +# +# SOURCES: +# ../chipsetsw/layer1/cfile/l1_sync.c +# +# RESULTS: +# ../chipsetsw/layer1/cfile/l1_sync_intram.c +# +# RULES: + +../chipsetsw/layer1/cfile/l1_sync_intram.c: \ + ../chipsetsw/layer1/cfile/l1_sync.c + perl ../chipsetsw/layer1/tools/gen_intram.pl \ + $< + + +l1_sync_intram: \ + ../chipsetsw/layer1/cfile/l1_sync_intram.c + +clean_l1_sync_intram: + $(BSB_REMOVE) ../chipsetsw/layer1/cfile/l1_sync_intram.c + + + +# TargetName=l1p_cmpl_intram +# +# TargetType=c +# TargetDir=../chipsetsw/layer1/p_cfile/ +# +# Using Tool: GEN_INTRAM +# mode: Single Run +# command: gen_intram +# modifier: n/a +# descr.: TI Perl script to convert .c -> .intram +# exec.: perl ../chipsetsw/layer1/tools/gen_intram.pl +# +# SOURCES: +# ../chipsetsw/layer1/p_cfile/l1p_cmpl.c +# +# RESULTS: +# ../chipsetsw/layer1/p_cfile/l1p_cmpl_intram.c +# +# RULES: + +../chipsetsw/layer1/p_cfile/l1p_cmpl_intram.c: \ + ../chipsetsw/layer1/p_cfile/l1p_cmpl.c + perl ../chipsetsw/layer1/tools/gen_intram.pl \ + $< + + +l1p_cmpl_intram: \ + ../chipsetsw/layer1/p_cfile/l1p_cmpl_intram.c + +clean_l1p_cmpl_intram: + $(BSB_REMOVE) ../chipsetsw/layer1/p_cfile/l1p_cmpl_intram.c + + + +# TargetName=l1p_sync_intram +# +# TargetType=c +# TargetDir=../chipsetsw/layer1/p_cfile/ +# +# Using Tool: GEN_INTRAM +# mode: Single Run +# command: gen_intram +# modifier: n/a +# descr.: TI Perl script to convert .c -> .intram +# exec.: perl ../chipsetsw/layer1/tools/gen_intram.pl +# +# SOURCES: +# ../chipsetsw/layer1/p_cfile/l1p_sync.c +# +# RESULTS: +# ../chipsetsw/layer1/p_cfile/l1p_sync_intram.c +# +# RULES: + +../chipsetsw/layer1/p_cfile/l1p_sync_intram.c: \ + ../chipsetsw/layer1/p_cfile/l1p_sync.c + perl ../chipsetsw/layer1/tools/gen_intram.pl \ + $< + + +l1p_sync_intram: \ + ../chipsetsw/layer1/p_cfile/l1p_sync_intram.c + +clean_l1p_sync_intram: + $(BSB_REMOVE) ../chipsetsw/layer1/p_cfile/l1p_sync_intram.c + + + +# TargetName=l1_int +# +# TargetType=obj +# TargetDir=__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/ +# +# Using Tool: CC2 +# mode: One to One +# command: cc_ti +# modifier: n/a +# descr.: TI C/C++ Compiler +# exec.: $(PATH_CC_1_22e)//cl470 +# +# SOURCES: +# ../chipsetsw/layer1/cfile/l1_func.c +# ../chipsetsw/layer1/cfile/l1_drive.c +# ../chipsetsw/layer1/cfile/l1_mfmgr.c +# ../chipsetsw/layer1/cfile/l1_ctl.c +# ../chipsetsw/layer1/audio_cfile/l1audio_func.c +# ../chipsetsw/layer1/audio_cfile/l1audio_sync.c +# ../chipsetsw/layer1/gtt_cfile/ctm/viterbi.c +# ../chipsetsw/layer1/gtt_cfile/ctm/wait_for_sync.c +# ../chipsetsw/layer1/dl1/dl1_com.c +# ../chipsetsw/layer1/cfile/l1_api_hisr.c +# ../chipsetsw/layer1/p_cfile/l1p_ctl.c +# ../chipsetsw/layer1/p_cfile/l1p_func.c +# ../chipsetsw/layer1/p_cfile/l1p_driv.c +# ../chipsetsw/layer1/cmacs/macs.c +# ../chipsetsw/layer1/cfile/l1_cmplx_intram.c +# ../chipsetsw/layer1/cfile/l1_sync_intram.c +# ../chipsetsw/layer1/p_cfile/l1p_cmpl_intram.c +# ../chipsetsw/layer1/p_cfile/l1p_sync_intram.c +# +# RESULTS: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_drive.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_mfmgr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_ctl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/viterbi.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/wait_for_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/dl1_com.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_api_hisr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_ctl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_driv.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/macs.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_cmplx_intram.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_sync_intram.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_cmpl_intram.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_sync_intram.obj +# +# RULES: + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_func.obj: \ + ../chipsetsw/layer1/cfile/l1_func.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_drive.obj: \ + ../chipsetsw/layer1/cfile/l1_drive.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_mfmgr.obj: \ + ../chipsetsw/layer1/cfile/l1_mfmgr.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_ctl.obj: \ + ../chipsetsw/layer1/cfile/l1_ctl.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_func.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_func.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_sync.obj: \ + ../chipsetsw/layer1/audio_cfile/l1audio_sync.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/viterbi.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/viterbi.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/wait_for_sync.obj: \ + ../chipsetsw/layer1/gtt_cfile/ctm/wait_for_sync.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/dl1_com.obj: \ + ../chipsetsw/layer1/dl1/dl1_com.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_api_hisr.obj: \ + ../chipsetsw/layer1/cfile/l1_api_hisr.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_ctl.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_ctl.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_func.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_func.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_driv.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_driv.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/macs.obj: \ + ../chipsetsw/layer1/cmacs/macs.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_cmplx_intram.obj: \ + ../chipsetsw/layer1/cfile/l1_cmplx_intram.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_sync_intram.obj: \ + ../chipsetsw/layer1/cfile/l1_sync_intram.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_cmpl_intram.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_cmpl_intram.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_sync_intram.obj: \ + ../chipsetsw/layer1/p_cfile/l1p_sync_intram.c + $(PATH_CC_1_22e)//cl470 \ + -g \ + -eoobj -me \ + -pw2 -q \ + -mt \ + -o \ + -mw \ + -DRV_TRACE_LEVEL_WARNING=2 \ + -DTOOL_CHOICE=0 \ + -D_TMS470 \ + -I$(PATH_CC_1_22e)/ \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/config \ + -I../chipsetsw/os/nucleus \ + -I__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0 \ + -I../gpf/FRAME/cust_os \ + -I../chipsetsw/system \ + -I../chipsetsw/drivers/drv_app \ + -I../chipsetsw/drivers/drv_app/buzzer \ + -I../chipsetsw/drivers/drv_app/ffs \ + -I../chipsetsw/drivers/drv_app/sim \ + -I../chipsetsw/drivers/drv_app/uart \ + -I../chipsetsw/riviera \ + -I../chipsetsw/riviera/rv \ + -I../chipsetsw/riviera/rvt \ + -I../chipsetsw/services \ + -I../chipsetsw/services/Audio \ + -I../chipsetsw/layer1/audio_cust0 \ + -I../chipsetsw/layer1/audio_include \ + -I../chipsetsw/layer1/cust0 \ + -I../chipsetsw/layer1/hmacs \ + -I../chipsetsw/layer1/include \ + -I../chipsetsw/layer1/p_include \ + -I../chipsetsw/layer1/tm_include \ + -I../chipsetsw/layer1/tm_cust0 \ + -I../chipsetsw/layer1/dyn_dwl_include \ + -I../chipsetsw/layer1/tpu_drivers/p_source0 \ + -I../chipsetsw/layer1/tpu_drivers/source0 \ + -I../chipsetsw/layer1/tpu_drivers/source \ + -I../chipsetsw/drivers/drv_core \ + -I../chipsetsw/drivers/drv_core/abb \ + -I../chipsetsw/drivers/drv_core/armio \ + -I../chipsetsw/drivers/drv_core/clkm \ + -I../chipsetsw/drivers/drv_core/conf \ + -I../chipsetsw/drivers/drv_core/dma \ + -I../chipsetsw/drivers/drv_core/dsp_dwnld \ + -I../chipsetsw/drivers/drv_core/inth \ + -I../chipsetsw/drivers/drv_core/memif \ + -I../chipsetsw/drivers/drv_core/rhea \ + -I../chipsetsw/drivers/drv_core/security \ + -I../chipsetsw/drivers/drv_core/spi \ + -I../chipsetsw/drivers/drv_core/timer \ + -I../chipsetsw/drivers/drv_core/uart \ + -I../chipsetsw/drivers/drv_core/ulpd \ + -fr__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int \ + $< + + +# TargetName=l1_int +# +# TargetType=lib +# TargetDir=__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/ +# +# Using Tool: AR2 +# mode: Single Run +# command: ar_ti +# modifier: n/a +# descr.: TI Archiver +# exec.: $(PATH_CC_1_22e)//ar470 r +# +# SOURCES: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_drive.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_mfmgr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_ctl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/viterbi.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/wait_for_sync.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/dl1_com.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_api_hisr.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_ctl.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_func.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_driv.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/macs.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_cmplx_intram.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_sync_intram.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_cmpl_intram.obj +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_sync_intram.obj +# +# RESULTS: +# __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib +# +# RULES: + +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib: \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_drive.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_mfmgr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_ctl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/viterbi.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/wait_for_sync.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/dl1_com.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_api_hisr.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_ctl.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_func.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_driv.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/macs.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_cmplx_intram.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_sync_intram.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_cmpl_intram.obj \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_sync_intram.obj + $(PATH_CC_1_22e)//ar470 r \ +__out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib \ + $^ + + +l1_int: \ + __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib + +clean_l1_int: + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/lib/l1_int.lib + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_func.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_drive.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_mfmgr.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_ctl.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_func.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1audio_sync.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/viterbi.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/wait_for_sync.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/dl1_com.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_api_hisr.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_ctl.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_func.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_driv.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/macs.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_cmplx_intram.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1_sync_intram.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_cmpl_intram.obj + $(BSB_REMOVE) __out__/gsm_ac_gp_fd_pu_em_cph_ds_vc_cal35_ri_36_amd8_ts0/obj/l1_int/l1p_sync_intram.obj + + + # TargetName=riviera_core_flash # # TargetType=obj @@ -31567,6 +36396,8 @@ clean_config_gprs_fl \ clean_gdi \ clean_drivers_flash \ + clean_l1_ext \ + clean_l1_int \ clean_riviera_core_flash \ clean_riviera_cust_flash \ clean_atp \ @@ -31648,6 +36479,12 @@ clean_config_gprs_fl \ clean_gdi \ clean_drivers_flash \ + clean_l1_ext \ + clean_l1_cmplx_intram \ + clean_l1_sync_intram \ + clean_l1p_cmpl_intram \ + clean_l1p_sync_intram \ + clean_l1_int \ clean_riviera_core_flash \ clean_riviera_cust_flash \ clean_atp \
--- a/g23m/system/busyb/deliverydefs/dlvcfg0.xml Wed Oct 21 01:57:01 2015 +0000 +++ b/g23m/system/busyb/deliverydefs/dlvcfg0.xml Wed Oct 21 03:11:03 2015 +0000 @@ -23,7 +23,7 @@ <property name="L23_GDI_LIB_DLV" value="0"/> <property name="L23_CUST_LIB_DLV" value="0"/> <property name="GPF_LIB_DLV" value="1"/> - <property name="L1_LIB_DLV" value="1"/> + <property name="L1_LIB_DLV" value="0"/> <property name="L1_CUST_LIB_DLV" value="1"/> <property name="L1_TPU_LIB_DLV" value="1"/> <property name="INIT_LIB_DLV" value="1"/>