changeset 57:ef8ab5a0fe8f

l1_cmplx.c: low-hanging fruit
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sun, 27 Mar 2016 06:37:24 +0000
parents b7046f3475b6
children fcdbd97411c4
files chipsetsw/layer1/cfile/l1_cmplx.c
diffstat 1 files changed, 6 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/chipsetsw/layer1/cfile/l1_cmplx.c	Sun Mar 27 06:27:29 2016 +0000
+++ b/chipsetsw/layer1/cfile/l1_cmplx.c	Sun Mar 27 06:37:24 2016 +0000
@@ -2313,7 +2313,9 @@
 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0))  // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START         // KEEP IN EXTERNAL MEM otherwise
 
+#if 0	/* FreeCalypso TCS211 reconstruction */
 UWORD32 qual_acc_idle1[2];
+#endif
 
 /*-------------------------------------------------------*/
 /* l1s_ctrl_snb_dl()                                     */
@@ -7543,6 +7545,7 @@
           toa_tab[burst_id] = toa;
   }
 
+#if 0	/* FreeCalypso TCS211 reconstruction */
 // added Enhanced RSSI
    if(l1s_dsp_com.dsp_ndb_ptr->a_cd[2] != 0xffff)
    {
@@ -7550,6 +7553,7 @@
         //RX Qual value reporting- total number of decoded bits
          qual_acc_idle1[1] += 1;
    }
+#endif
 
 #if (FF_L1_FAST_DECODING == 1)
     /* Perform the reporting if
@@ -11971,6 +11975,7 @@
 
 }
 
+#if (CHIPSET==15)
 /*-------------------------------------------------------*/
 /* l1s_reset_tx_ptr()                                    */
 /*-------------------------------------------------------*/
@@ -11985,7 +11990,6 @@
 
 void l1s_reset_tx_ptr(UWORD8 param1, UWORD8 param2)
 {
-#if (CHIPSET==15)
     volatile UWORD32 *ptr_drp_init32;
     ptr_drp_init32 = (UWORD32 *) (DRP_API_BASE_ADDRESS + DRP_REG_SRM_CW_ADDR); //0xFFFF1E00;
 
@@ -11994,6 +11998,5 @@
 
     // Reset the bit to zero as aslong as the bit is 1, pointers are in reset state
     (*ptr_drp_init32) = (*ptr_drp_init32)&(L1_DRP_TX_PTR_RESET_RESET);
-#endif
 }
-
+#endif