FreeCalypso > hg > tcs211-pirelli

annotate chipsetsw/services/Audio/audio_mode_i.h @ 34:a023d8a79d05 default tip

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Pirelli keypad mapping
author Space Falcon <falcon@ivan.Harhan.ORG>
date Wed, 09 Sep 2015 04:42:57 +0000
parents 509db1a7b7b8
children
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1 /****************************************************************************/
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2 /* */
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3 /* File Name: audio_mode_i.h */
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4 /* */
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5 /* Purpose: This file contains symbolic constant used for the audio mode */
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6 /* */
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7 /* Version 0.1 */
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8 /* */
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9 /* Date Modification */
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10 /* ------------------------------------ */
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11 /* 18 Jan 2002 Create */
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12 /* */
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13 /* Author Francois Mazard */
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14 /* */
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15 /* (C) Copyright 2001 by Texas Instruments Incorporated, All Rights Reserved*/
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16 /****************************************************************************/
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17
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18 #include "rv/rv_defined_swe.h"
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19 #ifdef RVM_AUDIO_MAIN_SWE
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20
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21 #ifndef __AUDIO_MODE_I_H_
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22 #define __AUDIO_MODE_I_H_
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23
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24 #ifdef __cplusplus
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25 extern "C"
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26 {
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27 #endif
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28
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29 #if (ANLG_FAM == 1)
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30 /* Register mapping for OMEGA, NAUSICA */
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31
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32 /* VBCR register */
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33 #define AUDIO_VBCR_VFBYP (0x0200)
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34 #define AUDIO_VBCR_VBDFAUXG (0x0100)
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35 #define AUDIO_VBCR_VSYNC (0x0080)
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36 #define AUDIO_VBCR_VCLKMODE (0x0040)
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37 #define AUDIO_VBCR_VALOOP (0x0020)
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38 #define AUDIO_VBCR_MICBIAS (0x0010)
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39 #define AUDIO_VBCR_VULSWITCH (0x0008)
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40 #define AUDIO_VBCR_VBUZ (0x0004)
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41 #define AUDIO_VBCR_VDLEAR (0x0002)
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42 #define AUDIO_VBCR_VDLAUX (0x0001)
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43
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44 /* VBUR */
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45 #define AUDIO_VBUR_DXEN (0x0200)
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46 #define AUDIO_VBUR_VDLST (0x000F)
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47 #define AUDIO_VBUR_VULPG (0x001F)
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48
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49 /* VBDR */
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50 #define AUDIO_VBDR_VDLPG (0x000F)
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51 #define AUDIO_VBDR_VOLCTL (0x000F)
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52 #endif
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53 #if (ANLG_FAM == 2)
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54 /* Register mapping for IOTA */
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55
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56 /* VBCR register */
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57 #define AUDIO_VBCR_VFBYP (0x0200)
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58 #define AUDIO_VBCR_VBDFAUXG (0x0100)
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59 #define AUDIO_VBCR_VSYNC (0x0080)
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60 #define AUDIO_VBCR_VCLKMODE (0x0040)
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61 #define AUDIO_VBCR_VALOOP (0x0020)
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62 #define AUDIO_VBCR_MICBIAS (0x0010)
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63 #define AUDIO_VBCR_VULSWITCH (0x0008)
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64 #define AUDIO_VBCR_VBUZ (0x0004)
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65 #define AUDIO_VBCR_VDLEAR (0x0002)
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66 #define AUDIO_VBCR_VDLAUX (0x0001)
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67
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68 /* VBCR2 */
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69 #define AUDIO_VBCR2_MICBIASEL (0x0001)
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70 #define AUDIO_VBCR2_VDLHSO (0x0002)
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71 #define AUDIO_VBCR2_MICNAUX (0x0004)
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72
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73 /* VBUR */
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74 #define AUDIO_VBUR_DXEN (0x0200)
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75 #define AUDIO_VBUR_VDLST (0x000F)
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76 #define AUDIO_VBUR_VULPG (0x001F)
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77
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78 /* VBDR */
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79 #define AUDIO_VBDR_VDLPG (0x000F)
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80 #define AUDIO_VBDR_VOLCTL (0x000F)
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81 #endif
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82 #if (ANLG_FAM == 3)
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83 /* Register mapping for SYREN */
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84
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85 /* VBCR register */
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86 #define AUDIO_VBCR_VFBYP (0x0200)
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87 #define AUDIO_VBCR_VBDFAUXG (0x0100)
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88 #define AUDIO_VBCR_VSYNC (0x0080)
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89 #define AUDIO_VBCR_VCLKMODE (0x0040)
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90 #define AUDIO_VBCR_VALOOP (0x0020)
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91 #define AUDIO_VBCR_MICBIAS (0x0010)
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92 #define AUDIO_VBCR_VULSWITCH (0x0008)
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93
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94 /* VBCR2 */
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95 #define AUDIO_VBCR2_MICBIASEL (0x0004)
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96
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97 /* VBUR */
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98 #define AUDIO_VBUR_DXEN (0x0200)
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99 #define AUDIO_VBUR_VDLST (0x01E0)
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100 #define AUDIO_VBUR_VULPG (0x001F)
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101
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102 /* VBDR */
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103 #define AUDIO_VBDR_VDLPG (0x000F)
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104 #define AUDIO_VBDR_VOLCTL (0x0070)
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105 #endif
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106
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107 #ifdef __cplusplus
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108 }
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109 #endif
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110
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111 #endif /* __AUDIO_MODE_I_H_ */
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112 #endif /* #ifdef RVM_AUDIO_MAIN_SWE */
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113
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114