comparison chipsetsw/layer1/p_include/l1p_cons.h @ 0:509db1a7b7b8

initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1P_CONS.H
4 *
5 * Filename l1p_cons.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 // TBF allocations...
11 #define DL_TBF 0
12 #define UL_TBF 1
13 #define BOTH_TBF 2
14 #define SINGLE_BLOCK_DL 3
15 #define SINGLE_BLOCK_UL 4
16 #define TWO_PHASE_ACCESS 5
17 #define NO_TBF 6
18
19 // MAC modes...
20 #define DYN_ALLOC 0
21 #define EXT_DYN_ALLOC 1
22 #define FIX_ALLOC_NO_HALF 2
23 #define FIX_ALLOC_HALF 3
24
25 // First task after the Idle frame...
26 #define RX_TASK 1
27 #define TX_TASK 2
28
29 // Status for interference measurement frame
30 #define ANY_IDLE_FRAME 0
31 #define PTCCH_FRAME 1
32 #define SEARCH_FRAME 2
33
34 // No measurement status
35 #define NO_MEAS 0x80
36
37 // Multislot bit of BBCTRL ABB register to set the multislot mode
38 #if (ANLG_FAM == 1)
39 #define B_MSLOT (0x40<<6)
40 #endif
41 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
42 #define B_MSLOT (0x20<<6)
43 #endif
44
45 //----------------------------------------
46 // LAYER 1 Asynchronous processes names...
47 //----------------------------------------
48 #define NBR_L1PA_PROCESSES 11
49
50 #define PI_SCP 0 // l1pa_idle_paging_process(msg)
51 #define TRANSFER 1 // l1pa_transfer_process(msg)
52 #define P_ACC 2 // l1pa_access_process(msg)
53 #define P_POLL 3 // l1pa_idle_packet_polling_process(msg)
54 #define SCPB 4 // l1pa_serving_cell_pbcch_read_process(msg)
55 #define CR_MEAS 5 // l1pa_cr_meas_process(msg)
56 #define TCR_MEAS 6 // l1pa_tcr_meas_process(msg)
57 #define PI_INT_MEAS 7 // l1pa_idle_interference_meas_process(msg)
58 #define PT_INT_MEAS 8 // l1pa_transfer_interference_meas_process(msg)
59 #define NCPB 9 // l1pa_neighbor_cell_pbcch_read_process(msg)
60 #define PI_SMSCB 10 // l1pa_idle_smscb_process(msg)
61
62 // Constants for PRACH
63 #define ACC_BURST_8 0
64 #define ACC_BURST_11 1
65
66 #define DYN_PRACH_ALLOC 1
67 #define FIX_PRACH_ALLOC 2
68
69 // DSP CS types (CHED)
70 //TABLE/ UL CS
71 #define CS_NONE_TYPE 0 //NAME/ No block
72 #define CS_AUTO_DETECT 1 //NAME/ N/A
73 #define CS1_TYPE_DATA 2 //NAME/ CS1
74 #define CS1_TYPE_POLL 3 //NAME/ Poll NB
75 #define CS2_TYPE 4 //NAME/ CS2
76 #define CS3_TYPE 5 //NAME/ CS3
77 #define CS4_TYPE 6 //NAME/ CS4
78 #define CS_PAB8_TYPE 7 //NAME/ PRACH 8bit
79 #define CS_PAB11_TYPE 8 //NAME/ PRACH 11bit
80 //END_TABLE/
81
82 // USF decoding for PRACH
83 #define USF_INVALID 0
84 #define USF_GOOD 1
85 #define USF_BAD 2
86 #define USF_FREE 7
87
88 // DSP tasks
89 #define DL_PDSP_TASK 2 // Downlink task (Normal burst or Prach).
90 #define UL_PDSP_TASK 2 // Uplink task (Normal burst or Prach).
91 #define PB_PDSP_TASK 3 // Power measurement Burst task.
92
93 // DSP tasks used in d_task_md
94 #define INTERF_DSP_TASK 100 // Interference measurements
95 #define INTERF1_DSP_TASK 101 // 1 Interference measurement
96 #define INTERF2_DSP_TASK 102 // 2 Interference measurement
97 #define INTERF3_DSP_TASK 103 // 3 Interference measurement
98 #define INTERF4_DSP_TASK 104 // 4 Interference measurement
99 #define INTERF5_DSP_TASK 105 // 5 Interference measurement
100 #define INTERF6_DSP_TASK 106 // 6 Interference measurement
101 #define INTERF7_DSP_TASK 107 // 7 Interference measurement
102 #define INTERF8_DSP_TASK 108 // 8 Interference measurement
103 #define PTCCHD_DSP_TASK 109 // PTCCH DL
104 #define PTCCHU_DSP_TASK 110 // PTCCH UL
105 #define PTCCHDU_DSP_TASK 111 // PTCCH DL and UL
106
107 //---------------------------------------------
108 // PTCCH activities
109 //---------------------------------------------
110 #define PTCCH_DL_BIT 0 // PTCCH DL bit position
111 #define PTCCH_UL_BIT 1 // PTCCH UL bit position
112
113 #define PTCCH_DL (TRUE_L << PTCCH_DL_BIT)
114 #define PTCCH_UL (TRUE_L << PTCCH_UL_BIT)
115
116 //---------------------------------------------
117 // SINGLE activities
118 //---------------------------------------------
119 #define ALL_SINGLE 0xFF
120 #define SINGLE_DL_BIT 0 // SINGLE DL bit position
121 #define SINGLE_UL_BIT 1 // SINGLE UL bit position
122
123 #define SINGLE_DL (TRUE_L << SINGLE_DL_BIT)
124 #define SINGLE_UL (TRUE_L << SINGLE_UL_BIT)
125
126 #define SINGLE_DL_MASK ALL_TASK ^ SINGLE_DL
127 #define SINGLE_UL_MASK ALL_TASK ^ SINGLE_UL
128
129 //---------------------------------------------
130 // Status for MPHP_SINGLE_BLOCK_CON
131 //---------------------------------------------
132 #define SINGLE_UL_DONE 0
133 #define SINGLE_STI_PASSED 1
134 #define SINGLE_NO_TA 2
135 #define SINGLE_DL_DONE 3
136
137
138 //---------------------------------------------
139 // MCU-DSP bit-field bit position definitions
140 //---------------------------------------------
141 // d_task_u_gprs...
142 #define B_ACCESS_PRACH 13
143 #define B_PTCCH_UL 14
144
145 // d_task_d_gprs...
146 #define B_PTCCH_DL 14
147
148 // d_sched_mode_gprs...
149 #define B_SWITCH 0 // Bit 0: switch to GPRS, Bit 1: switch to GSM.
150 #define B_MAC_MODE 2
151 #define B_RIF_RX_MODE 5
152
153 // a_ctrl_abb_gprs or d_ptcchu_ctrl_abb_gprs...
154 #define B_RAMP_GPRS 0
155 #define B_APCDEL2_GPRS 2
156 #define B_APCDEL1_GPRS 3
157 #define B_AFC_GPRS 4
158 #define B_RAMP_NB_GPRS 5
159 #define B_MS_RULE 8 // set an additionnal interrupt for the DSP
160
161 //---------------------------------------------
162 // LAYER 1 PACKET PERIODIC MEASUREMENT TASKS...
163 //---------------------------------------------
164 #define P_CRMS 0 // Packet Periodic Measurements task in Idle mode.
165 #define P_TCRMS 1 // Neighbour Measurement in Packet Transfer mode.
166
167 #define P_CRMS_MEAS (TRUE_L << P_CRMS) // Set Packet Periodic Measurements task
168 #define P_TCRMS_MEAS (TRUE_L << P_TCRMS) // Set Neighbour Measurement Packet Transfer task
169
170 #define P_CRMS_MEAS_MASK ALL_TASK ^ P_CRMS_MEAS // Mask Packet Periodic Measurement task
171 #define P_TCRMS_MEAS_MASK ALL_TASK ^ P_TCRMS_MEAS // Mask Neighbour Measurement Packet Transfer task
172
173 //--------------------------------------------
174 // Paging macro definition
175 //--------------------------------------------
176 //-- Paging States used for PPCH reading blocks
177 #define PPCH_POS_NOT_COMP 0
178 #define PPCH_POS_COMP 1
179
180 //-- Maximum Number of Packet Paging Blocks
181 #define MAX_NBR_PG_BLKS 11
182
183 //-- Paging Block index max
184 #define MAX_PG_BLKS_INDEX 10
185
186 //--------------------------------------------
187 // PBCCH macro definition
188 //--------------------------------------------
189 //-- Maximum Number of PBCCH Blocks
190 #define MAX_NBR_PB_BLKS 4
191
192 //-- PBCCH index max
193 #define MAX_PB_BLKS_INDEX 3
194
195 /*--------------------------------------------------------*/
196 /* Position of different blocs in a MF52. */
197 /*--------------------------------------------------------*/
198 #define PCCCH_0 0
199 #define PCCCH_1 4
200 #define PCCCH_2 8
201 #define PCCCH_3 13
202 #define PCCCH_4 17
203 #define PCCCH_5 21
204 #define PCCCH_6 26
205 #define PCCCH_7 30
206 #define PCCCH_8 34
207 #define PCCCH_9 39
208 #define PCCCH_10 43
209 #define PCCCH_11 47
210
211 //-- PBCCH block position
212 #define B0_POSITION 0L
213 #define B11_POSITION 47L
214
215 // Power measurement constants
216 // mode for power measurements
217 #define PACKET_IDLE 1
218 #define PACKET_TRANSFER 2
219 // number of meas
220 #define NB_MEAS_PACKET_IDLE 4 // Normal case 1RX + 3PW, if no RX=> 4PW
221
222 // TX burst types
223 #define TX_NB_BURST 0
224 #define TX_RA_BURST 1
225
226 // No power control packet transfer AGC algorithm phases
227 #define SEARCH 0
228 #define TRACK 1
229
230 /*--------------------------------------------------------*/
231 /* API addresses......................... */
232 /*--------------------------------------------------------*/
233 #define DSP_API_ADDRESS_BASE 0x00000800L //
234 #define ARM_API_ADDRESS_BASE 0xFFD00000L //
235
236 // Herebelow we define the MCU/DSP interface addresses as seen
237 // by the DSP (DSP address space) considering address 0 basis.
238
239 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
240 #define DSP_MAP_DB_W_PAGE_0_GPRS 0x00000050L //
241 #define DSP_MAP_DB_W_PAGE_1_GPRS 0x00000064L //
242 #define DSP_MAP_DB_R_PAGE_0_GPRS 0x00000078L //
243 #define DSP_MAP_DB_R_PAGE_1_GPRS 0x0000009CL //
244 #define DSP_MAP_NDB_ADR_GPRS 0x000001AEL //
245 #define DSP_MAP_PARAM_ADR_GPRS 0x00000480L //
246 #else
247 #define DSP_MAP_DB_W_PAGE_0_GPRS 0x000004ADL //
248 #define DSP_MAP_DB_W_PAGE_1_GPRS 0x000004C1L //
249 #define DSP_MAP_DB_R_PAGE_0_GPRS 0x000004D5L //
250 #define DSP_MAP_DB_R_PAGE_1_GPRS 0x000004F9L //
251 #define DSP_MAP_NDB_ADR_GPRS 0x00000056L //
252 #define DSP_MAP_PARAM_ADR_GPRS 0x000001F1L //
253 #endif
254
255 // Herebelow we define the MCU/DSP interface addresses as seen
256 // by the MCU (ARM address space) considering .
257
258 #define DB_W_PAGE_0_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_W_PAGE_0_GPRS * 2)) //
259 #define DB_W_PAGE_1_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_W_PAGE_1_GPRS * 2)) //
260 #define DB_R_PAGE_0_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_R_PAGE_0_GPRS * 2)) //
261 #define DB_R_PAGE_1_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_DB_R_PAGE_1_GPRS * 2)) //
262 #define NDB_ADR_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_NDB_ADR_GPRS * 2)) //
263 #define PARAM_ADR_GPRS (ARM_API_ADDRESS_BASE + (DSP_MAP_PARAM_ADR_GPRS * 2)) //