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comparison chipsetsw/system/template/gsm_ds_pirelli_flash.template @ 32:f6eaed5c5322

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crazy-supersize RVT pool - we were still getting some lost msgs on the GTA02
author Space Falcon <falcon@ivan.Harhan.ORG>
date Wed, 09 Sep 2015 03:56:15 +0000
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31:955d59353cf6 32:f6eaed5c5322
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 * This version of the linker script template has been concocted
9 * by Spacefalcon the Outlaw based on previous hacks.
10 */
11
12 -c /* Autoinitialize variables at runtime */
13
14 /*********************************/
15 /* SPECIFY THE SYSTEM MEMORY MAP */
16 /*********************************/
17
18 MEMORY
19 {
20 /* CS0: Flash 4 Mbytes ****************************************************/
21 /* Interrupt Vectors Table */
22 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
23
24 /* Boot Sector */
25 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
26
27 /* Magic Word for Calypso Boot ROM */
28 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
29
30 /* Program Memory */
31 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700
32 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004
33 P_MEM3 (RXI) : org = 0x00004704 len = 0x0037b8fc
34
35 /* FFS Area */
36 FFS_MEM (RX) : org = 0x02000000 len = 0x00800000
37 /**************************************************************************/
38
39 /* CS1: External SRAM 1 Mbytes ********************************************/
40 /* Data Memory */
41
42 /*
43 * Huge XRAM on the Pirelli: present it as two banks of 4 MiB each
44 */
45
46 D_MEM1 (RW) : org = 0x01000000 len = 0x00400000
47 D_MEM2 (RW) : org = 0x01400000 len = 0x00400000
48 /**************************************************************************/
49
50 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
51 /* Code & Variables Memory */
52 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
53 /**************************************************************************/
54 }
55
56 /***********************************************/
57 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
58 /***********************************************/
59
60 /*
61 * Since the bootloader directly calls the INT_Initialize() routine located
62 * in int.s, this int.s code must always be mapped at the same address
63 * (usually in the second flash sector). Its length is about 0x500 bytes.
64 * Then comes the code that need to be loaded into the internal RAM.
65 */
66
67 SECTIONS
68 {
69 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
70 .monitor : > B_MEM /* Monitor Constants & Code */
71 {
72 $(CONST_BOOT_LIB)
73 }
74
75 .inttext : {} > P_MEM1 /* int.s Code */
76
77 .bss_dar : > D_MEM1 /* DAR SWE Variables */
78 {
79 $(BSS_DAR_LIB)
80 }
81
82 /*
83 * The .bss section should not be split to ensure it is initialized to 0
84 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
85 * or in D_MEM2.
86 *
87 * Falcon's note for K5A3281: see the comments above where the memory
88 * regions are defined.
89 */
90
91 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
92 {
93 $(BSS_BOOT_LIB)
94 }
95
96 /*
97 * All .bss sections, which must be mapped in internal RAM must be
98 * grouped in order to initialized the corresponding memory to 0.
99 * This initialization is done in int.s file before calling the Nucleus
100 * routine.
101 */
102
103 GROUP
104 {
105 S_D_Mem /* Label of start address of .bss section in Int. RAM */
106 .DintMem
107 {
108
109 /*
110 * .bss sections of the application
111 */
112
113 $(BSS_LIBS)
114
115 }
116
117 API_HISR_stack : {}
118
119 E_D_Mem /* Label of end address of .bss section in Int. RAM */
120 } > S_MEM
121
122 /*
123 * .text and .const sections which must be mapped in internal RAM.
124 */
125
126 .ldfl : {} > P_MEM2 /* Used to know the start load address */
127 GROUP load = P_MEM3, run = S_MEM
128 {
129 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
130 .PIntMem
131 {
132 /*
133 * .text and .const sections of the application.
134 *
135 * The .veneer sections correspond exactly to .text:v&n sections
136 * implementing the veneer functions. The .text:v$n -> .veneer
137 * translation is performed by PTOOL software when PTOOL_OPTIONS
138 * environement variable is set to veneer_section.
139 */
140
141 $(CONST_LIBS)
142
143 }
144 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
145 }
146
147 /*
148 * The rest of the code is mapped in flash, however the trampolines
149 * load address should be consistent with .text.
150 */
151 COMMENT2START
152 `trampolines load = P_MEM3, run = S_MEM
153 COMMENT2END
154
155 .text : {} > P_MEM3 /* Code */
156
157 /*
158 * The rest of the constants is mapped in flash.
159 * The .cinit section should not be split.
160 */
161
162 .cinit : {} > P_MEM3 /* Initialization Tables */
163 .const : {} > P_MEM3 /* Constant Data */
164 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
165
166 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
167
168 .stackandheap : > D_MEM1 /* System Stacks, etc... */
169 {
170 /* Leave 20 32bit words for register pushes. */
171 . = align(8);
172 . += 20 * 4;
173
174 /* Stack for abort and/or undefined modes. */
175 exception_stack = .;
176
177 /* Leave 38 32bit words for state saving on exceptions. */
178 _xdump_buffer = .;
179 . += 38 * 4;
180 . = align(8);
181
182 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
183 stack_segment = .;
184 . += 0xB00;
185 }
186
187 .data : {} > D_MEM1 /* Initialized Data */
188 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
189
190 }