FreeCalypso > hg > ueda-linux

annotate ifctf-part-lib/geda-symbols/MC68302_PGA-2.trg @ 123:47873f218c37

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SIM_Socket_TI.fp added
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Jul 2020 20:16:04 +0000
parents cd92449fdb51
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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cd92449fdb51 initial import of ueda and ifctf-part-lib from ifctfvax CVS
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1 # This is the template file for creating symbols with tragesym
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2 # every line starting with '#' is a comment line.
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3
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4 [options]
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5 # rotate_labels rotates the pintext of top and bottom pins
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6 # wordswap swaps labels if the pin is on the right side an looks like this:
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7 # "PB1 (CLK)"
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8 wordswap=yes
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9 rotate_labels=no
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10 sort_labels=no
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11 generate_pinseq=no
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12 sym_width=3600
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13 pinwidthvertikal=400
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14 pinwidthhorizontal=400
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15
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16 [geda_attr]
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17 # name will be printed in the top of the symbol
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18 # if you have a device with slots, you'll have to use slot= and slotdef=
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19 # use comment= if there are special information you want to add
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20 version=20030525
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21 name=MC68302
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22 device=MC68302
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23 refdes=U?
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24 footprint=PGA132
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25 description=MC68302 IMP, peripherals (2 of 3)
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26 documentation=
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27 author=Michael Sokolov <msokolov@ivan.Harhan.ORG>
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28 numslots=0
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29 #slot=1
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30 #slotdef=1:
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31 #slotdef=2:
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32 #slotdef=3:
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33 #slotdef=4:
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34 comment=pinseq numbers are PQFP package pins
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35 #comment=
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36 #comment=
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37
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38 [pins]
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39 # tabseparated list of pin descriptions
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40 # pinnr is the physical number of the pin
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41 # seq is the pinseq= attribute, leave it blank if it doesn't matter
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42 # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
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43 # style can be (line,dot,clk,dotclk,none). none if only want to add a net
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44 # posit. can be (l,r,t,b) or empty for nets
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45 # net specifies the name of the Vcc or GND name
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46 # label represents the pinlabel.
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47 # negation lines can be added with _Q_
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48 # if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
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49 #-----------------------------------------------------
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50 #pinnr seq type style posit. net label
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51 #-----------------------------------------------------
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52 A13 52 in line r RxD1/L1RxD
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53 K11 80 out line r TxD1/L1TxD
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54 N13 82 io line r RCLK1/L1CLK
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55 L12 81 io line r TCLK1/L1SY0/SDS1
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56 C11 50 in line r _CD1_/L1SY1
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57 D10 51 in line r _CTS1_/L1GR
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58 K12 79 out line r _RTS1_/L1RQ/GCIDCL
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59 J11 76 out line r BRG1
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60 DUMMY1 1001 pas line r DUMMY1
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61 D9 53 io line r RxD2/PA0
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62 E10 54 io line r TxD2/PA1
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63 C12 55 io line r RCLK2/PA2
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64 D11 56 io line r TCLK2/PA3
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65 B13 58 io line r _CTS2_/PA4
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66 C13 59 io line r _RTS2_/PA5
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67 E11 60 io line r _CD2_/PA6
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68 E12 61 io line r BRG2/SDS2/PA7
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69 DUMMY2 1002 pas line r DUMMY2
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70 E13 63 io line r RxD3/PA8
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71 F11 64 io line r TxD3/PA9
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72 F12 65 io line r RCLK3/PA10
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73 F13 66 io line r TCLK3/PA11
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74 B12 49 in line r _CTS3_/SPRxD
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75 M13 78 out line r _RTS3_/SPTxD
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76 L13 77 io line r _CD3_/SPCLK
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77 G11 68 io line r BRG3/PA12
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78
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79 G12 69 io line l _DREQ_/PA13
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80 H13 70 io line l _DACK_/PA14
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81 H12 71 io line l _DONE_/PA15
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82 DUMMY3 1003 pas line l DUMMY3
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83 M5 108 io line l _IACK7_/PB0
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84 L5 109 io line l _IACK6_/PB1
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85 N3 110 io line l _IACK1_/PB2
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86 DUMMY4 1004 pas line l DUMMY4
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87 N2 111 io line l TIN1/PB3
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88 L4 113 io line l _TOUT1_/PB4
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89 M3 114 io line l TIN2/PB5
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90 M2 115 io line l _TOUT2_/PB6
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91 K5 117 io line l _WDOG_/PB7
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92 DUMMY5 1005 pas line l DUMMY5
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93 J4 118 io line l PB8
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94 K4 119 io line l PB9
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95 N1 120 io line l PB10
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96 L2 121 io line l PB11