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SIM_Socket_TI.fp added
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 05 Jul 2020 20:16:04 +0000
parents cd92449fdb51
children
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1 Welcome to uEDA, an EDA suite for UNIX!
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2 (for board level design)
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3
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4 The uEDA project has been inspired by gEDA (http://geda.seul.org/) and intends
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5 to do for the UNIX culture what gEDA has done for the GNU/Linux culture.
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6
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7 First a disclaimer is in order. Different people write Free Software based on
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8 different motivations. Like most Free Software written by Michael Sokolov,
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9 uEDA is based on the "scratching a personal itch" development model. In other
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10 words, I have written the software to satisfy my own internal need, and I
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11 don't really care if you like it or not. Please keep this observation in mind
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12 as you discover that it lacks some feature you need or want, or that its flow
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13 is not to your liking. I have written it to satisfy *my* needs. I could have
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14 written it for myself and never released it, but I believe in sharing and
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15 letting others have what I have (though whether they like it or not is not my
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16 concern). So there you have it.
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17
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18 uEDA has been written by a hard-core UNIX programmer (as in real UNIX in 4
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19 capitals running on Big Iron, not the cheap modern crap), and is designed to
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20 allow one to design hardware using not only a UNIX host environment, but also
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21 the intellectual creation flow model associated with the UNIX culture, one that
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22 revolves around the concepts of source code files, generated files and
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23 Makefiles. I won't explain these concepts here; if they are foreign to you,
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24 uEDA is not for you.
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25
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26 Note my choice of words: "the intellectual creation flow model" of the UNIX
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27 culture, rather than "the UNIX programming model". I fully acknowledge that
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28 hardware engineering is very different from SW eng, and uEDA does not try to
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29 "make hardware like software". However, the UNIX culture's intellectual
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30 creation flow model has already been extended many times to various intellectual
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31 products other than software. Consider for example an author writing a book in
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32 troff. The troff source files take the place of C source code, PostScript or
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33 other typesetter files for the print house take the place of the executable
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34 binary, and a Makefile is used to drive the flow. The author edits the book
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35 source files with vi and regenerates the generated files on each iteration by
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36 running 'make'. It isn't software, but the intellectual creation flow is
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37 virtually identical. uEDA applies the same model to hardware design.
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38
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39 So what is the source code for hardware, and what is the final product that
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40 should be generated by 'make all'? Well, the ultimate final product is the
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41 physical board which you can hold in your hand, but the most "final" product
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42 that can be made on a computer would be a set of gerber files for PCB
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43 fabrication, a bill of materials (BOM) for the purchasing or other procurement
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44 of parts, and a set of assembly instructions to be handed to the assembly line
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45 workers who populate the parts on the board. The starting source code would
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46 be the schematic design.
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47
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48 The ultimate UNIX-model EDA suite would thus be one that can generate all final
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49 manufacturing files from the schematic source code with a single 'make' command.
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50 uEDA is almost there, except for the layout step.
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51
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52 The problem is that even with the best EDA technology PCB layout still involves
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53 considerable human effort, and is thus not something that can be done by a batch
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54 program that works from stdin to stdout. Therefore, the PCB layout file is
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55 subject to human editing and is not just an intermediate file between schematics
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56 and gerbers like a .o file in the software compilation flow.
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57
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58 The uEDA solution is to view the job of designing a board as two separate
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59 intellectual creation jobs, each with its own UNIX-model Makefile-driven flow.
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60 These two jobs are the design and the layout. uEDA addresses the design. The
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61 uEDA suite does not really get involved in the layout, but is designed with the
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62 assumption that the layout will be done with the free & open source PCB program
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63 (http://pcb.sourceforge.net/). The two are connected by the "pre-layout" step
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64 described in prelayout.txt.
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65
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66 (Note that such separation of the design and layout jobs is additionally
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67 supported by the fact that in many engineering companies these jobs are done
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68 by different people.)
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69
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70 In the design phase addressed by uEDA, the source code is the set of schematic
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71 sources and the Master Component List (MCL), a human-edited text file documented
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72 in mcldoc.txt. The products that can be generated from these sources with a
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73 Makefile are:
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74
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75 * Printable schematics (PostScript or PDF) for documentation;
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76 * A set of "pre-layout materials" for handing to the PCB layout person;
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77 * Bill of Materials (BOM) in different formats for part procurement, for
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78 assembly and for quick reference.
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79
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80 In the layout phase the .pcb that is both read and written by the PCB GUI is the
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81 source code, and pcb can be invoked from the command line without the GUI to
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82 generate gerbers, PostScript prints of the layout and other product files from
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83 it; those generations can be codified in a Makefile, once again creating the
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84 traditional UNIX flow.
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85
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86 Design source code structure
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87
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88 The source code for a board design in uEDA consists of 3 major parts:
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89
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90 * Information about all components on the board;
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91 * Electrical interconnect information: how these components are interconnected
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92 with nets;
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93 * Graphical information used to construct PostScript prints of the schematic
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94 sheets.
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95
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96 The core philosophy of uEDA is that these 3 kinds of information should be kept
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97 as orthogonal as possible. Component information is stored in the Master
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98 Component List (MCL) documented in mcldoc.txt, whereas the interconnect and
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99 graphical schematic information is stored in the schematic sheets (.usch files)
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100 documented in uschemlang.txt. Although the electrical interconnect and
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101 graphical information are stored together, the uschem language is designed to
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102 provide a high degree of orthogonality between the two. Schematic sheets can
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103 be either graphical or non-graphical.
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104
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105 Further reading:
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106
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107 bom_model.txt Describes the uEDA approach to BOM handling
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108 drc.txt Describes the means for helping ensure a match between the
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109 actual electrical interconnect and the graphical representation
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110 graphsyms.txt Information about graphical symbols used on schematic sheets
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111 mcldoc.txt Master Component List document
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112 netlisting.txt Describes uEDA's handling of netlist information
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113 prelayout.txt Describes what I mean by "pre-layout"
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114 psfeatures.txt Describes the features available in the PostScript prints of
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115 schematic sheets made with uschem-print(1)
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116 uschemlang.txt uschem language document
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117 *.1 Man pages for all uEDA utilities