FreeCalypso > hg > ueda-linux

annotate ifctf-part-lib/geda-symbols/EPF10K30ATx144-power.trg @ 145:5e91200bf609

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netdiff: donl-pinreport utility written, compiles
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 15 Nov 2020 01:17:10 +0000
parents cd92449fdb51
children
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cd92449fdb51 initial import of ueda and ifctf-part-lib from ifctfvax CVS
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1 # This is the template file for creating symbols with tragesym
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2 # every line starting with '#' is a comment line.
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3
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4 [options]
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5 # rotate_labels rotates the pintext of top and bottom pins
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6 # wordswap swaps labels if the pin is on the right side an looks like this:
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7 # "PB1 (CLK)"
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8 wordswap=yes
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9 rotate_labels=no
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10 sort_labels=no
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11 generate_pinseq=yes
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12 sym_width=9000
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13 pinwidthvertikal=400
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14 pinwidthhorizontal=600
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15
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16 [geda_attr]
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17 # name will be printed in the top of the symbol
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18 # if you have a device with slots, you'll have to use slot= and slotdef=
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19 # use comment= if there are special information you want to add
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20 version=20030525
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21 name=EPF10K30ATx144
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22 device=EPF10K30ATx144
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23 refdes=U?
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24 footprint=QFP144
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25 description=EPF10K30ATx144 FPGA, power pins
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26 documentation=
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27 author=Michael Sokolov <msokolov@ivan.Harhan.ORG>
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28 numslots=0
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29 #slot=1
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30 #slotdef=1:
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31 #slotdef=2:
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32 #slotdef=3:
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33 #slotdef=4:
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34 #comment=
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35 #comment=
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36
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37 [pins]
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38 # tabseparated list of pin descriptions
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39 # pinnr is the physical number of the pin
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40 # seq is the pinseq= attribute, leave it blank if it doesn't matter
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41 # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
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42 # style can be (line,dot,clk,dotclk,none). none if only want to add a net
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43 # posit. can be (l,r,t,b) or empty for nets
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44 # net specifies the name of the Vcc or GND name
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45 # label represents the pinlabel.
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46 # negation lines can be added with _Q_
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47 # if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
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48 #-----------------------------------------------------
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49 #pinnr seq type style posit. net label
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50 #-----------------------------------------------------
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51 6 pwr line t VCCint
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52 25 pwr line t VCCint
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53 52 pwr line t VCCint
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54 53 pwr line t VCCint
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55 75 pwr line t VCCint
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56 93 pwr line t VCCint
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57 123 pwr line t VCCint
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58
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59 5 pwr line t VCCio
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60 24 pwr line t VCCio
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61 45 pwr line t VCCio
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62 61 pwr line t VCCio
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63 71 pwr line t VCCio
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64 94 pwr line t VCCio
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65 115 pwr line t VCCio
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66 134 pwr line t VCCio
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67
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68 16 pwr line b GNDint
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69 57 pwr line b GNDint
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70 58 pwr line b GNDint
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71 84 pwr line b GNDint
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72 103 pwr line b GNDint
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73 127 pwr line b GNDint
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74
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75 15 pwr line b GNDio
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76 40 pwr line b GNDio
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77 50 pwr line b GNDio
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78 66 pwr line b GNDio
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79 85 pwr line b GNDio
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80 104 pwr line b GNDio
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81 129 pwr line b GNDio
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82 139 pwr line b GNDio