FreeCalypso > hg > ueda-linux
annotate ueda/sverp/output.c @ 148:64d4abf63e1e
netdiff: donl-pindiff factored out of donl-netmatch
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 15 Nov 2020 04:11:01 +0000 |
parents | 7b4f78fcca08 |
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rev | line source |
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1 /* |
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2 * ueda-sverp netlist output |
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3 */ |
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4 |
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5 #include <stdio.h> |
4 | 6 #include <stdlib.h> |
7 #include <string.h> | |
0
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8 #include <strings.h> |
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9 #include "struct.h" |
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10 |
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11 extern struct output_net *output_net_head; |
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12 extern struct output_element *output_element_head; |
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13 extern int total_good_nets, total_singular_nets, total_null_nets; |
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14 extern int total_output_elements; |
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15 extern char *output_filename; |
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16 |
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17 static FILE *outF; |
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18 static int net_comment_column; |
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19 |
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20 static void |
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21 find_net_comment_column() |
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22 { |
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23 register struct output_net *net; |
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24 register int len, maxlen; |
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25 |
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26 maxlen = 0; |
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27 for (net = output_net_head; net; net = net->next) { |
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28 if (net->npoints < 2) |
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29 continue; |
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30 len = strlen(net->name); |
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31 if (len > maxlen) |
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32 maxlen = len; |
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33 } |
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34 maxlen += 4; |
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35 do |
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36 maxlen++; |
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37 while (maxlen % 8); |
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38 net_comment_column = maxlen; |
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39 } |
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40 |
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41 static void |
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42 emit_good_nets() |
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43 { |
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44 register struct output_net *net; |
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45 register int col; |
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46 |
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47 fprintf(outF, "\n# Elaborated net wires (%d total):\n#\n", |
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48 total_good_nets); |
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49 for (net = output_net_head; net; net = net->next) { |
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50 if (net->npoints < 2) |
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51 continue; |
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52 fprintf(outF, "NET %s", net->name); |
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53 col = 4 + strlen(net->name); |
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54 do { |
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55 fputc('\t', outF); |
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56 col += 8; |
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57 col &= ~7; |
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58 } while (col < net_comment_column); |
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59 fprintf(outF, "# %d points\n", net->npoints); |
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60 } |
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61 } |
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62 |
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63 static void |
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64 emit_singular_nets() |
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65 { |
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66 register struct output_net *net; |
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67 |
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68 fprintf(outF, |
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69 "\n# Singular nets converted into no-connects (%d total):\n#\n", |
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70 total_singular_nets); |
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71 for (net = output_net_head; net; net = net->next) { |
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72 if (net->npoints != 1) |
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73 continue; |
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74 fprintf(outF, "# %s\n", net->name); |
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75 } |
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76 } |
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77 |
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78 static void |
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79 emit_null_nets() |
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80 { |
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81 register struct output_net *net; |
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82 |
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83 fprintf(outF, "\n# Net wires declared but not used (%d total):\n#\n", |
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84 total_null_nets); |
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85 for (net = output_net_head; net; net = net->next) { |
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86 if (net->npoints) |
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87 continue; |
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88 fprintf(outF, "# %s\n", net->name); |
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89 } |
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90 } |
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91 |
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92 static void |
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93 emit_output_element(elem) |
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94 struct output_element *elem; |
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95 { |
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96 register struct module_def *mod = elem->prim_def; |
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97 register struct module_net_def *port; |
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98 register struct output_net **connp = elem->connections, *conn; |
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99 char *pinkw, *pinname; |
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100 |
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101 fprintf(outF, "\nCOMPONENT %s {\n PRIMITIVE %s\n\n", |
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102 elem->hier_inst_name, mod->name); |
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103 if (mod->prim_is_mapped) |
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104 pinkw = "PINMAP"; |
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105 else |
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106 pinkw = "PIN"; |
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107 for (port = mod->nets; port; port = port->next) { |
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108 pinname = port->name; |
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109 if (mod->prim_numeric_pins) |
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110 pinname += 4; |
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111 fprintf(outF, " %s %s = ", pinkw, pinname); |
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112 conn = *connp++; |
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113 if (conn->name) { |
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114 if (conn->npoints > 1) |
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115 fprintf(outF, "NET %s", conn->name); |
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116 else |
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117 fprintf(outF, "NC (singular net %s)", |
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118 conn->name); |
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119 } else |
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120 fprintf(outF, "NC (module %s line %d inst %s)", |
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121 conn->nc_module_name, conn->nc_module_lineno, |
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122 conn->nc_module_inst); |
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123 fputc('\n', outF); |
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124 } |
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125 fputs("}\n", outF); |
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126 } |
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127 |
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128 static void |
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129 emit_output_elements() |
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130 { |
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131 register struct output_element *elem; |
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132 |
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133 fprintf(outF, "\n# Total instantiated components: %d\n", |
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134 total_output_elements); |
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135 for (elem = output_element_head; elem; elem = elem->next) |
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136 emit_output_element(elem); |
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137 } |
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138 |
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139 generate_output() |
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140 { |
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141 outF = fopen(output_filename, "w"); |
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142 if (!outF) { |
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143 perror(output_filename); |
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144 exit(1); |
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145 } |
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146 fputs("# This netlist has been generated by ueda-sverp\n", outF); |
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147 fputs("# from structural Verilog sources\n", outF); |
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148 if (total_good_nets) { |
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149 find_net_comment_column(); |
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150 emit_good_nets(); |
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151 } |
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152 if (total_singular_nets) |
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153 emit_singular_nets(); |
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154 if (total_null_nets) |
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155 emit_null_nets(); |
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156 emit_output_elements(); |
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157 fclose(outF); |
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158 } |