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annotate ueda/sverp/struct.h @ 66:68900e8dcda1

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pads2gpcb/partinst.c: buglet fixed, swallows GTA02*.asc now
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sun, 31 Jan 2016 22:03:08 +0000
parents cd92449fdb51
children
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1 /*
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2 * Data structures for our structural Verilog to flat netlist processor
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3 */
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4
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5 /*
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6 * Definition of a module as a thing in itself, before elaboration
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7 */
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8 struct module_def {
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9 char *name;
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10 struct module_def *next;
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11 int is_primitive;
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12 /* ports and internal nets */
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13 struct module_net_def *nets;
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14 int nports;
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15 /* counts of individual wires (buses expanded) */
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16 int nwires_ports;
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17 int nwires_internal;
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18 /* downward instantiations */
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19 struct module_def_subinst *subinst;
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20 /* primitives only */
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21 int prim_numeric_pins;
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22 int prim_is_mapped;
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23 };
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24
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25 /*
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26 * Definition of a wire or bus visible in a module (thing-in-itself),
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27 * either port or internal wire.
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28 */
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29 struct module_net_def {
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30 char *name;
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31 struct module_net_def *next;
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32 int is_port;
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33 int def_complete;
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34 int is_bus;
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35 int bus_msb;
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36 int bus_lsb;
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37 int bus_width;
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38 int array_index;
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39 };
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40
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41 /*
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42 * Definition of an instantiation statement in a module as a thing-in-itself
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43 */
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44 struct module_def_subinst {
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45 char *submod_name;
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46 struct module_def *submod_def;
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47 char *inst_name;
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48 struct module_def_subinst *next;
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49 struct connect_entry *connections;
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50 int connect_by_order;
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51 };
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52
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53 /*
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54 * Definition of a connection from a module to a downward port
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55 */
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56 struct connect_entry {
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57 struct connect_entry *next;
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58 /* upper end of the connection */
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59 struct module_net_def *up_netdef; /* NULL means no connect */
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60 int up_offset;
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61 int up_width;
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62 /* lower end of the connection before link pass */
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63 char *down_portname; /* NULL means connect by order */
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64 int down_range_given;
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65 int down_range_msb;
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66 int down_range_lsb;
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67 /* lower end of the connection after link pass */
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68 struct module_net_def *down_portdef;
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69 int down_offset;
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70 int down_width;
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71 /* source line number */
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72 int src_lineno;
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73 };
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74
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75 /* output of the elaboration pass */
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76
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77 struct output_net {
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78 char *name; /* NULL means no connect */
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79 int npoints; /* # of package pins connected to this net */
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80 struct output_net *next;
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81 /* no-connect pseudo-nets */
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82 char *nc_module_name;
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83 int nc_module_lineno;
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84 char *nc_module_inst;
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85 };
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86
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87 struct output_element {
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88 struct module_def *prim_def;
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89 char *hier_inst_name;
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90 struct output_net **connections;
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91 struct output_element *next;
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92 };