FreeCalypso > hg > ueda-linux
annotate ueda/doc/netlisting.txt @ 52:727d4e56d5c8
pads2gpcb/decals.c: silk line extraction implemented
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Sun, 31 Jan 2016 01:26:11 +0000 |
parents | cd92449fdb51 |
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rev | line source |
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1 How uEDA tracks electrical interconnect (netlist) information |
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2 |
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3 Whereas the MCL (see mcldoc.txt) is the authoritative source of information |
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4 about all components making up a board design, information about the way they |
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5 are interconnected is stored in the schematic sheets (.usch files) in the |
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6 language described in uschemlang.txt. Electrical connections are declared by |
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7 way of assigning component pins to named or unnamed nets and may or may not be |
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8 represented graphically. The following two constructs in the uschem language |
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9 connect component pins to nets: |
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10 |
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11 * Net and GraphNet objects |
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12 * PinToNet decorations on component instance objects |
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13 |
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14 Whichever method is used (see uschemlang.txt for the syntax details), the |
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15 declaration of an electrical connection effectively consists of the following |
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16 3 parts: |
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17 |
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18 * Identification of the component involved; |
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19 * Identification of which pin to connect; |
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20 * The name of the net. (Net and GraphNet objects can create unnamed nets - |
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21 those connect together everything listed in the respective object, but |
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22 nothing else can connect to such nets.) |
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23 |
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24 While it's possible for the component identification to be equal to the refdes |
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25 as given in the MCL and for the pin identification to be the "raw" pin number, |
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26 uEDA provides two mechanisms that allow the interconnect information to be |
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27 entered in a slightly more high-level form: component instances and pinout |
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28 mapping. |
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29 |
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30 Component instances |
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31 |
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32 In uEDA a component instance is essentially a reference from a schematic sheet |
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33 to a component in the MCL. In a graphical schematic each component instance |
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34 would normally be represented by a graphical symbol, and all net connections |
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35 made in schematic sheets actually refer to component instances rather than to |
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36 MCL components directly. |
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37 |
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38 For trivial components like resistors and capacitors as well as some simple |
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39 ICs there is normally only one instance per component, hence the component in |
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40 the MCL and the instance in a .usch sheet are one and the same for all practical |
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41 purposes. However, for many of the more complex components it is generally |
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42 desirable to break the component up into multiple sections (which may be |
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43 identical or heterogeneous) represented separately in the schematic source code |
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44 for the design. That's what the component instances in uEDA are for. |
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45 |
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46 In the case when there are multiple component instances referring to the same |
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47 component, these instances may appear either in the same schematic sheet or in |
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48 different sheets. If a given schematic sheet contains only one instance of a |
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49 given MCL component, regardless of whether or not there are other instances for |
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50 the same component in other sheets, the instance name may be equal to the refdes |
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51 of the component - that's what happens when the user doesn't make use of the |
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52 component instance mechanism. However, if a single schematic sheet contains |
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53 more than one instance for a given component, there needs to be a way to |
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54 distinguish between them. |
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55 |
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56 When uEDA tools process a uschem sheet and match it to the MCL, the following |
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57 algorithm is used to match component instances to components: |
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58 |
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59 1. All component instance names appearing in a given schematic sheet are |
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60 required to be unique. |
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61 2. Each component instance name is stripped of any trailing lowercase letters to |
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62 obtain the corresponding refdes. |
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63 3. Each refdes is looked up in the MCL - if not found, that is an error. |
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64 |
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65 Thus if you need to put multiple instances for a given component in a single |
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66 schematic sheet, give each a unique name consisting of the refdes with a unique |
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67 all-lowercase suffix appended to it. |
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68 |
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69 Pinout mapping |
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70 |
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71 uEDA allows one to use two different alphanumeric strings to identify the |
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72 individual pins of a component: pin name and pin number. Both are arbitrary |
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73 alphanumeric strings (actually strings of any printable ASCII characters subject |
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74 only to common sense limitations); the pin number string doesn't have to be |
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75 purely numeric. (For example, PGA and BGA packages normally use alphanumeric |
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76 pin numbers.) |
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77 |
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78 Pin numbers are what appears in the final netlist output from uschem-netlist(1), |
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79 and they may also be used in the schematic source code. If the source only uses |
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80 pin numbers for a given component, then there is no need for uEDA to know the |
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81 pinout of that component. However, uEDA also allows one to specify the pinout |
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82 mapping for a component and to use pin names instead of pin numbers. |
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83 |
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84 Pinouts are specified in dedicated pinout mapping files and brought into the |
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85 design via pinout= attributes in the MCL. Pinout mapping files use a very |
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86 straightforward format: each pin mapping is given on a separate line; each such |
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87 line consists of two fields separated by tabs or spaces: the left field is the |
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88 pin name and the right field is the pin number. Comments are marked by '#'; |
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89 all blank lines and comment lines are ignored. Any additional fields past the |
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90 pin number are currently ignored as well, but this behavior should not be relied |
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91 upon; any such line-appended comments should begin with a '#' character. |
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92 |
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93 The name of the pinout mapping file specified in the pinout= attribute is only |
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94 the base filename, not a pathname. uschem-netlist and uschem-print (the only |
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95 two programs in the uEDA suite that need pinout mappings) locate pinout mapping |
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96 files using the same mechanism that is used to locate graphical symbol files - |
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97 see uschem-netlist(1) and uschem-print(1). |
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98 |
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99 In addition to making the schematic source code more readable, pinout mappings |
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100 make it easy to support components that come in several different packages with |
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101 different physical pin numbers for the same logical functions. It is no longer |
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102 necessary to create multiple versions of the same graphical symbols with |
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103 different pin numbers embedded inside or to edit pin references in Net objects; |
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104 instead all those references can now be made by the logical pin name. If a |
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105 decision is made to change to a different package with a different pinout, only |
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106 the pinout= attribute in the MCL entry for the respective component needs to be |
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107 changed - at the same time when you change the manufacturer_part_number= and |
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108 footprint= attributes. |
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109 |
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110 By the same token it is no longer necessary to create special PCB footprints |
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111 with logical pin names embedded in them where pin number strings normally go: |
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112 instead one can take the natural approach of having footprints identify pins or |
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113 pads by their physical position, having schematics and symbols refer to pins by |
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114 their logical function only and using pinout mapping files to bridge the gap. |
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115 The pinout mapping feature is one of uEDA's main advantages over gEDA. |
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116 |
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117 Slotting |
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118 |
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119 The concept of slotting (and the term) originates in gEDA, but uEDA implements |
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120 it in a very different manner. uEDA's approach to slotting combines component |
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121 instances with pinout mapping in a special way. But first, what is slotting? |
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122 |
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123 Suppose that you have a physical component (typically an IC) that consists of |
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124 multiple identical logical blocks such that each of those blocks should be |
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125 treated as a separate device in the schematic source code. 74xx logic ICs are |
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126 a classic example. When one needs to describe the use of such a component in a |
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127 design, it is normally desirable to represent each slot as its own component |
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128 instance and furthermore to do it in such a way that one doesn't have to decide |
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129 upfront which slot will be used for what, allowing slots to be reassigned with |
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130 ease. |
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131 |
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132 In uEDA this feat is accomplished by combining component instances with pinout |
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133 mapping. When each slot is declared as a component instance, all connections |
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134 to it are made by logical names only: for example, a NAND gate that is 1/4th of |
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135 a 7400 would have connections made to A, B and Y rather than to specific pin |
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136 numbers. So far, so good. But how would the tools know whether A for example |
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137 should be mapped to pin 1, 4, 9 or 12? That is where the slot= attribute comes |
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138 in. It is one of the few attributes defined in the component instance |
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139 declaration (Component object) in a schematic sheet rather than in the MCL. |
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140 When uEDA tools map a pin name to a pin number for a component instance that has |
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141 the slot= attribute defined, the value of this attribute is appended to the pin |
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142 name after a colon, e.g., if the pin name is A and slot=1, the pin name looked |
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143 up in the pinout mapping table will be A:1. The pinout for a 7400 quad NAND |
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144 gate looks like this: |
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145 |
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146 #pin name pin number |
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147 A:1 1 |
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148 B:1 2 |
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149 Y:1 3 |
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150 A:2 4 |
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151 B:2 5 |
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152 Y:2 6 |
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153 GND 7 |
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154 Y:3 8 |
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155 A:3 9 |
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156 B:3 10 |
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157 Y:4 11 |
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158 A:4 12 |
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159 B:4 13 |
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160 Vcc 14 |
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161 |
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162 Note the GND and Vcc pins which are not slotted. It is perfectly legitimate to |
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163 have some component instances which have the slot= attribute selecting one of |
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164 the logic slots, yet have other component instances referring to the same |
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165 component (e.g., for the power pins) without slotting. |
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166 |
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167 The following pinout for an SN75LBC784 EIA-423 transceiver is a more complicated |
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168 example of heterogeneous slotting: |
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169 |
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170 #pin name pin number |
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171 Drvr_In:3 1 |
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172 Rcvr_Out:3 2 |
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173 BIAS1 3 |
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174 Drvr_In:4 4 |
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175 Rcvr_Out:4 5 |
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176 BIAS2 6 |
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177 Vss 7 |
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178 GND 8 |
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179 Rcvr_In_N:4 9 |
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180 Drvr_Out:4 10 |
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181 Rcvr_In_N:3 11 |
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182 Drvr_Out:3 12 |
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183 Rcvr_In_P:3 13 |
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184 Rcvr_In_P:4 14 |
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185 Rcvr_In_P:1 15 |
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186 Rcvr_In_P:2 16 |
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187 Rcvr_In_N:2 17 |
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188 Drvr_Out:2 18 |
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189 Rcvr_In_N:1 19 |
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190 Drvr_Out:1 20 |
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191 Vdd 21 |
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192 Rws 22 |
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193 Drvr_In:1 23 |
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194 Rcvr_Out:1 24 |
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195 BIAS3 25 |
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196 Drvr_In:2 26 |
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197 Rcvr_Out:2 27 |
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198 BIAS4 28 |
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199 |
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200 This IC has 4 driver sections, 4 receiver sections and a set of common pins. |
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201 The pinout file given above allows it to be represented schematically using a |
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202 separate component instance for each driver section (with slotting), a separate |
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203 set of component instances for the receiver sections (an independent set of |
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204 slots) and one or more non-slotted component instances for the common pins. |
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205 |
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206 It is also worth noting that slot names (the value of the slot= attribute) are |
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207 not restricted to numbers only and may in fact be arbitrary ASCII strings. For |
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208 example, it would be sensible to define the pinout for a bicolor LED with slots |
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209 named "red" and "green", having complete pin names such as A:green and C:red |
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210 with connections being made to just A and C on the proper instances. |
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211 |
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212 Netlist generation |
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213 |
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214 When uschem-netlist processes a set of schematic sheets and an MCL to compile a |
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215 complete netlist, it first resolves all pin names (with or without slots) to |
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216 physical pin numbers and tracks the connection information at the component |
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217 level, i.e., the information is effectively moved up from the instance level at |
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218 which it is specified in the schematic source code to the component level. The |
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219 netlist data structures constructed by uschem-netlist maintain a hard |
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220 requirement that every physical pin of every component listed in the MCL be |
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221 either connected to exactly one net or left unconnected; thus any attempt to |
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222 connect the same physical pin to more than one net will be detected and flagged |
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223 as an error regardless of how each connection was specified in the source code. |
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224 |
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225 One may use the NoConnect decoration on a component instance object to declare |
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226 explicitly that a given pin shall be left unconnected. uschem-netlist will note |
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227 such declarations and flag an error if an attempt is made anywhere else in the |
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228 source code to connect the same physical pin to some net. |
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229 |
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230 Differences from gEDA |
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231 |
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232 The main difference between gEDA and uEDA with regard to netlisting is that in |
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233 uEDA graphical elements such as symbols and net lines do not create electrical |
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234 connections, they merely illustrate them. The uschem language (documented fully |
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235 in uschemlang.txt) is designed so that the graphical information and the |
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236 electrical interconnect information are mostly orthogonal. The electrical |
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237 interconnect information must be fully specified in the .usch files, not |
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238 inferred from symbol files, to the point that the latter files are not needed |
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239 for netlist generation and are not read by uschem-netlist at all. Thus gEDA |
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240 constructs such as auto-connected hidden power pins have no place in uEDA; the |
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241 closest one can get to that would be to insert a non-graphical component |
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242 instance with the necessary net connections into an otherwise graphical |
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243 schematic sheet. |
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244 |
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245 By a similar token the graphical symbols for power rails and such do not cause |
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246 a net to be connected to a rail, instead that connection is made by having the |
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247 proper netname set on the GraphNet object in the .usch file; the symbols merely |
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248 illustrate it graphically for those looking at the printout rather than the |
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249 source code. |
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250 |
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251 The downside with uEDA's approach is of course the very real possibility that |
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252 the netlist and the graphics will get out of sync, i.e., that the set of |
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253 electrical interconnections mentally inferred by someone looking at the |
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254 graphical schematic printout will differ from the set of interconnections |
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255 embodied in the source code processed by uEDA tools. See drc.txt for the |
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256 discussion of how uEDA addresses this problem. |