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comparison ifctf-part-lib/geda-symbols/EPF10K30ATx144-power.trg @ 0:cd92449fdb51

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initial import of ueda and ifctf-part-lib from ifctfvax CVS
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 20 Jul 2015 00:24:37 +0000
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-1:000000000000 0:cd92449fdb51
1 # This is the template file for creating symbols with tragesym
2 # every line starting with '#' is a comment line.
3
4 [options]
5 # rotate_labels rotates the pintext of top and bottom pins
6 # wordswap swaps labels if the pin is on the right side an looks like this:
7 # "PB1 (CLK)"
8 wordswap=yes
9 rotate_labels=no
10 sort_labels=no
11 generate_pinseq=yes
12 sym_width=9000
13 pinwidthvertikal=400
14 pinwidthhorizontal=600
15
16 [geda_attr]
17 # name will be printed in the top of the symbol
18 # if you have a device with slots, you'll have to use slot= and slotdef=
19 # use comment= if there are special information you want to add
20 version=20030525
21 name=EPF10K30ATx144
22 device=EPF10K30ATx144
23 refdes=U?
24 footprint=QFP144
25 description=EPF10K30ATx144 FPGA, power pins
26 documentation=
27 author=Michael Sokolov <msokolov@ivan.Harhan.ORG>
28 numslots=0
29 #slot=1
30 #slotdef=1:
31 #slotdef=2:
32 #slotdef=3:
33 #slotdef=4:
34 #comment=
35 #comment=
36
37 [pins]
38 # tabseparated list of pin descriptions
39 # pinnr is the physical number of the pin
40 # seq is the pinseq= attribute, leave it blank if it doesn't matter
41 # type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
42 # style can be (line,dot,clk,dotclk,none). none if only want to add a net
43 # posit. can be (l,r,t,b) or empty for nets
44 # net specifies the name of the Vcc or GND name
45 # label represents the pinlabel.
46 # negation lines can be added with _Q_
47 # if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
48 #-----------------------------------------------------
49 #pinnr seq type style posit. net label
50 #-----------------------------------------------------
51 6 pwr line t VCCint
52 25 pwr line t VCCint
53 52 pwr line t VCCint
54 53 pwr line t VCCint
55 75 pwr line t VCCint
56 93 pwr line t VCCint
57 123 pwr line t VCCint
58
59 5 pwr line t VCCio
60 24 pwr line t VCCio
61 45 pwr line t VCCio
62 61 pwr line t VCCio
63 71 pwr line t VCCio
64 94 pwr line t VCCio
65 115 pwr line t VCCio
66 134 pwr line t VCCio
67
68 16 pwr line b GNDint
69 57 pwr line b GNDint
70 58 pwr line b GNDint
71 84 pwr line b GNDint
72 103 pwr line b GNDint
73 127 pwr line b GNDint
74
75 15 pwr line b GNDio
76 40 pwr line b GNDio
77 50 pwr line b GNDio
78 66 pwr line b GNDio
79 85 pwr line b GNDio
80 104 pwr line b GNDio
81 129 pwr line b GNDio
82 139 pwr line b GNDio