--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144-power.trg	Mon Jul 20 00:24:37 2015 +0000
@@ -0,0 +1,82 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# rotate_labels rotates the pintext of top and bottom pins
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)"
+wordswap=yes
+rotate_labels=no
+sort_labels=no
+generate_pinseq=yes
+sym_width=9000
+pinwidthvertikal=400
+pinwidthhorizontal=600
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20030525
+name=EPF10K30ATx144
+device=EPF10K30ATx144
+refdes=U?
+footprint=QFP144
+description=EPF10K30ATx144 FPGA, power pins
+documentation=
+author=Michael Sokolov <msokolov@ivan.Harhan.ORG>
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the Vcc or GND name
+# label represents the pinlabel. 
+#	negation lines can be added with _Q_ 
+#	if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
+#-----------------------------------------------------
+#pinnr	seq	type	style	posit.	net	label	
+#-----------------------------------------------------
+6		pwr	line	t		VCCint
+25		pwr	line	t		VCCint
+52		pwr	line	t		VCCint
+53		pwr	line	t		VCCint
+75		pwr	line	t		VCCint
+93		pwr	line	t		VCCint
+123		pwr	line	t		VCCint
+
+5		pwr	line	t		VCCio
+24		pwr	line	t		VCCio
+45		pwr	line	t		VCCio
+61		pwr	line	t		VCCio
+71		pwr	line	t		VCCio
+94		pwr	line	t		VCCio
+115		pwr	line	t		VCCio
+134		pwr	line	t		VCCio
+
+16		pwr	line	b		GNDint
+57		pwr	line	b		GNDint
+58		pwr	line	b		GNDint
+84		pwr	line	b		GNDint
+103		pwr	line	b		GNDint
+127		pwr	line	b		GNDint
+
+15		pwr	line	b		GNDio
+40		pwr	line	b		GNDio
+50		pwr	line	b		GNDio
+66		pwr	line	b		GNDio
+85		pwr	line	b		GNDio
+104		pwr	line	b		GNDio
+129		pwr	line	b		GNDio
+139		pwr	line	b		GNDio