--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ueda/sverp/main.c	Mon Jul 20 00:24:37 2015 +0000
@@ -0,0 +1,90 @@
+/*
+ * main() function for ueda-sverp
+ */
+
+#include <stdio.h>
+#include "struct.h"
+
+struct module_def *glob_module_list, *top_module_def;
+char *primitives_filename = "primitives", *top_module_expl;
+int verbose, top_module_candidates;
+char *output_filename = "sverp.out";
+
+static void
+usage()
+{
+	fprintf(stderr,
+"usage: ueda-sverp [-p primfile] [-t top-module] [-v] verilog-sources\n");
+	exit(1);
+}
+
+static void
+process_options(argc, argv)
+	char **argv;
+{
+	register int c;
+	extern char *optarg;
+
+	while ((c = getopt(argc, argv, "I:o:p:t:v")) != EOF) {
+		switch (c) {
+		case 'I':
+			add_symfile_dir(optarg);
+			continue;
+		case 'o':
+			output_filename = optarg;
+			continue;
+		case 'p':
+			primitives_filename = optarg;
+			continue;
+		case 't':
+			top_module_expl = optarg;
+			continue;
+		case 'v':
+			verbose++;
+			continue;
+		default:
+			usage();
+		}
+	}
+}
+
+main(argc, argv)
+	char **argv;
+{
+	extern int optind;
+
+	process_options(argc, argv);
+	if (optind >= argc)
+		usage();
+	for (; optind < argc; optind++) {
+		if (verbose)
+			printf("Reading Verilog source %s\n", argv[optind]);
+		read_verilog_file(argv[optind]);
+	}
+	if (top_module_expl)
+		process_explicit_topmod();
+	if (verbose)
+		printf("Reading primitive definitions from %s\n",
+			primitives_filename);
+	set_default_sympath();	/* for xGA definition files */
+	read_primitives_file(primitives_filename);
+	if (verbose)
+		printf("Linking instantiations to lower modules\n");
+	link_pass();
+	if (!top_module_def) {
+		fprintf(stderr, "error: no top module found\n");
+		exit(1);
+	}
+	if (!top_module_expl && top_module_candidates > 1) {
+		fprintf(stderr,
+		"error: more than one top module candidate, use -t option\n");
+		exit(1);
+	}
+	if (verbose)
+		printf("Elaborating hierarchy from top module %s\n",
+			top_module_def->name);
+	elaborate_module(top_module_def, top_module_def->name, "", 0);
+	tally_output_nets();
+	generate_output();
+	exit(0);
+}