v 20040111 1
T 4400 3300 8 10 1 1 0 6 1
refdes=U?
T 400 3250 9 10 1 1 0 0 1
device=EPF10K30ATx144
T 400 3650 5 10 0 0 0 0 1
footprint=LQFP144_20
T 400 3850 5 10 0 0 0 0 1
author=Michael Sokolov <msokolov@ivan.Harhan.ORG>
T 400 4250 5 10 0 0 0 0 1
description=EPF10K30ATx144 FPGA, global input pins
T 400 4450 5 10 0 0 0 0 1
numslots=0
P 100 2800 400 2800 1 0 0
{
T 300 2850 5 8 1 1 0 6 1
pinnumber=55
T 300 2750 5 8 0 1 0 8 1
pinseq=55
T 525 2800 9 8 1 1 0 0 1
pinname=GCLK0
T 525 2800 5 8 0 1 0 2 1
pintype=in
}
L 500 2800 400 2875 3 0 0 0 -1 -1
L 500 2800 400 2725 3 0 0 0 -1 -1
P 100 2400 400 2400 1 0 0
{
T 300 2450 5 8 1 1 0 6 1
pinnumber=125
T 300 2350 5 8 0 1 0 8 1
pinseq=125
T 525 2400 9 8 1 1 0 0 1
pinname=GCLK1
T 525 2400 5 8 0 1 0 2 1
pintype=in
}
L 500 2400 400 2475 3 0 0 0 -1 -1
L 500 2400 400 2325 3 0 0 0 -1 -1
P 100 1600 400 1600 1 0 0
{
T 300 1650 5 8 1 1 0 6 1
pinnumber=54
T 300 1550 5 8 0 1 0 8 1
pinseq=54
T 450 1600 9 8 1 1 0 0 1
pinname=GIN0
T 450 1600 5 8 0 1 0 2 1
pintype=in
}
P 100 1200 400 1200 1 0 0
{
T 300 1250 5 8 1 1 0 6 1
pinnumber=56
T 300 1150 5 8 0 1 0 8 1
pinseq=56
T 450 1200 9 8 1 1 0 0 1
pinname=GIN1
T 450 1200 5 8 0 1 0 2 1
pintype=in
}
P 100 800 400 800 1 0 0
{
T 300 850 5 8 1 1 0 6 1
pinnumber=124
T 300 750 5 8 0 1 0 8 1
pinseq=124
T 450 800 9 8 1 1 0 0 1
pinname=GIN2
T 450 800 5 8 0 1 0 2 1
pintype=in
}
P 100 400 400 400 1 0 0
{
T 300 450 5 8 1 1 0 6 1
pinnumber=126
T 300 350 5 8 0 1 0 8 1
pinseq=126
T 450 400 9 8 1 1 0 0 1
pinname=GIN3
T 450 400 5 8 0 1 0 2 1
pintype=in
}
P 4700 1600 4400 1600 1 0 0
{
T 4500 1650 5 8 1 1 0 0 1
pinnumber=122
T 4500 1550 5 8 0 1 0 2 1
pinseq=122
T 4350 1600 9 8 1 1 0 6 1
pinname=DEV_CLRn
T 4350 1600 5 8 0 1 0 8 1
pintype=in
}
P 4700 1200 4400 1200 1 0 0
{
T 4500 1250 5 8 1 1 0 0 1
pinnumber=128
T 4500 1150 5 8 0 1 0 2 1
pinseq=128
T 4350 1200 9 8 1 1 0 6 1
pinname=DEV_OE
T 4350 1200 5 8 0 1 0 8 1
pintype=in
}
B 400 0 4000 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1800 1500 9 10 1 0 0 0 1
GLOBAL
T 1900 1200 9 10 1 0 0 0 1
INPUTS