FreeCalypso > hg > ueda-linux
view ifctf-part-lib/uschem-symbols/EPF10K30ATx144-power.sym @ 43:4a50888d09ce
pads2gpcb: handle error cases when the default pad is defined, but failed
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Sat, 30 Jan 2016 05:39:52 +0000 |
parents | cd92449fdb51 |
children |
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v 20040111 1 T 9200 1800 8 10 1 1 0 0 1 refdes=U? T 200 1350 9 10 1 1 0 0 1 device=EPF10K30ATx144 T 300 2950 5 10 0 0 0 0 1 footprint=LQFP144_20 T 300 3150 5 10 0 0 0 0 1 author=Michael Sokolov <msokolov@ivan.Harhan.ORG> T 300 3550 5 10 0 0 0 0 1 description=EPF10K30ATx144 FPGA, power pins T 300 3750 5 10 0 0 0 0 1 numslots=0 P 400 2300 400 2000 1 0 0 { T 450 2100 5 8 1 1 0 0 1 pinnumber=6 T 450 2100 5 8 0 1 0 2 1 pinseq=6 T 400 1950 9 8 1 1 0 5 1 pinlabel=VCCint T 400 1800 5 8 0 1 0 5 1 pintype=pwr } P 1000 2300 1000 2000 1 0 0 { T 1050 2100 5 8 1 1 0 0 1 pinnumber=25 T 1050 2100 5 8 0 1 0 2 1 pinseq=25 T 1000 1950 9 8 1 1 0 5 1 pinlabel=VCCint T 1000 1800 5 8 0 1 0 5 1 pintype=pwr } P 1600 2300 1600 2000 1 0 0 { T 1650 2100 5 8 1 1 0 0 1 pinnumber=52 T 1650 2100 5 8 0 1 0 2 1 pinseq=52 T 1600 1950 9 8 1 1 0 5 1 pinlabel=VCCint T 1600 1800 5 8 0 1 0 5 1 pintype=pwr } P 2200 2300 2200 2000 1 0 0 { T 2250 2100 5 8 1 1 0 0 1 pinnumber=53 T 2250 2100 5 8 0 1 0 2 1 pinseq=53 T 2200 1950 9 8 1 1 0 5 1 pinlabel=VCCint T 2200 1800 5 8 0 1 0 5 1 pintype=pwr } P 2800 2300 2800 2000 1 0 0 { T 2850 2100 5 8 1 1 0 0 1 pinnumber=75 T 2850 2100 5 8 0 1 0 2 1 pinseq=75 T 2800 1950 9 8 1 1 0 5 1 pinlabel=VCCint T 2800 1800 5 8 0 1 0 5 1 pintype=pwr } P 3400 2300 3400 2000 1 0 0 { T 3450 2100 5 8 1 1 0 0 1 pinnumber=93 T 3450 2100 5 8 0 1 0 2 1 pinseq=93 T 3400 1950 9 8 1 1 0 5 1 pinlabel=VCCint T 3400 1800 5 8 0 1 0 5 1 pintype=pwr } P 4000 2300 4000 2000 1 0 0 { T 4050 2100 5 8 1 1 0 0 1 pinnumber=123 T 4050 2100 5 8 0 1 0 2 1 pinseq=123 T 4000 1950 9 8 1 1 0 5 1 pinlabel=VCCint T 4000 1800 5 8 0 1 0 5 1 pintype=pwr } P 4600 2300 4600 2000 1 0 0 { T 4650 2100 5 8 1 1 0 0 1 pinnumber=5 T 4650 2100 5 8 0 1 0 2 1 pinseq=5 T 4600 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 4600 1800 5 8 0 1 0 5 1 pintype=pwr } P 5200 2300 5200 2000 1 0 0 { T 5250 2100 5 8 1 1 0 0 1 pinnumber=24 T 5250 2100 5 8 0 1 0 2 1 pinseq=24 T 5200 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 5200 1800 5 8 0 1 0 5 1 pintype=pwr } P 5800 2300 5800 2000 1 0 0 { T 5850 2100 5 8 1 1 0 0 1 pinnumber=45 T 5850 2100 5 8 0 1 0 2 1 pinseq=45 T 5800 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 5800 1800 5 8 0 1 0 5 1 pintype=pwr } P 6400 2300 6400 2000 1 0 0 { T 6450 2100 5 8 1 1 0 0 1 pinnumber=61 T 6450 2100 5 8 0 1 0 2 1 pinseq=61 T 6400 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 6400 1800 5 8 0 1 0 5 1 pintype=pwr } P 7000 2300 7000 2000 1 0 0 { T 7050 2100 5 8 1 1 0 0 1 pinnumber=71 T 7050 2100 5 8 0 1 0 2 1 pinseq=71 T 7000 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 7000 1800 5 8 0 1 0 5 1 pintype=pwr } P 7600 2300 7600 2000 1 0 0 { T 7650 2100 5 8 1 1 0 0 1 pinnumber=94 T 7650 2100 5 8 0 1 0 2 1 pinseq=94 T 7600 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 7600 1800 5 8 0 1 0 5 1 pintype=pwr } P 8200 2300 8200 2000 1 0 0 { T 8250 2100 5 8 1 1 0 0 1 pinnumber=115 T 8250 2100 5 8 0 1 0 2 1 pinseq=115 T 8200 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 8200 1800 5 8 0 1 0 5 1 pintype=pwr } P 8800 2300 8800 2000 1 0 0 { T 8850 2100 5 8 1 1 0 0 1 pinnumber=134 T 8850 2100 5 8 0 1 0 2 1 pinseq=134 T 8800 1950 9 8 1 1 0 5 1 pinlabel=VCCio T 8800 1800 5 8 0 1 0 5 1 pintype=pwr } P 400 0 400 300 1 0 0 { T 450 100 5 8 1 1 0 0 1 pinnumber=16 T 450 100 5 8 0 1 0 2 1 pinseq=16 T 400 350 9 8 1 1 0 3 1 pinlabel=GNDint T 400 500 5 8 0 1 0 3 1 pintype=pwr } P 1000 0 1000 300 1 0 0 { T 1050 100 5 8 1 1 0 0 1 pinnumber=57 T 1050 100 5 8 0 1 0 2 1 pinseq=57 T 1000 350 9 8 1 1 0 3 1 pinlabel=GNDint T 1000 500 5 8 0 1 0 3 1 pintype=pwr } P 1600 0 1600 300 1 0 0 { T 1650 100 5 8 1 1 0 0 1 pinnumber=58 T 1650 100 5 8 0 1 0 2 1 pinseq=58 T 1600 350 9 8 1 1 0 3 1 pinlabel=GNDint T 1600 500 5 8 0 1 0 3 1 pintype=pwr } P 2200 0 2200 300 1 0 0 { T 2250 100 5 8 1 1 0 0 1 pinnumber=84 T 2250 100 5 8 0 1 0 2 1 pinseq=84 T 2200 350 9 8 1 1 0 3 1 pinlabel=GNDint T 2200 500 5 8 0 1 0 3 1 pintype=pwr } P 2800 0 2800 300 1 0 0 { T 2850 100 5 8 1 1 0 0 1 pinnumber=103 T 2850 100 5 8 0 1 0 2 1 pinseq=103 T 2800 350 9 8 1 1 0 3 1 pinlabel=GNDint T 2800 500 5 8 0 1 0 3 1 pintype=pwr } P 3400 0 3400 300 1 0 0 { T 3450 100 5 8 1 1 0 0 1 pinnumber=127 T 3450 100 5 8 0 1 0 2 1 pinseq=127 T 3400 350 9 8 1 1 0 3 1 pinlabel=GNDint T 3400 500 5 8 0 1 0 3 1 pintype=pwr } P 4600 0 4600 300 1 0 0 { T 4650 100 5 8 1 1 0 0 1 pinnumber=15 T 4650 100 5 8 0 1 0 2 1 pinseq=15 T 4600 350 9 8 1 1 0 3 1 pinlabel=GNDio T 4600 500 5 8 0 1 0 3 1 pintype=pwr } P 5200 0 5200 300 1 0 0 { T 5250 100 5 8 1 1 0 0 1 pinnumber=40 T 5250 100 5 8 0 1 0 2 1 pinseq=40 T 5200 350 9 8 1 1 0 3 1 pinlabel=GNDio T 5200 500 5 8 0 1 0 3 1 pintype=pwr } P 5800 0 5800 300 1 0 0 { T 5850 100 5 8 1 1 0 0 1 pinnumber=50 T 5850 100 5 8 0 1 0 2 1 pinseq=50 T 5800 350 9 8 1 1 0 3 1 pinlabel=GNDio T 5800 500 5 8 0 1 0 3 1 pintype=pwr } P 6400 0 6400 300 1 0 0 { T 6450 100 5 8 1 1 0 0 1 pinnumber=66 T 6450 100 5 8 0 1 0 2 1 pinseq=66 T 6400 350 9 8 1 1 0 3 1 pinlabel=GNDio T 6400 500 5 8 0 1 0 3 1 pintype=pwr } P 7000 0 7000 300 1 0 0 { T 7050 100 5 8 1 1 0 0 1 pinnumber=85 T 7050 100 5 8 0 1 0 2 1 pinseq=85 T 7000 350 9 8 1 1 0 3 1 pinlabel=GNDio T 7000 500 5 8 0 1 0 3 1 pintype=pwr } P 7600 0 7600 300 1 0 0 { T 7650 100 5 8 1 1 0 0 1 pinnumber=104 T 7650 100 5 8 0 1 0 2 1 pinseq=104 T 7600 350 9 8 1 1 0 3 1 pinlabel=GNDio T 7600 500 5 8 0 1 0 3 1 pintype=pwr } P 8200 0 8200 300 1 0 0 { T 8250 100 5 8 1 1 0 0 1 pinnumber=129 T 8250 100 5 8 0 1 0 2 1 pinseq=129 T 8200 350 9 8 1 1 0 3 1 pinlabel=GNDio T 8200 500 5 8 0 1 0 3 1 pintype=pwr } P 8800 0 8800 300 1 0 0 { T 8850 100 5 8 1 1 0 0 1 pinnumber=139 T 8850 100 5 8 0 1 0 2 1 pinseq=139 T 8800 350 9 8 1 1 0 3 1 pinlabel=GNDio T 8800 500 5 8 0 1 0 3 1 pintype=pwr } B 0 300 9100 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 3900 1000 9 10 1 0 0 0 1 POWER