# This is the template file for creating symbols with tragesym
# every line starting with '#' is a comment line.

[options]
# rotate_labels rotates the pintext of top and bottom pins
# wordswap swaps labels if the pin is on the right side an looks like this:
# "PB1 (CLK)"
wordswap=yes
rotate_labels=no
sort_labels=no
generate_pinseq=yes
sym_width=4000
pinwidthvertikal=400
pinwidthhorizontal=600

[geda_attr]
# name will be printed in the top of the symbol
# if you have a device with slots, you'll have to use slot= and slotdef=
# use comment= if there are special information you want to add
version=20030525
name=EPF10K30ATx144
device=EPF10K30ATx144
refdes=U?
footprint=QFP144
description=EPF10K30ATx144 FPGA, configuration and JTAG pins
documentation=
author=Michael Sokolov <msokolov@ivan.Harhan.ORG>
numslots=0
#slot=1
#slotdef=1:
#slotdef=2:
#slotdef=3:
#slotdef=4:
#comment=
#comment=

[pins]
# tabseparated list of pin descriptions
# pinnr is the physical number of the pin
# seq is the pinseq= attribute, leave it blank if it doesn't matter
# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
# style can be (line,dot,clk,dotclk,none). none if only want to add a net
# posit. can be (l,r,t,b) or empty for nets
# net specifies the name of the Vcc or GND name
# label represents the pinlabel. 
#	negation lines can be added with _Q_ 
#	if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
#-----------------------------------------------------
#pinnr	seq	type	style	posit.	net	label	
#-----------------------------------------------------
105		in	line	l		TDI
34		in	line	l		TMS
4		out	line	l		TDO
1		in	clk	l		TCK
1001		pas	line	l		DUMMY
106		in	line	l		nCE
1002		pas	line	l		DUMMY
74		in	line	l		nCONFIG
35		tri	line	l		nSTATUS
2		out	line	l		CONF\_DONE
14		out	line	l		INIT\_DONE

77		in	line	r		MSEL0
76		in	line	r		MSEL1

3		out	line	r		nCEO