FreeCalypso > hg > ueda-linux
changeset 0:cd92449fdb51
initial import of ueda and ifctf-part-lib from ifctfvax CVS
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/footprints/DE9M.fp Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,18 @@ +Element["" "DE9M" "J?" "" 42500 100000 12100 41700 1 150 ""] +( + Pin[600 0 6000 3000 6600 3500 "1" "1" "square"] + Pin[600 10800 6000 3000 6600 3500 "2" "2" ""] + Pin[600 21600 6000 3000 6600 3500 "3" "3" ""] + Pin[600 32400 6000 3000 6600 3500 "4" "4" ""] + Pin[600 43200 6000 3000 6600 3500 "5" "5" ""] + Pin[-10600 5400 6000 3000 6600 3500 "6" "6" ""] + Pin[-10600 16200 6000 3000 6600 3500 "7" "7" ""] + Pin[-10600 27000 6000 3000 6600 3500 "8" "8" ""] + Pin[-10600 37800 6000 3000 6600 3500 "9" "9" ""] + Pin[-5000 -27600 25000 3000 25600 12500 "C1" "10" ""] + Pin[-5000 70800 25000 3000 25600 12500 "C2" "11" ""] + ElementLine [-42000 -41200 8600 -41200 1000] + ElementLine [-42000 84400 8600 84400 1000] + ElementLine [8600 -41200 8600 84400 1000] + + )
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/footprints/FUSE__Littelfuse_461_Series.fp Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,12 @@ +# author: Michael Spacefalcon +# email: msokolov@ivan.Harhan.ORG + +Element["" "" "" "" 20000 20000 0 0 0 100 ""] +( + ElementLine[-25900 -7850 25900 -7850 1000] + ElementLine[-25900 7850 25900 7850 1000] + ElementLine[-25900 -7850 -25900 7850 1000] + ElementLine[ 25900 -7850 25900 7850 1000] + Pad[-18400 -350 -18400 350 12800 1000 13400 "1" "1" "square"] + Pad[ 18400 -350 18400 350 12800 1000 13400 "2" "2" "square"] +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/footprints/LED__Dialight_591-2xxx Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,11 @@ +# author: Michael Sokolov +# email: msokolov@ivan.Harhan.ORG + +Element["" "" "" "" 20000 20000 0 0 0 100 ""] +( + ElementLine[-12000 -9000 12500 -9000 1000] + ElementLine[-12000 9000 12500 9000 1000] + ElementLine[ 12500 -9000 12500 9000 1000] + Pad[ 6300 -750 6300 750 7900 1000 8500 "1" "1" "square"] + Pad[-6300 -750 -6300 750 7900 1000 8500 "2" "2" "square"] +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/footprints/LED__Dialight_591-3xxx Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,13 @@ +# author: Michael Sokolov +# email: msokolov@ivan.Harhan.ORG + +Element["" "" "" "" 20000 20000 0 0 0 100 ""] +( + ElementLine[-12000 -9000 12500 -9000 1000] + ElementLine[-12000 9000 12500 9000 1000] + ElementLine[ 12500 -9000 12500 9000 1000] + Pad[ 5100 2950 6700 2950 4300 1000 4900 "1" "1" "square"] + Pad[-5100 2950 -6700 2950 4300 1000 4900 "2" "2" "square"] + Pad[ 5100 -2950 6700 -2950 4300 1000 4900 "3" "3" "square"] + Pad[-5100 -2950 -6700 -2950 4300 1000 4900 "4" "4" "square"] +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/footprints/RJ12 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,22 @@ +# author: Levente Kovacs +# email: lekovacs@interware.hu +# dist-license: GPL 2 +# use-license: unlimited + +Element["" "" "" "" 297500 147500 0 0 0 100 ""] +( + Pin[-35000 -7500 12800 2000 12800 12800 "" "1" "hole,edge2"] + Pin[-35000 32500 12800 2000 12800 12800 "" "2" "hole,edge2"] + Pin[-10000 15000 6000 2000 6000 2800 "" "4" "edge2"] + Pin[0 10000 6000 2000 6000 2800 "" "3" "edge2"] + Pin[0 20000 6000 2000 6000 2800 "" "5" "edge2"] + Pin[0 0 6000 2000 6000 2800 "" "1" "square,edge2"] + Pin[-10000 5000 6000 2000 6000 2800 "" "2" "edge2"] + Pin[-10000 25000 6000 2000 6000 2800 "" "6" "edge2"] + ElementLine [-66000 -18700 -66000 43800 1000] + ElementLine [-66000 43800 5500 43800 1000] + ElementLine [5500 43800 5500 -18700 1000] + ElementLine [5500 -18700 -66000 -18700 1000] + ElementLine [-56600 43600 -56600 -18700 1000] + + )
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/footprints/RJ45 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,24 @@ +# author: Levente Kovacs +# email: lekovacs@interware.hu +# dist-license: GPL 2 +# use-license: unlimited + +Element["" "" "" "" 200000 142500 -2500 0 0 100 ""] +( + Pin[10000 35000 6000 2000 6000 2800 "" "8" "edge2"] + Pin[0 30000 6000 2000 6000 2800 "" "7" "edge2"] + Pin[10000 15000 6000 2000 6000 2800 "" "4" "edge2"] + Pin[0 10000 6000 2000 6000 2800 "" "3" "edge2"] + Pin[0 20000 6000 2000 6000 2800 "" "5" "edge2"] + Pin[0 0 6000 2000 6000 2800 "" "1" "square,edge2"] + Pin[10000 5000 6000 2000 6000 2800 "" "2" "edge2"] + Pin[10000 25000 6000 2000 6000 2800 "" "6" "edge2"] + Pin[-25000 -5000 12800 2000 12800 12800 "" "1" "hole,edge2"] + Pin[-25000 40000 12800 2000 12800 12800 "" "2" "hole,edge2"] + ElementLine [-47000 -14500 -47000 49300 1000] + ElementLine [-56000 49500 15000 49500 1000] + ElementLine [15000 49500 15000 -14500 1000] + ElementLine [-56000 -14500 15000 -14500 1000] + ElementLine [-56000 -14500 -56000 49500 1000] + + )
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/footprints/SIDAC__Littelfuse_DO214_Package.fp Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,12 @@ +# author: Michael Spacefalcon +# email: msokolov@ivan.Harhan.ORG + +Element["" "" "" "" 20000 20000 0 0 0 100 ""] +( + ElementLine[-13000 -7800 13000 -7800 1000] + ElementLine[-13000 7800 13000 7800 1000] + ElementLine[-13000 -7800 -13000 7800 1000] + ElementLine[ 13000 -7800 13000 7800 1000] + Pad[-7900 -1550 -7900 1550 7900 1000 8500 "1" "1" "square"] + Pad[ 7900 -1550 7900 1550 7900 1000 8500 "2" "2" "square"] +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/12V-minus-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +v 20040111 1 +P 200 200 200 400 1 0 1 +{ +T 250 250 5 6 0 1 0 0 1 +pinnumber=1 +T 250 250 5 6 0 0 0 0 1 +pinseq=1 +T 250 250 5 6 0 1 0 0 1 +pinlabel=1 +T 250 250 5 6 0 1 0 0 1 +pintype=pwr +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 50 50 9 8 1 0 0 0 1 +-12V +T 300 200 8 8 0 0 0 0 1 +net=-12V:1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/26LS31-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,58 @@ +v 20040111 1 +L 400 600 400 200 3 0 0 0 -1 -1 +L 400 200 700 400 3 0 0 0 -1 -1 +L 700 400 400 600 3 0 0 0 -1 -1 +V 650 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 400 400 400 1 0 0 +{ +T 200 500 5 8 1 1 0 7 1 +pinnumber=1 +T 200 500 5 8 0 1 0 7 1 +pinseq=1 +T 200 500 5 8 0 1 0 6 1 +pinlabel=A +T 200 500 5 8 0 1 0 8 1 +pintype=in +} +P 900 300 600 300 1 0 0 +{ +T 800 400 5 8 1 1 0 7 1 +pinnumber=2 +T 800 400 5 8 0 1 0 7 1 +pinseq=2 +T 800 350 5 8 0 1 0 6 1 +pinlabel=Y +T 800 350 5 8 0 1 0 8 1 +pintype=out +} +P 900 500 700 500 1 0 0 +{ +T 800 600 5 8 1 1 0 7 1 +pinnumber=3 +T 800 600 5 8 0 1 0 7 1 +pinseq=3 +T 800 550 5 8 0 1 0 6 1 +pinlabel=Z +T 800 550 5 8 0 1 0 8 1 +pintype=out +} +T 300 0 9 8 1 1 0 0 1 +device=26LS31 +T 400 700 8 10 1 1 0 0 1 +refdes=U? +T 100 1000 5 10 0 0 0 0 1 +footprint=DIP16 +T 100 1200 5 10 0 0 0 0 1 +description=Quad Differential Line Driver +T 100 1400 5 10 0 0 0 0 1 +numslots=4 +T 100 1600 5 10 0 0 0 0 1 +slot=1 +T 100 1800 5 10 0 0 0 0 1 +slotdef=1:1,2,3 +T 100 2000 5 10 0 0 0 0 1 +slotdef=2:7,6,5 +T 100 2200 5 10 0 0 0 0 1 +slotdef=3:9,10,11 +T 100 2400 5 10 0 0 0 0 1 +slotdef=4:15,14,13
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/26LS31-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,58 @@ +v 20040111 1 +L 400 600 400 200 3 0 0 0 -1 -1 +L 400 200 700 400 3 0 0 0 -1 -1 +L 700 400 400 600 3 0 0 0 -1 -1 +V 650 300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 400 400 400 1 0 0 +{ +T 200 500 5 8 1 1 0 7 1 +pinnumber=1 +T 200 500 5 8 0 1 0 7 1 +pinseq=1 +T 200 500 5 8 0 1 0 6 1 +pinlabel=A +T 200 500 5 8 0 1 0 8 1 +pintype=in +} +P 900 500 600 500 1 0 0 +{ +T 800 600 5 8 1 1 0 7 1 +pinnumber=2 +T 800 600 5 8 0 1 0 7 1 +pinseq=2 +T 800 550 5 8 0 1 0 6 1 +pinlabel=Y +T 800 550 5 8 0 1 0 8 1 +pintype=out +} +P 900 300 700 300 1 0 0 +{ +T 800 400 5 8 1 1 0 7 1 +pinnumber=3 +T 800 400 5 8 0 1 0 7 1 +pinseq=3 +T 800 350 5 8 0 1 0 6 1 +pinlabel=Z +T 800 350 5 8 0 1 0 8 1 +pintype=out +} +T 300 0 9 8 1 1 0 0 1 +device=26LS31 +T 400 700 8 10 1 1 0 0 1 +refdes=U? +T 100 1000 5 10 0 0 0 0 1 +footprint=DIP16 +T 100 1200 5 10 0 0 0 0 1 +description=Quad Differential Line Driver +T 100 1400 5 10 0 0 0 0 1 +numslots=4 +T 100 1600 5 10 0 0 0 0 1 +slot=1 +T 100 1800 5 10 0 0 0 0 1 +slotdef=1:1,2,3 +T 100 2000 5 10 0 0 0 0 1 +slotdef=2:7,6,5 +T 100 2200 5 10 0 0 0 0 1 +slotdef=3:9,10,11 +T 100 2400 5 10 0 0 0 0 1 +slotdef=4:15,14,13
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/26LS31-com.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,59 @@ +v 20040111 1 +T 1700 1600 8 10 1 1 0 6 1 +refdes=U? +T 300 1550 9 9 1 1 0 0 1 +device=26LS31 +T 300 1950 5 10 0 0 0 0 1 +footprint=DIP16 +T 300 2150 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 2550 5 10 0 0 0 0 1 +description=Quad Differential Line Driver +T 300 2750 5 10 0 0 0 0 1 +numslots=0 +P 0 1100 300 1100 1 0 0 +{ +T 200 1150 5 8 1 1 0 6 1 +pinnumber=4 +T 200 1050 5 8 0 1 0 8 1 +pinseq=4 +T 350 1100 9 8 1 1 0 0 1 +pinlabel=G +T 350 1100 5 8 0 1 0 2 1 +pintype=in +} +P 0 700 300 700 1 0 0 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=12 +T 200 650 5 8 0 1 0 8 1 +pinseq=12 +T 350 700 9 8 1 1 0 0 1 +pinlabel=G +T 350 700 5 8 0 1 0 2 1 +pintype=in +} +L 350 824 470 824 3 0 0 0 -1 -1 +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=8 +T 1050 100 5 8 0 1 0 2 1 +pinseq=8 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1000 1800 1000 1500 1 0 0 +{ +T 1050 1600 5 8 1 1 0 0 1 +pinnumber=16 +T 1050 1600 5 8 0 1 0 2 1 +pinseq=16 +T 1000 1450 9 8 1 1 0 5 1 +pinlabel=VCC +T 1000 1300 5 8 0 1 0 5 1 +pintype=pwr +} +B 300 300 1400 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/26LS31-com.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,55 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=26LS31 +device=26LS31 +refdes=U? +footprint=DIP16 +description=Quad Differential Line Driver +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +4 in line l G +12 in line l _G_ +8 pwr line b GND +16 pwr line t VCC
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/26LS32-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,58 @@ +v 20040111 1 +L 200 1000 200 200 3 0 0 0 -1 -1 +L 200 1000 800 600 3 0 0 0 -1 -1 +T 100 0 9 10 1 1 0 0 1 +device=26LS32 +L 800 600 200 200 3 0 0 0 -1 -1 +L 300 450 300 350 3 0 0 0 -1 -1 +L 250 400 350 400 3 0 0 0 -1 -1 +L 250 800 350 800 3 0 0 0 -1 -1 +P 0 400 200 400 1 0 0 +{ +T 0 450 5 10 1 1 0 0 1 +pinnumber=2 +T 0 450 5 10 0 0 0 0 1 +pinseq=2 +T 0 450 5 10 0 0 0 0 1 +pintype=in +T 0 450 5 10 0 0 0 0 1 +pinlabel=A +} +P 0 800 200 800 1 0 0 +{ +T 0 850 5 10 1 1 0 0 1 +pinnumber=1 +T 0 850 5 10 0 0 0 0 1 +pinseq=1 +T 0 850 5 10 0 0 0 0 1 +pintype=in +T 0 850 5 10 0 0 0 0 1 +pinlabel=B +} +P 800 600 1000 600 1 0 1 +{ +T 800 650 5 10 1 1 0 0 1 +pinnumber=3 +T 800 650 5 10 0 0 0 0 1 +pinseq=3 +T 800 650 5 10 0 0 0 0 1 +pintype=out +T 800 650 5 10 0 0 0 0 1 +pinlabel=Y +} +T 200 1100 8 10 1 1 0 0 1 +refdes=U? +T 200 1300 5 10 0 0 0 0 1 +slot=1 +T 200 1700 5 10 0 0 0 0 1 +numslots=4 +T 200 1500 5 10 0 0 0 0 1 +footprint=DIP16 +T 200 1900 5 10 0 0 0 0 1 +slotdef=1:1,2,3 +T 200 2100 5 10 0 0 0 0 1 +slotdef=2:7,6,5 +T 200 2300 5 10 0 0 0 0 1 +slotdef=3:9,10,11 +T 200 2500 5 10 0 0 0 0 1 +slotdef=4:15,14,13
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/26LS32-com.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,59 @@ +v 20040111 1 +T 1700 1600 8 10 1 1 0 6 1 +refdes=U? +T 300 1550 9 9 1 1 0 0 1 +device=26LS32 +T 300 1950 5 10 0 0 0 0 1 +footprint=DIP16 +T 300 2150 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 2550 5 10 0 0 0 0 1 +description=Quad Differential Line Receiver +T 300 2750 5 10 0 0 0 0 1 +numslots=0 +P 0 1100 300 1100 1 0 0 +{ +T 200 1150 5 8 1 1 0 6 1 +pinnumber=4 +T 200 1050 5 8 0 1 0 8 1 +pinseq=4 +T 350 1100 9 8 1 1 0 0 1 +pinlabel=G +T 350 1100 5 8 0 1 0 2 1 +pintype=in +} +P 0 700 300 700 1 0 0 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=12 +T 200 650 5 8 0 1 0 8 1 +pinseq=12 +T 350 700 9 8 1 1 0 0 1 +pinlabel=G +T 350 700 5 8 0 1 0 2 1 +pintype=in +} +L 350 824 470 824 3 0 0 0 -1 -1 +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=8 +T 1050 100 5 8 0 1 0 2 1 +pinseq=8 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1000 1800 1000 1500 1 0 0 +{ +T 1050 1600 5 8 1 1 0 0 1 +pinnumber=16 +T 1050 1600 5 8 0 1 0 2 1 +pinseq=16 +T 1000 1450 9 8 1 1 0 5 1 +pinlabel=VCC +T 1000 1300 5 8 0 1 0 5 1 +pintype=pwr +} +B 300 300 1400 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/29x040-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,369 @@ +v 20040111 1 +T 2400 9700 8 10 1 1 0 6 1 +refdes=U? +T 400 9650 9 10 1 1 0 0 1 +device=29x040 +T 400 10050 5 10 0 0 0 0 1 +footprint=PLCC32 +T 400 10250 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 10450 5 10 0 0 0 0 1 +description=512Kx8 flash memory +T 400 10650 5 10 0 0 0 0 1 +numslots=0 +P 1400 9900 1400 9600 1 0 0 +{ +T 1450 9700 5 8 1 1 0 0 1 +pinnumber=32 +T 1450 9700 5 8 0 1 0 2 1 +pinseq=32 +T 1400 9550 9 8 1 1 0 5 1 +pinlabel=VCC +T 1400 9400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2700 9200 2400 9200 1 0 0 +{ +T 2500 9250 5 8 1 1 0 0 1 +pinnumber=13 +T 2500 9150 5 8 0 1 0 2 1 +pinseq=13 +T 2350 9200 9 8 1 1 0 6 1 +pinlabel=DQ0 +T 2350 9200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8800 2400 8800 1 0 0 +{ +T 2500 8850 5 8 1 1 0 0 1 +pinnumber=14 +T 2500 8750 5 8 0 1 0 2 1 +pinseq=14 +T 2350 8800 9 8 1 1 0 6 1 +pinlabel=DQ1 +T 2350 8800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8400 2400 8400 1 0 0 +{ +T 2500 8450 5 8 1 1 0 0 1 +pinnumber=15 +T 2500 8350 5 8 0 1 0 2 1 +pinseq=15 +T 2350 8400 9 8 1 1 0 6 1 +pinlabel=DQ2 +T 2350 8400 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8000 2400 8000 1 0 0 +{ +T 2500 8050 5 8 1 1 0 0 1 +pinnumber=17 +T 2500 7950 5 8 0 1 0 2 1 +pinseq=17 +T 2350 8000 9 8 1 1 0 6 1 +pinlabel=DQ3 +T 2350 8000 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7600 2400 7600 1 0 0 +{ +T 2500 7650 5 8 1 1 0 0 1 +pinnumber=18 +T 2500 7550 5 8 0 1 0 2 1 +pinseq=18 +T 2350 7600 9 8 1 1 0 6 1 +pinlabel=DQ4 +T 2350 7600 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7200 2400 7200 1 0 0 +{ +T 2500 7250 5 8 1 1 0 0 1 +pinnumber=19 +T 2500 7150 5 8 0 1 0 2 1 +pinseq=19 +T 2350 7200 9 8 1 1 0 6 1 +pinlabel=DQ5 +T 2350 7200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6800 2400 6800 1 0 0 +{ +T 2500 6850 5 8 1 1 0 0 1 +pinnumber=20 +T 2500 6750 5 8 0 1 0 2 1 +pinseq=20 +T 2350 6800 9 8 1 1 0 6 1 +pinlabel=DQ6 +T 2350 6800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6400 2400 6400 1 0 0 +{ +T 2500 6450 5 8 1 1 0 0 1 +pinnumber=21 +T 2500 6350 5 8 0 1 0 2 1 +pinseq=21 +T 2350 6400 9 8 1 1 0 6 1 +pinlabel=DQ7 +T 2350 6400 5 8 0 1 0 8 1 +pintype=tri +} +P 100 9200 400 9200 1 0 0 +{ +T 300 9250 5 8 1 1 0 6 1 +pinnumber=12 +T 300 9150 5 8 0 1 0 8 1 +pinseq=12 +T 450 9200 9 8 1 1 0 0 1 +pinlabel=A0 +T 450 9200 5 8 0 1 0 2 1 +pintype=in +} +P 100 8800 400 8800 1 0 0 +{ +T 300 8850 5 8 1 1 0 6 1 +pinnumber=11 +T 300 8750 5 8 0 1 0 8 1 +pinseq=11 +T 450 8800 9 8 1 1 0 0 1 +pinlabel=A1 +T 450 8800 5 8 0 1 0 2 1 +pintype=in +} +P 100 8400 400 8400 1 0 0 +{ +T 300 8450 5 8 1 1 0 6 1 +pinnumber=10 +T 300 8350 5 8 0 1 0 8 1 +pinseq=10 +T 450 8400 9 8 1 1 0 0 1 +pinlabel=A2 +T 450 8400 5 8 0 1 0 2 1 +pintype=in +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=9 +T 300 7950 5 8 0 1 0 8 1 +pinseq=9 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=A3 +T 450 8000 5 8 0 1 0 2 1 +pintype=in +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=8 +T 300 7550 5 8 0 1 0 8 1 +pinseq=8 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=A4 +T 450 7600 5 8 0 1 0 2 1 +pintype=in +} +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=7 +T 300 7150 5 8 0 1 0 8 1 +pinseq=7 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=A5 +T 450 7200 5 8 0 1 0 2 1 +pintype=in +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=6 +T 300 6750 5 8 0 1 0 8 1 +pinseq=6 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=A6 +T 450 6800 5 8 0 1 0 2 1 +pintype=in +} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=5 +T 300 6350 5 8 0 1 0 8 1 +pinseq=5 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=A7 +T 450 6400 5 8 0 1 0 2 1 +pintype=in +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=27 +T 300 5950 5 8 0 1 0 8 1 +pinseq=27 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=A8 +T 450 6000 5 8 0 1 0 2 1 +pintype=in +} +P 100 5600 400 5600 1 0 0 +{ +T 300 5650 5 8 1 1 0 6 1 +pinnumber=26 +T 300 5550 5 8 0 1 0 8 1 +pinseq=26 +T 450 5600 9 8 1 1 0 0 1 +pinlabel=A9 +T 450 5600 5 8 0 1 0 2 1 +pintype=in +} +P 100 5200 400 5200 1 0 0 +{ +T 300 5250 5 8 1 1 0 6 1 +pinnumber=23 +T 300 5150 5 8 0 1 0 8 1 +pinseq=23 +T 450 5200 9 8 1 1 0 0 1 +pinlabel=A10 +T 450 5200 5 8 0 1 0 2 1 +pintype=in +} +P 100 4800 400 4800 1 0 0 +{ +T 300 4850 5 8 1 1 0 6 1 +pinnumber=25 +T 300 4750 5 8 0 1 0 8 1 +pinseq=25 +T 450 4800 9 8 1 1 0 0 1 +pinlabel=A11 +T 450 4800 5 8 0 1 0 2 1 +pintype=in +} +P 100 4400 400 4400 1 0 0 +{ +T 300 4450 5 8 1 1 0 6 1 +pinnumber=4 +T 300 4350 5 8 0 1 0 8 1 +pinseq=4 +T 450 4400 9 8 1 1 0 0 1 +pinlabel=A12 +T 450 4400 5 8 0 1 0 2 1 +pintype=in +} +P 100 4000 400 4000 1 0 0 +{ +T 300 4050 5 8 1 1 0 6 1 +pinnumber=28 +T 300 3950 5 8 0 1 0 8 1 +pinseq=28 +T 450 4000 9 8 1 1 0 0 1 +pinlabel=A13 +T 450 4000 5 8 0 1 0 2 1 +pintype=in +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=29 +T 300 3550 5 8 0 1 0 8 1 +pinseq=29 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=A14 +T 450 3600 5 8 0 1 0 2 1 +pintype=in +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=3 +T 300 3150 5 8 0 1 0 8 1 +pinseq=3 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=A15 +T 450 3200 5 8 0 1 0 2 1 +pintype=in +} +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=2 +T 300 2750 5 8 0 1 0 8 1 +pinseq=2 +T 450 2800 9 8 1 1 0 0 1 +pinlabel=A16 +T 450 2800 5 8 0 1 0 2 1 +pintype=in +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=30 +T 300 2350 5 8 0 1 0 8 1 +pinseq=30 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=A17 +T 450 2400 5 8 0 1 0 2 1 +pintype=in +} +P 100 2000 400 2000 1 0 0 +{ +T 300 2050 5 8 1 1 0 6 1 +pinnumber=1 +T 300 1950 5 8 0 1 0 8 1 +pinseq=1 +T 450 2000 9 8 1 1 0 0 1 +pinlabel=A18 +T 450 2000 5 8 0 1 0 2 1 +pintype=in +} +P 100 1600 300 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=22 +T 300 1550 5 8 0 1 0 8 1 +pinseq=22 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=CE +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +V 350 1600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 1200 300 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=24 +T 300 1150 5 8 0 1 0 8 1 +pinseq=24 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=OE +T 450 1200 5 8 0 1 0 2 1 +pintype=in +} +V 350 1200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 800 300 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=31 +T 300 750 5 8 0 1 0 8 1 +pinseq=31 +T 450 800 9 8 1 1 0 0 1 +pinlabel=WE +T 450 800 5 8 0 1 0 2 1 +pintype=in +} +V 350 800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1400 100 1400 400 1 0 0 +{ +T 1450 200 5 8 1 1 0 0 1 +pinnumber=16 +T 1450 200 5 8 0 1 0 2 1 +pinseq=16 +T 1400 450 9 8 1 1 0 3 1 +pinlabel=GND +T 1400 600 5 8 0 1 0 3 1 +pintype=pwr +} +B 400 400 2000 9200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/29x040-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,83 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=yes +generate_pinseq=yes +sym_width=2000 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=29x040 +device=29x040 +refdes=U? +footprint=PLCC32 +description=512Kx8 flash memory +#documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l A18 +30 in line l A17 +2 in line l A16 +3 in line l A15 +29 in line l A14 +28 in line l A13 +4 in line l A12 +25 in line l A11 +23 in line l A10 +26 in line l A9 +27 in line l A8 +5 in line l A7 +6 in line l A6 +7 in line l A5 +8 in line l A4 +9 in line l A3 +10 in line l A2 +11 in line l A1 +12 in line l A0 +22 in dot l CE +31 in dot l WE +24 in dot l OE +21 tri line r DQ7 +20 tri line r DQ6 +19 tri line r DQ5 +18 tri line r DQ4 +17 tri line r DQ3 +15 tri line r DQ2 +14 tri line r DQ1 +13 tri line r DQ0 +32 pwr line t VCC +16 pwr line b GND
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/5V-plus-analog.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +v 20031231 1 +P 200 0 200 200 1 0 0 +{ +T 250 50 5 6 0 1 0 0 1 +pinnumber=1 +T 250 50 5 6 0 0 0 0 1 +pinseq=1 +T 250 50 5 6 0 1 0 0 1 +pinlabel=1 +T 250 50 5 6 0 1 0 0 1 +pintype=pwr +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 200 250 9 8 1 0 0 3 1 ++5VAA +T 300 0 8 8 0 0 0 0 1 +net=+5VAA:1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/5V-plus-digital.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +v 20031231 1 +P 200 0 200 200 1 0 0 +{ +T 250 50 5 6 0 1 0 0 1 +pinnumber=1 +T 250 50 5 6 0 0 0 0 1 +pinseq=1 +T 250 50 5 6 0 1 0 0 1 +pinlabel=1 +T 250 50 5 6 0 1 0 0 1 +pintype=pwr +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 200 250 9 8 1 0 0 3 1 ++5VDD +T 300 0 8 8 0 0 0 0 1 +net=+5VDD:1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7400-1-np.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,61 @@ +v 20031231 1 +L 300 200 300 800 3 0 0 0 -1 -1 +T 300 0 9 8 1 1 0 0 1 +device=7400 +L 300 800 700 800 3 0 0 0 -1 -1 +T 500 1100 5 10 0 0 0 0 1 +slot=1 +T 500 1300 5 10 0 0 0 0 1 +numslots=4 +T 500 1500 5 10 0 0 0 0 1 +slotdef=1:1,2,3 +T 500 1700 5 10 0 0 0 0 1 +slotdef=2:4,5,6 +T 500 1900 5 10 0 0 0 0 1 +slotdef=3:9,10,8 +T 500 2100 5 10 0 0 0 0 1 +slotdef=4:12,13,11 +L 300 200 700 200 3 0 0 0 -1 -1 +A 700 500 300 270 180 3 0 0 0 -1 -1 +V 1050 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1100 500 1300 500 1 0 1 +{ +T 1100 550 5 8 1 1 0 0 1 +pinnumber=3 +T 1100 450 5 8 0 1 0 2 1 +pinseq=3 +T 950 500 9 8 0 1 0 6 1 +pinlabel=Y +T 950 500 5 8 0 1 0 8 1 +pintype=out +} +P 300 300 0 300 1 0 1 +{ +T 200 350 5 8 1 1 0 6 1 +pinnumber=2 +T 200 250 5 8 0 1 0 8 1 +pinseq=2 +T 350 300 9 8 0 1 0 0 1 +pinlabel=B +T 350 300 5 8 0 1 0 2 1 +pintype=in +} +P 300 700 0 700 1 0 1 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=1 +T 200 650 5 8 0 1 0 8 1 +pinseq=1 +T 350 700 9 8 0 1 0 0 1 +pinlabel=A +T 350 700 5 8 0 1 0 2 1 +pintype=in +} +T 300 900 8 10 1 1 0 0 1 +refdes=U? +T 500 2250 5 10 0 0 0 0 1 +footprint=DIP14 +T 500 2450 5 10 0 0 0 0 1 +description=4 NAND gates with 2 inputs +T 500 2650 5 10 0 0 0 0 1 +documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7400-2-np.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,61 @@ +v 20031231 1 +L 260 200 600 200 3 0 0 0 -1 -1 +L 260 800 600 800 3 0 0 0 -1 -1 +T 400 1100 5 10 0 0 0 0 1 +numslots=4 +T 400 1300 5 10 0 0 0 0 1 +slotdef=1:1,2,3 +T 400 1500 5 10 0 0 0 0 1 +slotdef=2:4,5,6 +T 400 1700 5 10 0 0 0 0 1 +slotdef=3:9,10,8 +T 400 1900 5 10 0 0 0 0 1 +slotdef=4:12,13,11 +T 300 0 9 8 1 1 0 0 1 +device=7400 +A 0 500 400 312 97 3 0 0 0 -1 -1 +V 250 700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 250 300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 988 500 1300 500 1 0 1 +{ +T 1100 550 5 8 1 1 0 0 1 +pinnumber=3 +T 1100 450 5 8 0 1 0 2 1 +pinseq=3 +T 950 500 9 8 0 1 0 6 1 +pinlabel=Y +T 950 500 5 8 0 1 0 8 1 +pintype=out +} +P 200 700 0 700 1 0 1 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=1 +T 200 650 5 8 0 1 0 8 1 +pinseq=1 +T 350 700 9 8 0 1 0 0 1 +pinlabel=A +T 350 700 5 8 0 1 0 2 1 +pintype=in +} +P 200 300 0 300 1 0 1 +{ +T 200 350 5 8 1 1 0 6 1 +pinnumber=2 +T 200 250 5 8 0 1 0 8 1 +pinseq=2 +T 350 300 9 8 0 1 0 0 1 +pinlabel=B +T 350 300 5 8 0 1 0 2 1 +pintype=in +} +A 600 600 400 270 76 3 0 0 0 -1 -1 +A 600 400 400 14 76 3 0 0 0 -1 -1 +T 300 900 8 10 1 1 0 0 1 +refdes=U? +T 400 2050 5 10 0 0 0 0 1 +footprint=DIP14 +T 400 2250 5 10 0 0 0 0 1 +description=4 NAND gates with 2 inputs +T 400 2450 5 10 0 0 0 0 1 +documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7400-pwr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,36 @@ +v 20040111 1 +T 900 1000 8 10 1 1 0 6 1 +refdes=U? +T 150 300 9 10 1 1 90 0 1 +device=7400 +T 200 1750 5 10 0 0 0 0 1 +footprint=DIP14 +T 200 2050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 200 2350 5 10 0 0 0 0 1 +description=7400 quad NAND gate power & ground pins +T 200 2650 5 10 0 0 0 0 1 +numslots=0 +P 400 1400 400 1100 1 0 0 +{ +T 450 1200 5 8 1 1 0 0 1 +pinnumber=14 +T 450 1200 5 8 0 1 0 2 1 +pinseq=14 +T 400 1050 9 8 1 1 0 5 1 +pinlabel=VCC +T 400 900 5 8 0 1 0 5 1 +pintype=pwr +} +P 400 0 400 300 1 0 0 +{ +T 450 100 5 8 1 1 0 0 1 +pinnumber=7 +T 450 100 5 8 0 1 0 2 1 +pinseq=7 +T 400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 400 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 200 300 400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7404-1-np.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,58 @@ +v 20031231 1 +L 300 800 800 500 3 0 0 0 -1 -1 +T 600 1100 5 10 0 0 0 0 1 +slot=1 +T 600 1300 5 10 0 0 0 0 1 +numslots=6 +T 600 1500 5 10 0 0 0 0 1 +slotdef=1:1,2 +T 600 1700 5 10 0 0 0 0 1 +slotdef=2:3,4 +T 600 1900 5 10 0 0 0 0 1 +slotdef=3:5,6 +T 600 2100 5 10 0 0 0 0 1 +slotdef=4:9,8 +T 600 2300 5 10 0 0 0 0 1 +slotdef=5:11,10 +T 600 2500 5 10 0 0 0 0 1 +slotdef=6:13,12 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +V 850 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=1 +T 200 450 5 8 0 1 0 8 1 +pinseq=1 +T 350 500 9 8 0 1 0 0 1 +pinlabel=A +T 350 500 5 8 0 1 0 2 1 +pintype=in +} +P 1100 500 900 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=2 +T 900 450 5 8 0 1 0 2 1 +pinseq=2 +T 750 500 9 8 0 1 0 6 1 +pinlabel=Y +T 750 500 5 8 0 1 0 8 1 +pintype=out +} +T 300 0 9 8 1 1 0 0 1 +device=7404 +T 300 900 8 10 1 1 0 0 1 +refdes=U? +T 600 2900 5 10 0 0 0 0 1 +pins=14 +T 600 2700 5 10 0 0 0 0 1 +class=IC +T 600 3500 5 10 0 0 0 0 1 +footprint=DIP14 +T 600 3700 5 10 0 0 0 0 1 +description=6 NOT gates +T 600 3900 5 10 0 0 0 0 1 +documentation=http://www-s.ti.com/sc/ds/sn74hc04.pdf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7404-2-np.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,54 @@ +v 20031231 1 +L 300 800 800 500 3 0 0 0 -1 -1 +T 600 1100 5 10 0 0 0 0 1 +slot=1 +T 600 1300 5 10 0 0 0 0 1 +numslots=6 +T 600 1500 5 10 0 0 0 0 1 +slotdef=1:1,2 +T 600 1700 5 10 0 0 0 0 1 +slotdef=2:3,4 +T 600 1900 5 10 0 0 0 0 1 +slotdef=3:5,6 +T 600 2100 5 10 0 0 0 0 1 +slotdef=4:9,8 +T 600 2300 5 10 0 0 0 0 1 +slotdef=5:11,10 +T 600 2500 5 10 0 0 0 0 1 +slotdef=6:13,12 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +V 250 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 300 0 9 8 1 1 0 0 1 +device=7404 +P 1100 500 800 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=2 +T 900 450 5 8 0 1 0 2 1 +pinseq=2 +T 750 500 9 8 0 1 0 6 1 +pinlabel=Y +T 750 500 5 8 0 1 0 8 1 +pintype=out +} +P 200 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=1 +T 200 450 5 8 0 1 0 8 1 +pinseq=1 +T 350 500 9 8 0 1 0 0 1 +pinlabel=A +T 350 500 5 8 0 1 0 2 1 +pintype=in +} +T 300 900 8 10 1 1 0 0 1 +refdes=U? +T 600 2700 5 10 0 0 0 0 1 +footprint=DIP14 +T 600 2900 5 10 0 0 0 0 1 +description=6 NOT gates +T 600 3500 5 10 0 0 0 0 1 +documentation=http://www-s.ti.com/sc/ds/sn74hc04.pdf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7404-pwr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,36 @@ +v 20040111 1 +T 900 1000 8 10 1 1 0 6 1 +refdes=U? +T 150 300 9 10 1 1 90 0 1 +device=7404 +T 200 1750 5 10 0 0 0 0 1 +footprint=DIP14 +T 200 2050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 200 2350 5 10 0 0 0 0 1 +description=7404 hex invertor power & ground pins +T 200 2650 5 10 0 0 0 0 1 +numslots=0 +P 400 1400 400 1100 1 0 0 +{ +T 450 1200 5 8 1 1 0 0 1 +pinnumber=14 +T 450 1200 5 8 0 1 0 2 1 +pinseq=14 +T 400 1050 9 8 1 1 0 5 1 +pinlabel=VCC +T 400 900 5 8 0 1 0 5 1 +pintype=pwr +} +P 400 0 400 300 1 0 0 +{ +T 450 100 5 8 1 1 0 0 1 +pinnumber=7 +T 450 100 5 8 0 1 0 2 1 +pinseq=7 +T 400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 400 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 200 300 400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7405-1-np.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,55 @@ +v 20031231 1 +L 300 800 800 500 3 0 0 0 -1 -1 +T 300 0 9 8 1 1 0 0 1 +device=7405 +T 600 1100 5 10 0 0 0 0 1 +slot=1 +T 600 1300 5 10 0 0 0 0 1 +numslots=6 +T 600 1500 5 10 0 0 0 0 1 +slotdef=1:1,2 +T 600 1700 5 10 0 0 0 0 1 +slotdef=2:3,4 +T 600 1900 5 10 0 0 0 0 1 +slotdef=3:5,6 +T 600 2100 5 10 0 0 0 0 1 +slotdef=4:9,8 +T 600 2300 5 10 0 0 0 0 1 +slotdef=5:11,10 +T 600 2500 5 10 0 0 0 0 1 +slotdef=6:13,12 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +V 850 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=1 +T 200 450 5 8 0 1 0 8 1 +pinseq=1 +T 350 500 9 8 0 1 0 0 1 +pinlabel=A +T 350 500 5 8 0 1 0 2 1 +pintype=in +} +P 1100 500 900 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=2 +T 900 450 5 8 0 1 0 2 1 +pinseq=2 +T 750 500 9 8 0 1 0 6 1 +pinlabel=Y +T 750 500 5 8 0 1 0 8 1 +pintype=oc +} +L 488 313 619 606 3 0 0 0 -1 -1 +T 300 900 8 10 1 1 0 0 1 +refdes=U? +T 600 2700 5 10 0 0 0 0 1 +footprint=DIP14 +T 600 2900 5 10 0 0 0 0 1 +description=6 NOT gates with open collector outputs +T 600 3500 5 10 0 0 0 0 1 +documentation=http://www-s.ti.com/sc/ds/sn74hc05.pdf
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7405-pwr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,36 @@ +v 20040111 1 +T 900 1000 8 10 1 1 0 6 1 +refdes=U? +T 150 300 9 10 1 1 90 0 1 +device=7405 +T 200 1750 5 10 0 0 0 0 1 +footprint=DIP14 +T 200 2050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 200 2350 5 10 0 0 0 0 1 +description=7405 hex OC invertor power & ground pins +T 200 2650 5 10 0 0 0 0 1 +numslots=0 +P 400 1400 400 1100 1 0 0 +{ +T 450 1200 5 8 1 1 0 0 1 +pinnumber=14 +T 450 1200 5 8 0 1 0 2 1 +pinseq=14 +T 400 1050 9 8 1 1 0 5 1 +pinlabel=VCC +T 400 900 5 8 0 1 0 5 1 +pintype=pwr +} +P 400 0 400 300 1 0 0 +{ +T 450 100 5 8 1 1 0 0 1 +pinnumber=7 +T 450 100 5 8 0 1 0 2 1 +pinseq=7 +T 400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 400 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 200 300 400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7407-1-np.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,52 @@ +v 20031231 1 +L 300 800 800 500 3 0 0 0 -1 -1 +T 600 1100 5 10 0 0 0 0 1 +slot=1 +T 600 1300 5 10 0 0 0 0 1 +numslots=6 +T 600 1500 5 10 0 0 0 0 1 +slotdef=1:1,2 +T 600 1700 5 10 0 0 0 0 1 +slotdef=2:3,4 +T 600 1900 5 10 0 0 0 0 1 +slotdef=3:5,6 +T 600 2100 5 10 0 0 0 0 1 +slotdef=4:9,8 +T 600 2300 5 10 0 0 0 0 1 +slotdef=5:11,10 +T 600 2500 5 10 0 0 0 0 1 +slotdef=6:13,12 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=1 +T 200 450 5 8 0 1 0 8 1 +pinseq=1 +T 350 500 9 8 0 1 0 0 1 +pinlabel=A +T 350 500 5 8 0 1 0 2 1 +pintype=in +} +T 300 0 9 8 1 1 0 0 1 +device=7407 +P 1100 500 800 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=2 +T 900 450 5 8 0 1 0 2 1 +pinseq=2 +T 750 500 9 8 0 1 0 6 1 +pinlabel=Y +T 750 500 5 8 0 1 0 8 1 +pintype=oc +} +L 488 313 619 606 3 0 0 0 -1 -1 +T 300 900 8 10 1 1 0 0 1 +refdes=U? +T 600 2700 5 10 0 0 0 0 1 +footprint=DIP14 +T 600 2900 5 10 0 0 0 0 1 +description=6 noninverting drivers with open collector outputs
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7407-pwr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,36 @@ +v 20040111 1 +T 900 1000 8 10 1 1 0 6 1 +refdes=U? +T 150 300 9 10 1 1 90 0 1 +device=7407 +T 200 1750 5 10 0 0 0 0 1 +footprint=DIP14 +T 200 2050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 200 2350 5 10 0 0 0 0 1 +description=7407 hex OC driver power & ground pins +T 200 2650 5 10 0 0 0 0 1 +numslots=0 +P 400 1400 400 1100 1 0 0 +{ +T 450 1200 5 8 1 1 0 0 1 +pinnumber=14 +T 450 1200 5 8 0 1 0 2 1 +pinseq=14 +T 400 1050 9 8 1 1 0 5 1 +pinlabel=VCC +T 400 900 5 8 0 1 0 5 1 +pintype=pwr +} +P 400 0 400 300 1 0 0 +{ +T 450 100 5 8 1 1 0 0 1 +pinnumber=7 +T 450 100 5 8 0 1 0 2 1 +pinseq=7 +T 400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 400 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 200 300 400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7474-4.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,91 @@ +v 20041228 1 +P 0 1400 300 1400 1 0 0 +{ +T 200 1450 5 8 1 1 0 6 1 +pinnumber=2 +T 200 1350 5 8 0 1 0 8 1 +pinseq=1 +T 350 1400 9 8 1 1 0 0 1 +pinlabel=D +T 350 1400 5 8 0 1 0 2 1 +pintype=in +} +P 2000 1400 1700 1400 1 0 0 +{ +T 1800 1450 5 8 1 1 0 0 1 +pinnumber=5 +T 1800 1350 5 8 0 1 0 2 1 +pinseq=2 +T 1650 1400 9 8 1 1 0 6 1 +pinlabel=Q +T 1650 1400 5 8 0 1 0 8 1 +pintype=out +} +P 0 1000 200 1000 1 0 0 +{ +T 200 1050 5 8 1 1 0 6 1 +pinnumber=1 +T 200 950 5 8 0 1 0 8 1 +pinseq=3 +T 350 1000 9 8 1 1 0 0 1 +pinlabel=CLR +T 350 1000 5 8 0 1 0 2 1 +pintype=in +} +V 250 1000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 2000 1000 1800 1000 1 0 0 +{ +T 1800 1050 5 8 1 1 0 0 1 +pinnumber=6 +T 1800 950 5 8 0 1 0 2 1 +pinseq=4 +T 1650 1000 9 8 1 1 0 6 1 +pinlabel=Q +T 1650 1000 5 8 0 1 0 8 1 +pintype=out +} +P 0 600 200 600 1 0 0 +{ +T 200 650 5 8 1 1 0 6 1 +pinnumber=4 +T 200 550 5 8 0 1 0 8 1 +pinseq=5 +T 350 600 9 8 1 1 0 0 1 +pinlabel=PRE +T 350 600 5 8 0 1 0 2 1 +pintype=in +} +V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 0 200 300 200 1 0 0 +{ +T 200 250 5 8 1 1 0 6 1 +pinnumber=3 +T 200 150 5 8 0 1 0 8 1 +pinseq=6 +T 375 200 9 8 1 1 0 0 1 +pinlabel=CLK +T 375 200 5 8 0 1 0 2 1 +pintype=clk +} +V 1750 1000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 300 0 1400 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 2100 1600 8 10 0 0 0 0 1 +footprint=DIP14 +T 2100 1000 8 10 0 0 0 0 1 +numslots=2 +T 2100 1200 8 10 0 0 0 0 1 +slotdef=1:2,5,1,6,4,3 +T 2100 1400 8 10 0 0 0 0 1 +slotdef=2:12,9,13,8,10,11 +T 1700 1800 8 10 1 1 0 6 1 +refdes=U? +T 2100 1800 8 10 0 0 0 0 1 +description=2 D-flip-flops with preset and clear +L 300 250 375 200 3 0 0 0 -1 -1 +L 375 200 300 150 3 0 0 0 -1 -1 +T 2100 800 8 10 0 0 0 0 1 +slot=1 +T 2100 2000 8 10 0 0 0 0 1 +documentation=http://www-s.ti.com/sc/ds/sn74hc74.pdf +T 300 1750 8 10 1 1 0 0 1 +device=7474
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/7474-pwr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,36 @@ +v 20040111 1 +T 900 1000 8 10 1 1 0 6 1 +refdes=U? +T 150 300 9 10 1 1 90 0 1 +device=7474 +T 200 1750 5 10 0 0 0 0 1 +footprint=DIP14 +T 200 2050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 200 2350 5 10 0 0 0 0 1 +description=7474 dual flip-flop power & ground pins +T 200 2650 5 10 0 0 0 0 1 +numslots=0 +P 400 1400 400 1100 1 0 0 +{ +T 450 1200 5 8 1 1 0 0 1 +pinnumber=14 +T 450 1200 5 8 0 1 0 2 1 +pinseq=14 +T 400 1050 9 8 1 1 0 5 1 +pinlabel=VCC +T 400 900 5 8 0 1 0 5 1 +pintype=pwr +} +P 400 0 400 300 1 0 0 +{ +T 450 100 5 8 1 1 0 0 1 +pinnumber=7 +T 450 100 5 8 0 1 0 2 1 +pinseq=7 +T 400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 400 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 200 300 400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/ADG704-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,124 @@ +v 20040111 1 +T 2300 2800 8 10 1 1 0 6 1 +refdes=U? +T 300 2750 9 10 1 0 0 0 1 +ADG704 +T 300 2950 5 10 0 0 0 0 1 +device=ADG704 +T 300 3150 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 3350 5 10 0 0 0 0 1 +description=4-to-1 CMOS analog MUX +T 300 3550 5 10 0 0 0 0 1 +numslots=0 +P 0 2300 300 2300 1 0 0 +{ +T 200 2350 5 8 1 1 0 6 1 +pinnumber=2 +T 200 2250 5 8 0 1 0 8 1 +pinseq=2 +T 350 2300 9 8 1 1 0 0 1 +pinlabel=S1 +T 350 2300 5 8 0 1 0 2 1 +pintype=in +} +P 0 1900 300 1900 1 0 0 +{ +T 200 1950 5 8 1 1 0 6 1 +pinnumber=9 +T 200 1850 5 8 0 1 0 8 1 +pinseq=9 +T 350 1900 9 8 1 1 0 0 1 +pinlabel=S2 +T 350 1900 5 8 0 1 0 2 1 +pintype=in +} +P 0 1500 300 1500 1 0 0 +{ +T 200 1550 5 8 1 1 0 6 1 +pinnumber=4 +T 200 1450 5 8 0 1 0 8 1 +pinseq=4 +T 350 1500 9 8 1 1 0 0 1 +pinlabel=S3 +T 350 1500 5 8 0 1 0 2 1 +pintype=in +} +P 0 1100 300 1100 1 0 0 +{ +T 200 1150 5 8 1 1 0 6 1 +pinnumber=7 +T 200 1050 5 8 0 1 0 8 1 +pinseq=7 +T 350 1100 9 8 1 1 0 0 1 +pinlabel=S4 +T 350 1100 5 8 0 1 0 2 1 +pintype=in +} +P 2600 2300 2300 2300 1 0 0 +{ +T 2400 2350 5 8 1 1 0 0 1 +pinnumber=8 +T 2400 2250 5 8 0 1 0 2 1 +pinseq=8 +T 2250 2300 9 8 1 1 0 6 1 +pinlabel=D +T 2250 2300 5 8 0 1 0 8 1 +pintype=out +} +P 2600 1500 2300 1500 1 0 0 +{ +T 2400 1550 5 8 1 1 0 0 1 +pinnumber=1 +T 2400 1450 5 8 0 1 0 2 1 +pinseq=1 +T 2250 1500 9 8 1 1 0 6 1 +pinlabel=A0 +T 2250 1500 5 8 0 1 0 8 1 +pintype=in +} +P 2600 1100 2300 1100 1 0 0 +{ +T 2400 1150 5 8 1 1 0 0 1 +pinnumber=10 +T 2400 1050 5 8 0 1 0 2 1 +pinseq=10 +T 2250 1100 9 8 1 1 0 6 1 +pinlabel=A1 +T 2250 1100 5 8 0 1 0 8 1 +pintype=in +} +P 2600 700 2300 700 1 0 0 +{ +T 2400 750 5 8 1 1 0 0 1 +pinnumber=5 +T 2400 650 5 8 0 1 0 2 1 +pinseq=5 +T 2250 700 9 8 1 1 0 6 1 +pinlabel=EN +T 2250 700 5 8 0 1 0 8 1 +pintype=in +} +P 1300 0 1300 300 1 0 0 +{ +T 1350 100 5 8 1 1 0 0 1 +pinnumber=3 +T 1350 100 5 8 0 1 0 2 1 +pinseq=3 +T 1300 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1300 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1300 3000 1300 2700 1 0 0 +{ +T 1350 2800 5 8 1 1 0 0 1 +pinnumber=6 +T 1350 2800 5 8 0 1 0 2 1 +pinseq=6 +T 1300 2650 9 8 1 1 0 5 1 +pinlabel=VDD +T 1300 2500 5 8 0 1 0 5 1 +pintype=pwr +} +B 300 300 2000 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/ADG704-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,64 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=2000 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=ADG704 +device=ADG704 +refdes=U? +#footprint= +description=4-to-1 CMOS analog MUX +#documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 in line l S1 +9 in line l S2 +4 in line l S3 +7 in line l S4 + +8 out line r D +1000 pas line r DUMMY +1 in line r A0 +10 in line r A1 +5 in line r EN + +3 pwr line b GND +6 pwr line t VDD
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/ADM709-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,50 @@ +v 20040111 1 +T 1800 1200 8 10 1 1 0 6 1 +refdes=U? +T 0 1150 9 10 1 0 0 0 1 +ADM709 +T 0 1350 5 10 0 0 0 0 1 +device=ADM709 +T 0 1550 5 10 0 0 0 0 1 +footprint=SO8 +T 0 1750 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 0 2150 5 10 0 0 0 0 1 +description=Power supply monitor and reset generator +T 0 2350 5 10 0 0 0 0 1 +numslots=0 +P 900 1400 900 1100 1 0 0 +{ +T 950 1200 5 8 1 1 0 0 1 +pinnumber=2 +T 950 1200 5 8 0 1 0 2 1 +pinseq=2 +T 900 1050 9 8 1 1 0 5 1 +pinlabel=Vcc +T 900 900 5 8 0 1 0 5 1 +pintype=pwr +} +P 900 0 900 300 1 0 0 +{ +T 950 100 5 8 1 1 0 0 1 +pinnumber=3 +T 950 100 5 8 0 1 0 2 1 +pinseq=3 +T 900 350 9 8 1 1 0 3 1 +pinlabel=GND +T 900 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 2100 700 1800 700 1 0 0 +{ +T 1900 750 5 8 1 1 0 0 1 +pinnumber=7 +T 1900 650 5 8 0 1 0 2 1 +pinseq=7 +T 1750 700 9 8 1 1 0 6 1 +pinlabel=RESET +T 1750 700 5 8 0 1 0 8 1 +pintype=out +} +L 1222 824 1750 824 3 0 0 0 -1 -1 +B 0 300 1800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/ADM709-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,54 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=ADM709 +device=ADM709 +refdes=U? +footprint=SO8 +description=Power supply monitor and reset generator +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 pwr line t Vcc +3 pwr line b GND +7 out line r _RESET_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/ADP3303-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,106 @@ +v 20040111 1 +T 1700 2800 8 10 1 1 0 6 1 +refdes=U? +T 300 2750 9 10 1 0 0 0 1 +ADP3303 +T 300 2950 5 10 0 0 0 0 1 +device=ADP3303 +T 300 3150 5 10 0 0 0 0 1 +footprint=SO8 +T 300 3350 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 3750 5 10 0 0 0 0 1 +description=Linear Regulator +T 300 3950 5 10 0 0 0 0 1 +numslots=0 +P 0 1900 300 1900 1 0 0 +{ +T 200 1950 5 8 1 1 0 6 1 +pinnumber=7 +T 200 1850 5 8 0 1 0 8 1 +pinseq=7 +T 350 1900 9 8 1 1 0 0 1 +pinlabel=IN +T 350 1900 5 8 0 1 0 2 1 +pintype=in +} +P 0 1500 300 1500 1 0 0 +{ +T 200 1550 5 8 1 1 0 6 1 +pinnumber=8 +T 200 1450 5 8 0 1 0 8 1 +pinseq=8 +T 350 1500 9 8 1 1 0 0 1 +pinlabel=IN +T 350 1500 5 8 0 1 0 2 1 +pintype=in +} +P 0 700 200 700 1 0 0 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=5 +T 200 650 5 8 0 1 0 8 1 +pinseq=5 +T 350 700 9 8 1 1 0 0 1 +pinlabel=SD +T 350 700 5 8 0 1 0 2 1 +pintype=in +} +V 250 700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 2000 2300 1700 2300 1 0 0 +{ +T 1800 2350 5 8 1 1 0 0 1 +pinnumber=3 +T 1800 2250 5 8 0 1 0 2 1 +pinseq=3 +T 1650 2300 9 8 1 1 0 6 1 +pinlabel=NR +T 1650 2300 5 8 0 1 0 8 1 +pintype=pas +} +P 2000 1900 1700 1900 1 0 0 +{ +T 1800 1950 5 8 1 1 0 0 1 +pinnumber=1 +T 1800 1850 5 8 0 1 0 2 1 +pinseq=1 +T 1650 1900 9 8 1 1 0 6 1 +pinlabel=OUT +T 1650 1900 5 8 0 1 0 8 1 +pintype=out +} +P 2000 1500 1700 1500 1 0 0 +{ +T 1800 1550 5 8 1 1 0 0 1 +pinnumber=2 +T 1800 1450 5 8 0 1 0 2 1 +pinseq=2 +T 1650 1500 9 8 1 1 0 6 1 +pinlabel=OUT +T 1650 1500 5 8 0 1 0 8 1 +pintype=out +} +P 2000 700 1800 700 1 0 0 +{ +T 1800 750 5 8 1 1 0 0 1 +pinnumber=6 +T 1800 650 5 8 0 1 0 2 1 +pinseq=6 +T 1650 700 9 8 1 1 0 6 1 +pinlabel=ERR +T 1650 700 5 8 0 1 0 8 1 +pintype=out +} +V 1750 700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=4 +T 1050 100 5 8 0 1 0 2 1 +pinseq=4 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 300 300 1400 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/ADP3303-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,64 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=1400 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=ADP3303 +device=ADP3303 +refdes=U? +footprint=SO8 +description=Linear Regulator +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1001 pas line l DUMMY +7 in line l IN +8 in line l IN +1002 pas line l DUMMY +5 in dot l SD + +3 pas line r NR +1 out line r OUT +2 out line r OUT +1003 pas line r DUMMY +6 out dot r ERR + +4 pwr line b GND
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/CY62148B-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,369 @@ +v 20040111 1 +T 2400 9700 8 10 1 1 0 6 1 +refdes=U? +T 400 9650 9 9 1 0 0 0 1 +CY62148B +T 400 9850 5 10 0 0 0 0 1 +device=CY62148B +T 400 10050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 10250 5 10 0 0 0 0 1 +description=512Kx8 static RAM +T 400 10450 5 10 0 0 0 0 1 +numslots=0 +P 1400 9900 1400 9600 1 0 0 +{ +T 1450 9700 5 8 1 1 0 0 1 +pinnumber=32 +T 1450 9700 5 8 0 1 0 2 1 +pinseq=32 +T 1400 9550 9 8 1 1 0 5 1 +pinlabel=VCC +T 1400 9400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2700 9200 2400 9200 1 0 0 +{ +T 2500 9250 5 8 1 1 0 0 1 +pinnumber=13 +T 2500 9150 5 8 0 1 0 2 1 +pinseq=13 +T 2350 9200 9 8 1 1 0 6 1 +pinlabel=DQ0 +T 2350 9200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8800 2400 8800 1 0 0 +{ +T 2500 8850 5 8 1 1 0 0 1 +pinnumber=14 +T 2500 8750 5 8 0 1 0 2 1 +pinseq=14 +T 2350 8800 9 8 1 1 0 6 1 +pinlabel=DQ1 +T 2350 8800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8400 2400 8400 1 0 0 +{ +T 2500 8450 5 8 1 1 0 0 1 +pinnumber=15 +T 2500 8350 5 8 0 1 0 2 1 +pinseq=15 +T 2350 8400 9 8 1 1 0 6 1 +pinlabel=DQ2 +T 2350 8400 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8000 2400 8000 1 0 0 +{ +T 2500 8050 5 8 1 1 0 0 1 +pinnumber=17 +T 2500 7950 5 8 0 1 0 2 1 +pinseq=17 +T 2350 8000 9 8 1 1 0 6 1 +pinlabel=DQ3 +T 2350 8000 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7600 2400 7600 1 0 0 +{ +T 2500 7650 5 8 1 1 0 0 1 +pinnumber=18 +T 2500 7550 5 8 0 1 0 2 1 +pinseq=18 +T 2350 7600 9 8 1 1 0 6 1 +pinlabel=DQ4 +T 2350 7600 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7200 2400 7200 1 0 0 +{ +T 2500 7250 5 8 1 1 0 0 1 +pinnumber=19 +T 2500 7150 5 8 0 1 0 2 1 +pinseq=19 +T 2350 7200 9 8 1 1 0 6 1 +pinlabel=DQ5 +T 2350 7200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6800 2400 6800 1 0 0 +{ +T 2500 6850 5 8 1 1 0 0 1 +pinnumber=20 +T 2500 6750 5 8 0 1 0 2 1 +pinseq=20 +T 2350 6800 9 8 1 1 0 6 1 +pinlabel=DQ6 +T 2350 6800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6400 2400 6400 1 0 0 +{ +T 2500 6450 5 8 1 1 0 0 1 +pinnumber=21 +T 2500 6350 5 8 0 1 0 2 1 +pinseq=21 +T 2350 6400 9 8 1 1 0 6 1 +pinlabel=DQ7 +T 2350 6400 5 8 0 1 0 8 1 +pintype=tri +} +P 100 9200 400 9200 1 0 0 +{ +T 300 9250 5 8 1 1 0 6 1 +pinnumber=12 +T 300 9150 5 8 0 1 0 8 1 +pinseq=12 +T 450 9200 9 8 1 1 0 0 1 +pinlabel=A0 +T 450 9200 5 8 0 1 0 2 1 +pintype=in +} +P 100 8800 400 8800 1 0 0 +{ +T 300 8850 5 8 1 1 0 6 1 +pinnumber=11 +T 300 8750 5 8 0 1 0 8 1 +pinseq=11 +T 450 8800 9 8 1 1 0 0 1 +pinlabel=A1 +T 450 8800 5 8 0 1 0 2 1 +pintype=in +} +P 100 8400 400 8400 1 0 0 +{ +T 300 8450 5 8 1 1 0 6 1 +pinnumber=10 +T 300 8350 5 8 0 1 0 8 1 +pinseq=10 +T 450 8400 9 8 1 1 0 0 1 +pinlabel=A2 +T 450 8400 5 8 0 1 0 2 1 +pintype=in +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=9 +T 300 7950 5 8 0 1 0 8 1 +pinseq=9 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=A3 +T 450 8000 5 8 0 1 0 2 1 +pintype=in +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=8 +T 300 7550 5 8 0 1 0 8 1 +pinseq=8 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=A4 +T 450 7600 5 8 0 1 0 2 1 +pintype=in +} +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=7 +T 300 7150 5 8 0 1 0 8 1 +pinseq=7 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=A5 +T 450 7200 5 8 0 1 0 2 1 +pintype=in +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=6 +T 300 6750 5 8 0 1 0 8 1 +pinseq=6 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=A6 +T 450 6800 5 8 0 1 0 2 1 +pintype=in +} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=5 +T 300 6350 5 8 0 1 0 8 1 +pinseq=5 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=A7 +T 450 6400 5 8 0 1 0 2 1 +pintype=in +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=27 +T 300 5950 5 8 0 1 0 8 1 +pinseq=27 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=A8 +T 450 6000 5 8 0 1 0 2 1 +pintype=in +} +P 100 5600 400 5600 1 0 0 +{ +T 300 5650 5 8 1 1 0 6 1 +pinnumber=26 +T 300 5550 5 8 0 1 0 8 1 +pinseq=26 +T 450 5600 9 8 1 1 0 0 1 +pinlabel=A9 +T 450 5600 5 8 0 1 0 2 1 +pintype=in +} +P 100 5200 400 5200 1 0 0 +{ +T 300 5250 5 8 1 1 0 6 1 +pinnumber=23 +T 300 5150 5 8 0 1 0 8 1 +pinseq=23 +T 450 5200 9 8 1 1 0 0 1 +pinlabel=A10 +T 450 5200 5 8 0 1 0 2 1 +pintype=in +} +P 100 4800 400 4800 1 0 0 +{ +T 300 4850 5 8 1 1 0 6 1 +pinnumber=25 +T 300 4750 5 8 0 1 0 8 1 +pinseq=25 +T 450 4800 9 8 1 1 0 0 1 +pinlabel=A11 +T 450 4800 5 8 0 1 0 2 1 +pintype=in +} +P 100 4400 400 4400 1 0 0 +{ +T 300 4450 5 8 1 1 0 6 1 +pinnumber=4 +T 300 4350 5 8 0 1 0 8 1 +pinseq=4 +T 450 4400 9 8 1 1 0 0 1 +pinlabel=A12 +T 450 4400 5 8 0 1 0 2 1 +pintype=in +} +P 100 4000 400 4000 1 0 0 +{ +T 300 4050 5 8 1 1 0 6 1 +pinnumber=28 +T 300 3950 5 8 0 1 0 8 1 +pinseq=28 +T 450 4000 9 8 1 1 0 0 1 +pinlabel=A13 +T 450 4000 5 8 0 1 0 2 1 +pintype=in +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=3 +T 300 3550 5 8 0 1 0 8 1 +pinseq=3 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=A14 +T 450 3600 5 8 0 1 0 2 1 +pintype=in +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=31 +T 300 3150 5 8 0 1 0 8 1 +pinseq=31 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=A15 +T 450 3200 5 8 0 1 0 2 1 +pintype=in +} +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=2 +T 300 2750 5 8 0 1 0 8 1 +pinseq=2 +T 450 2800 9 8 1 1 0 0 1 +pinlabel=A16 +T 450 2800 5 8 0 1 0 2 1 +pintype=in +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=1 +T 300 2350 5 8 0 1 0 8 1 +pinseq=1 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=A17 +T 450 2400 5 8 0 1 0 2 1 +pintype=in +} +P 100 2000 400 2000 1 0 0 +{ +T 300 2050 5 8 1 1 0 6 1 +pinnumber=30 +T 300 1950 5 8 0 1 0 8 1 +pinseq=30 +T 450 2000 9 8 1 1 0 0 1 +pinlabel=A18 +T 450 2000 5 8 0 1 0 2 1 +pintype=in +} +P 100 1600 300 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=22 +T 300 1550 5 8 0 1 0 8 1 +pinseq=22 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=CE +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +V 350 1600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 1200 300 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=24 +T 300 1150 5 8 0 1 0 8 1 +pinseq=24 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=OE +T 450 1200 5 8 0 1 0 2 1 +pintype=in +} +V 350 1200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 800 300 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=29 +T 300 750 5 8 0 1 0 8 1 +pinseq=29 +T 450 800 9 8 1 1 0 0 1 +pinlabel=WE +T 450 800 5 8 0 1 0 2 1 +pintype=in +} +V 350 800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1400 100 1400 400 1 0 0 +{ +T 1450 200 5 8 1 1 0 0 1 +pinnumber=16 +T 1450 200 5 8 0 1 0 2 1 +pinseq=16 +T 1400 450 9 8 1 1 0 3 1 +pinlabel=GND +T 1400 600 5 8 0 1 0 3 1 +pintype=pwr +} +B 400 400 2000 9200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/CY62148B-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,83 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=yes +generate_pinseq=yes +sym_width=2000 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=CY62148B +device=CY62148B +refdes=U? +#footprint= +description=512Kx8 static RAM +#documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in line l A17 +2 in line l A16 +3 in line l A14 +4 in line l A12 +5 in line l A7 +6 in line l A6 +7 in line l A5 +8 in line l A4 +9 in line l A3 +10 in line l A2 +11 in line l A1 +12 in line l A0 +13 tri line r DQ0 +14 tri line r DQ1 +15 tri line r DQ2 +16 pwr line b GND +17 tri line r DQ3 +18 tri line r DQ4 +19 tri line r DQ5 +20 tri line r DQ6 +21 tri line r DQ7 +22 in line l CE +23 in line l A10 +24 in line l OE +25 in line l A11 +26 in line l A9 +27 in line l A8 +28 in line l A13 +29 in line l WE +30 in line l A18 +31 in line l A15 +32 pwr line t VCC
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144-confjtag.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,152 @@ +v 20040111 1 +T 4400 4900 8 10 1 1 0 6 1 +refdes=U? +T 400 4850 9 10 1 1 0 0 1 +device=EPF10K30ATx144 +T 400 5250 5 10 0 0 0 0 1 +footprint=LQFP144_20 +T 400 5450 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 5850 5 10 0 0 0 0 1 +description=EPF10K30ATx144 FPGA, configuration and JTAG pins +T 400 6050 5 10 0 0 0 0 1 +numslots=0 +P 100 4400 400 4400 1 0 0 +{ +T 300 4450 5 8 1 1 0 6 1 +pinnumber=105 +T 300 4350 5 8 0 1 0 8 1 +pinseq=105 +T 450 4400 9 8 1 1 0 0 1 +pinlabel=TDI +T 450 4400 5 8 0 1 0 2 1 +pintype=in +} +P 100 4000 400 4000 1 0 0 +{ +T 300 4050 5 8 1 1 0 6 1 +pinnumber=34 +T 300 3950 5 8 0 1 0 8 1 +pinseq=34 +T 450 4000 9 8 1 1 0 0 1 +pinlabel=TMS +T 450 4000 5 8 0 1 0 2 1 +pintype=in +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=4 +T 300 3550 5 8 0 1 0 8 1 +pinseq=4 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=TDO +T 450 3600 5 8 0 1 0 2 1 +pintype=out +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=1 +T 300 3150 5 8 0 1 0 8 1 +pinseq=1 +T 525 3200 9 8 1 1 0 0 1 +pinlabel=TCK +T 525 3200 5 8 0 1 0 2 1 +pintype=in +} +L 500 3200 400 3275 3 0 0 0 -1 -1 +L 500 3200 400 3125 3 0 0 0 -1 -1 +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=106 +T 300 2350 5 8 0 1 0 8 1 +pinseq=106 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=nCE +T 450 2400 5 8 0 1 0 2 1 +pintype=in +} +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=74 +T 300 1550 5 8 0 1 0 8 1 +pinseq=74 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=nCONFIG +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=35 +T 300 1150 5 8 0 1 0 8 1 +pinseq=35 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=nSTATUS +T 450 1200 5 8 0 1 0 2 1 +pintype=tri +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=2 +T 300 750 5 8 0 1 0 8 1 +pinseq=2 +T 450 800 9 8 1 1 0 0 1 +pinlabel=CONF_DONE +T 450 800 5 8 0 1 0 2 1 +pintype=out +} +P 100 400 400 400 1 0 0 +{ +T 300 450 5 8 1 1 0 6 1 +pinnumber=14 +T 300 350 5 8 0 1 0 8 1 +pinseq=14 +T 450 400 9 8 1 1 0 0 1 +pinlabel=INIT_DONE +T 450 400 5 8 0 1 0 2 1 +pintype=out +} +P 4700 4400 4400 4400 1 0 0 +{ +T 4500 4450 5 8 1 1 0 0 1 +pinnumber=77 +T 4500 4350 5 8 0 1 0 2 1 +pinseq=77 +T 4350 4400 9 8 1 1 0 6 1 +pinlabel=MSEL0 +T 4350 4400 5 8 0 1 0 8 1 +pintype=in +} +P 4700 4000 4400 4000 1 0 0 +{ +T 4500 4050 5 8 1 1 0 0 1 +pinnumber=76 +T 4500 3950 5 8 0 1 0 2 1 +pinseq=76 +T 4350 4000 9 8 1 1 0 6 1 +pinlabel=MSEL1 +T 4350 4000 5 8 0 1 0 8 1 +pintype=in +} +P 4700 2400 4400 2400 1 0 0 +{ +T 4500 2450 5 8 1 1 0 0 1 +pinnumber=3 +T 4500 2350 5 8 0 1 0 2 1 +pinseq=3 +T 4350 2400 9 8 1 1 0 6 1 +pinlabel=nCEO +T 4350 2400 5 8 0 1 0 8 1 +pintype=out +} +B 400 0 4000 4800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 2000 1600 9 10 1 0 0 0 1 +CONFIGURATION +T 2400 1300 9 10 1 0 0 0 1 +& JTAG
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144-confjtag.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,66 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=4000 +pinwidthvertikal=400 +pinwidthhorizontal=600 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EPF10K30ATx144 +device=EPF10K30ATx144 +refdes=U? +footprint=QFP144 +description=EPF10K30ATx144 FPGA, configuration and JTAG pins +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +105 in line l TDI +34 in line l TMS +4 out line l TDO +1 in clk l TCK +1001 pas line l DUMMY +106 in line l nCE +1002 pas line l DUMMY +74 in line l nCONFIG +35 tri line l nSTATUS +2 out line l CONF\_DONE +14 out line l INIT\_DONE + +77 in line r MSEL0 +76 in line r MSEL1 + +3 out line r nCEO
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144-global.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,110 @@ +v 20040111 1 +T 4400 3300 8 10 1 1 0 6 1 +refdes=U? +T 400 3250 9 10 1 1 0 0 1 +device=EPF10K30ATx144 +T 400 3650 5 10 0 0 0 0 1 +footprint=LQFP144_20 +T 400 3850 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 4250 5 10 0 0 0 0 1 +description=EPF10K30ATx144 FPGA, global input pins +T 400 4450 5 10 0 0 0 0 1 +numslots=0 +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=55 +T 300 2750 5 8 0 1 0 8 1 +pinseq=55 +T 525 2800 9 8 1 1 0 0 1 +pinlabel=GCLK0 +T 525 2800 5 8 0 1 0 2 1 +pintype=in +} +L 500 2800 400 2875 3 0 0 0 -1 -1 +L 500 2800 400 2725 3 0 0 0 -1 -1 +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=125 +T 300 2350 5 8 0 1 0 8 1 +pinseq=125 +T 525 2400 9 8 1 1 0 0 1 +pinlabel=GCLK1 +T 525 2400 5 8 0 1 0 2 1 +pintype=in +} +L 500 2400 400 2475 3 0 0 0 -1 -1 +L 500 2400 400 2325 3 0 0 0 -1 -1 +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=54 +T 300 1550 5 8 0 1 0 8 1 +pinseq=54 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=GIN0 +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=56 +T 300 1150 5 8 0 1 0 8 1 +pinseq=56 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=GIN1 +T 450 1200 5 8 0 1 0 2 1 +pintype=in +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=124 +T 300 750 5 8 0 1 0 8 1 +pinseq=124 +T 450 800 9 8 1 1 0 0 1 +pinlabel=GIN2 +T 450 800 5 8 0 1 0 2 1 +pintype=in +} +P 100 400 400 400 1 0 0 +{ +T 300 450 5 8 1 1 0 6 1 +pinnumber=126 +T 300 350 5 8 0 1 0 8 1 +pinseq=126 +T 450 400 9 8 1 1 0 0 1 +pinlabel=GIN3 +T 450 400 5 8 0 1 0 2 1 +pintype=in +} +P 4700 1600 4400 1600 1 0 0 +{ +T 4500 1650 5 8 1 1 0 0 1 +pinnumber=122 +T 4500 1550 5 8 0 1 0 2 1 +pinseq=122 +T 4350 1600 9 8 1 1 0 6 1 +pinlabel=DEV_CLRn +T 4350 1600 5 8 0 1 0 8 1 +pintype=in +} +P 4700 1200 4400 1200 1 0 0 +{ +T 4500 1250 5 8 1 1 0 0 1 +pinnumber=128 +T 4500 1150 5 8 0 1 0 2 1 +pinseq=128 +T 4350 1200 9 8 1 1 0 6 1 +pinlabel=DEV_OE +T 4350 1200 5 8 0 1 0 8 1 +pintype=in +} +B 400 0 4000 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1800 1500 9 10 1 0 0 0 1 +GLOBAL +T 1900 1200 9 10 1 0 0 0 1 +INPUTS
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144-global.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,60 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=4000 +pinwidthvertikal=400 +pinwidthhorizontal=600 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EPF10K30ATx144 +device=EPF10K30ATx144 +refdes=U? +footprint=QFP144 +description=EPF10K30ATx144 FPGA, global input pins +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +55 in clk l GCLK0 +125 in clk l GCLK1 +1000 pas line l DUMMY +54 in line l GIN0 +56 in line l GIN1 +124 in line l GIN2 +126 in line l GIN3 + +122 in line r DEV\_CLRn +128 in line r DEV\_OE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144-power.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,335 @@ +v 20040111 1 +T 9200 1800 8 10 1 1 0 0 1 +refdes=U? +T 200 1350 9 10 1 1 0 0 1 +device=EPF10K30ATx144 +T 300 2950 5 10 0 0 0 0 1 +footprint=LQFP144_20 +T 300 3150 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 3550 5 10 0 0 0 0 1 +description=EPF10K30ATx144 FPGA, power pins +T 300 3750 5 10 0 0 0 0 1 +numslots=0 +P 400 2300 400 2000 1 0 0 +{ +T 450 2100 5 8 1 1 0 0 1 +pinnumber=6 +T 450 2100 5 8 0 1 0 2 1 +pinseq=6 +T 400 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 400 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 1000 2300 1000 2000 1 0 0 +{ +T 1050 2100 5 8 1 1 0 0 1 +pinnumber=25 +T 1050 2100 5 8 0 1 0 2 1 +pinseq=25 +T 1000 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 1000 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 1600 2300 1600 2000 1 0 0 +{ +T 1650 2100 5 8 1 1 0 0 1 +pinnumber=52 +T 1650 2100 5 8 0 1 0 2 1 +pinseq=52 +T 1600 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 1600 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 2200 2300 2200 2000 1 0 0 +{ +T 2250 2100 5 8 1 1 0 0 1 +pinnumber=53 +T 2250 2100 5 8 0 1 0 2 1 +pinseq=53 +T 2200 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 2200 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 2800 2300 2800 2000 1 0 0 +{ +T 2850 2100 5 8 1 1 0 0 1 +pinnumber=75 +T 2850 2100 5 8 0 1 0 2 1 +pinseq=75 +T 2800 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 2800 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 3400 2300 3400 2000 1 0 0 +{ +T 3450 2100 5 8 1 1 0 0 1 +pinnumber=93 +T 3450 2100 5 8 0 1 0 2 1 +pinseq=93 +T 3400 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 3400 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 4000 2300 4000 2000 1 0 0 +{ +T 4050 2100 5 8 1 1 0 0 1 +pinnumber=123 +T 4050 2100 5 8 0 1 0 2 1 +pinseq=123 +T 4000 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 4000 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 4600 2300 4600 2000 1 0 0 +{ +T 4650 2100 5 8 1 1 0 0 1 +pinnumber=5 +T 4650 2100 5 8 0 1 0 2 1 +pinseq=5 +T 4600 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 4600 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 5200 2300 5200 2000 1 0 0 +{ +T 5250 2100 5 8 1 1 0 0 1 +pinnumber=24 +T 5250 2100 5 8 0 1 0 2 1 +pinseq=24 +T 5200 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 5200 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 5800 2300 5800 2000 1 0 0 +{ +T 5850 2100 5 8 1 1 0 0 1 +pinnumber=45 +T 5850 2100 5 8 0 1 0 2 1 +pinseq=45 +T 5800 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 5800 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 6400 2300 6400 2000 1 0 0 +{ +T 6450 2100 5 8 1 1 0 0 1 +pinnumber=61 +T 6450 2100 5 8 0 1 0 2 1 +pinseq=61 +T 6400 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 6400 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 7000 2300 7000 2000 1 0 0 +{ +T 7050 2100 5 8 1 1 0 0 1 +pinnumber=71 +T 7050 2100 5 8 0 1 0 2 1 +pinseq=71 +T 7000 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 7000 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 7600 2300 7600 2000 1 0 0 +{ +T 7650 2100 5 8 1 1 0 0 1 +pinnumber=94 +T 7650 2100 5 8 0 1 0 2 1 +pinseq=94 +T 7600 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 7600 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 8200 2300 8200 2000 1 0 0 +{ +T 8250 2100 5 8 1 1 0 0 1 +pinnumber=115 +T 8250 2100 5 8 0 1 0 2 1 +pinseq=115 +T 8200 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 8200 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 8800 2300 8800 2000 1 0 0 +{ +T 8850 2100 5 8 1 1 0 0 1 +pinnumber=134 +T 8850 2100 5 8 0 1 0 2 1 +pinseq=134 +T 8800 1950 9 8 1 1 0 5 1 +pinlabel=VCCio +T 8800 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 400 0 400 300 1 0 0 +{ +T 450 100 5 8 1 1 0 0 1 +pinnumber=16 +T 450 100 5 8 0 1 0 2 1 +pinseq=16 +T 400 350 9 8 1 1 0 3 1 +pinlabel=GNDint +T 400 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=57 +T 1050 100 5 8 0 1 0 2 1 +pinseq=57 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GNDint +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1600 0 1600 300 1 0 0 +{ +T 1650 100 5 8 1 1 0 0 1 +pinnumber=58 +T 1650 100 5 8 0 1 0 2 1 +pinseq=58 +T 1600 350 9 8 1 1 0 3 1 +pinlabel=GNDint +T 1600 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 2200 0 2200 300 1 0 0 +{ +T 2250 100 5 8 1 1 0 0 1 +pinnumber=84 +T 2250 100 5 8 0 1 0 2 1 +pinseq=84 +T 2200 350 9 8 1 1 0 3 1 +pinlabel=GNDint +T 2200 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 2800 0 2800 300 1 0 0 +{ +T 2850 100 5 8 1 1 0 0 1 +pinnumber=103 +T 2850 100 5 8 0 1 0 2 1 +pinseq=103 +T 2800 350 9 8 1 1 0 3 1 +pinlabel=GNDint +T 2800 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 3400 0 3400 300 1 0 0 +{ +T 3450 100 5 8 1 1 0 0 1 +pinnumber=127 +T 3450 100 5 8 0 1 0 2 1 +pinseq=127 +T 3400 350 9 8 1 1 0 3 1 +pinlabel=GNDint +T 3400 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 4600 0 4600 300 1 0 0 +{ +T 4650 100 5 8 1 1 0 0 1 +pinnumber=15 +T 4650 100 5 8 0 1 0 2 1 +pinseq=15 +T 4600 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 4600 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 5200 0 5200 300 1 0 0 +{ +T 5250 100 5 8 1 1 0 0 1 +pinnumber=40 +T 5250 100 5 8 0 1 0 2 1 +pinseq=40 +T 5200 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 5200 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 5800 0 5800 300 1 0 0 +{ +T 5850 100 5 8 1 1 0 0 1 +pinnumber=50 +T 5850 100 5 8 0 1 0 2 1 +pinseq=50 +T 5800 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 5800 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 6400 0 6400 300 1 0 0 +{ +T 6450 100 5 8 1 1 0 0 1 +pinnumber=66 +T 6450 100 5 8 0 1 0 2 1 +pinseq=66 +T 6400 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 6400 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 7000 0 7000 300 1 0 0 +{ +T 7050 100 5 8 1 1 0 0 1 +pinnumber=85 +T 7050 100 5 8 0 1 0 2 1 +pinseq=85 +T 7000 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 7000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 7600 0 7600 300 1 0 0 +{ +T 7650 100 5 8 1 1 0 0 1 +pinnumber=104 +T 7650 100 5 8 0 1 0 2 1 +pinseq=104 +T 7600 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 7600 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 8200 0 8200 300 1 0 0 +{ +T 8250 100 5 8 1 1 0 0 1 +pinnumber=129 +T 8250 100 5 8 0 1 0 2 1 +pinseq=129 +T 8200 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 8200 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 8800 0 8800 300 1 0 0 +{ +T 8850 100 5 8 1 1 0 0 1 +pinnumber=139 +T 8850 100 5 8 0 1 0 2 1 +pinseq=139 +T 8800 350 9 8 1 1 0 3 1 +pinlabel=GNDio +T 8800 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 0 300 9100 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 3900 1000 9 10 1 0 0 0 1 +POWER
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144-power.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,82 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=9000 +pinwidthvertikal=400 +pinwidthhorizontal=600 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=EPF10K30ATx144 +device=EPF10K30ATx144 +refdes=U? +footprint=QFP144 +description=EPF10K30ATx144 FPGA, power pins +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +6 pwr line t VCCint +25 pwr line t VCCint +52 pwr line t VCCint +53 pwr line t VCCint +75 pwr line t VCCint +93 pwr line t VCCint +123 pwr line t VCCint + +5 pwr line t VCCio +24 pwr line t VCCio +45 pwr line t VCCio +61 pwr line t VCCio +71 pwr line t VCCio +94 pwr line t VCCio +115 pwr line t VCCio +134 pwr line t VCCio + +16 pwr line b GNDint +57 pwr line b GNDint +58 pwr line b GNDint +84 pwr line b GNDint +103 pwr line b GNDint +127 pwr line b GNDint + +15 pwr line b GNDio +40 pwr line b GNDio +50 pwr line b GNDio +66 pwr line b GNDio +85 pwr line b GNDio +104 pwr line b GNDio +129 pwr line b GNDio +139 pwr line b GNDio
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144.pins Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,86 @@ +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +2 out line l CONF_DONE +14 out line l INIT_DONE +35 tri line l nSTATUS +74 in line l nCONFIG +77 in line l MSEL0 +76 in line l MSEL1 +107 in clk l DCLK + +106 in line l nCE +3 out line l nCEO +142 in line l nWS +141 in line l nRS +144 in line l nCS +143 in line l CS +11 out line l RDYnBSY +7 clk line l CLKUSR + +116 io line l DATA7 +114 io line l DATA6 +113 io line l DATA5 +112 io line l DATA4 +111 io line l DATA3 +110 io line l DATA2 +109 io line l DATA1 +108 io line l DATA0 + +105 in line l TDI +4 out line l TDO +1 in clk l TCK +34 in line l TMS + +54 in line l GIN0 +56 in line l GIN1 +124 in line l GIN2 +126 in line l GIN3 +55 in clk l GCLK0 +125 in clk l GCLK1 +122 in line l DEV_CLRn +128 in line l DEV_OE + +6 pwr line t VCCint +25 pwr line t VCCint +52 pwr line t VCCint +53 pwr line t VCCint +75 pwr line t VCCint +93 pwr line t VCCint +123 pwr line t VCCint + +5 pwr line t VCCio +24 pwr line t VCCio +45 pwr line t VCCio +61 pwr line t VCCio +71 pwr line t VCCio +94 pwr line t VCCio +115 pwr line t VCCio +134 pwr line t VCCio + +16 pwr line b GNDint +57 pwr line b GNDint +58 pwr line b GNDint +84 pwr line b GNDint +103 pwr line b GNDint +127 pwr line b GNDint + +15 pwr line b GNDio +40 pwr line b GNDio +50 pwr line b GNDio +66 pwr line b GNDio +85 pwr line b GNDio +104 pwr line b GNDio +129 pwr line b GNDio +139 pwr line b GNDio
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/EPF10K30ATx144.pins.bynum Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,78 @@ +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 in clk l TCK +2 out line l CONF_DONE +3 out line l nCEO +4 out line l TDO +5 pwr line t VCCio +6 pwr line t VCCint +7 clk line l CLKUSR +11 out line l RDYnBSY +14 out line l INIT_DONE +15 pwr line b GNDio +16 pwr line b GNDint +24 pwr line t VCCio +25 pwr line t VCCint +34 in line l TMS +35 tri line l nSTATUS +40 pwr line b GNDio +45 pwr line t VCCio +50 pwr line b GNDio +52 pwr line t VCCint +53 pwr line t VCCint +54 in line l GIN0 +55 in clk l GCLK0 +56 in line l GIN1 +57 pwr line b GNDint +58 pwr line b GNDint +61 pwr line t VCCio +66 pwr line b GNDio +71 pwr line t VCCio +74 in line l nCONFIG +75 pwr line t VCCint +76 in line l MSEL1 +77 in line l MSEL0 +84 pwr line b GNDint +85 pwr line b GNDio +93 pwr line t VCCint +94 pwr line t VCCio +103 pwr line b GNDint +104 pwr line b GNDio +105 in line l TDI +106 in line l nCE +107 in clk l DCLK +108 io line l DATA0 +109 io line l DATA1 +110 io line l DATA2 +111 io line l DATA3 +112 io line l DATA4 +113 io line l DATA5 +114 io line l DATA6 +115 pwr line t VCCio +116 io line l DATA7 +122 in line l DEV_CLRn +123 pwr line t VCCint +124 in line l GIN2 +125 in clk l GCLK1 +126 in line l GIN3 +127 pwr line b GNDint +128 in line l DEV_OE +129 pwr line b GNDio +134 pwr line t VCCio +139 pwr line b GNDio +141 in line l nRS +142 in line l nWS +143 in line l CS +144 in line l nCS
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/HDSL-xfmr-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,88 @@ +v 20040111 1 +L 500 1100 200 1100 3 0 0 0 -1 -1 +A 500 1000 100 270 180 3 0 0 0 -1 -1 +A 500 400 100 270 180 3 0 0 0 -1 -1 +A 500 200 100 270 180 3 0 0 0 -1 -1 +L 500 100 200 100 3 0 0 0 -1 -1 +L 1000 100 1300 100 3 0 0 0 -1 -1 +A 1000 200 100 90 180 3 0 0 0 -1 -1 +A 1000 400 100 90 180 3 0 0 0 -1 -1 +A 1000 1000 100 90 180 3 0 0 0 -1 -1 +L 1000 1100 1300 1100 3 0 0 0 -1 -1 +L 700 1200 700 0 3 0 0 0 -1 -1 +L 800 1200 800 0 3 0 0 0 -1 -1 +P 200 100 0 100 1 0 1 +{ +T 100 150 5 8 1 1 0 0 1 +pinnumber=5 +T 100 150 5 8 0 0 0 0 1 +pinseq=5 +T 100 150 5 8 0 1 0 0 1 +pinlabel=5 +T 100 150 5 8 0 1 0 0 1 +pintype=pas +} +P 200 700 0 700 1 0 1 +{ +T 100 750 5 8 1 1 0 0 1 +pinnumber=4 +T 100 750 5 8 0 0 0 0 1 +pinseq=4 +T 100 750 5 8 0 1 0 0 1 +pinlabel=4 +T 100 750 5 8 0 1 0 0 1 +pintype=pas +} +P 200 500 0 500 1 0 1 +{ +T 100 550 5 8 1 1 0 0 1 +pinnumber=2 +T 100 550 5 8 0 0 0 0 1 +pinseq=2 +T 100 550 5 8 0 1 0 0 1 +pinlabel=2 +T 100 550 5 8 0 1 0 0 1 +pintype=pas +} +P 200 1100 0 1100 1 0 1 +{ +T 100 1150 5 8 1 1 0 0 1 +pinnumber=1 +T 100 1150 5 8 0 0 0 0 1 +pinseq=1 +T 100 1150 5 8 0 1 0 0 1 +pinlabel=1 +T 100 1150 5 8 0 1 0 0 1 +pintype=pas +} +P 1500 100 1300 100 1 0 0 +{ +T 1400 150 5 8 1 1 0 0 1 +pinnumber=7 +T 1400 150 5 8 0 0 0 0 1 +pinseq=7 +T 1400 150 5 8 0 1 0 0 1 +pinlabel=7 +T 1400 150 5 8 0 1 0 0 1 +pintype=pas +} +P 1500 1100 1300 1100 1 0 0 +{ +T 1400 1150 5 8 1 1 0 0 1 +pinnumber=9 +T 1400 1150 5 8 0 0 0 0 1 +pinseq=9 +T 1400 1150 5 8 0 1 0 0 1 +pinlabel=9 +T 1400 1150 5 8 0 1 0 0 1 +pintype=pas +} +T 300 1300 8 10 1 1 0 0 1 +refdes=T? +T 300 1300 8 10 0 0 0 0 1 +device=TRANSFORMER +A 500 800 100 270 180 3 0 0 0 -1 -1 +A 1000 800 100 90 180 3 0 0 0 -1 -1 +A 1000 600 100 90 180 3 0 0 0 -1 -1 +L 500 500 200 500 3 0 0 0 -1 -1 +L 500 700 200 700 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/HM628512-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,369 @@ +v 20040111 1 +T 2400 9700 8 10 1 1 0 6 1 +refdes=U? +T 400 9650 9 9 1 0 0 0 1 +HM628512 +T 400 9850 5 10 0 0 0 0 1 +device=HM628512 +T 400 10050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 10250 5 10 0 0 0 0 1 +description=512Kx8 static RAM +T 400 10450 5 10 0 0 0 0 1 +numslots=0 +P 1400 9900 1400 9600 1 0 0 +{ +T 1450 9700 5 8 1 1 0 0 1 +pinnumber=32 +T 1450 9700 5 8 0 1 0 2 1 +pinseq=32 +T 1400 9550 9 8 1 1 0 5 1 +pinlabel=VCC +T 1400 9400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2700 9200 2400 9200 1 0 0 +{ +T 2500 9250 5 8 1 1 0 0 1 +pinnumber=13 +T 2500 9150 5 8 0 1 0 2 1 +pinseq=13 +T 2350 9200 9 8 1 1 0 6 1 +pinlabel=DQ0 +T 2350 9200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8800 2400 8800 1 0 0 +{ +T 2500 8850 5 8 1 1 0 0 1 +pinnumber=14 +T 2500 8750 5 8 0 1 0 2 1 +pinseq=14 +T 2350 8800 9 8 1 1 0 6 1 +pinlabel=DQ1 +T 2350 8800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8400 2400 8400 1 0 0 +{ +T 2500 8450 5 8 1 1 0 0 1 +pinnumber=15 +T 2500 8350 5 8 0 1 0 2 1 +pinseq=15 +T 2350 8400 9 8 1 1 0 6 1 +pinlabel=DQ2 +T 2350 8400 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8000 2400 8000 1 0 0 +{ +T 2500 8050 5 8 1 1 0 0 1 +pinnumber=17 +T 2500 7950 5 8 0 1 0 2 1 +pinseq=17 +T 2350 8000 9 8 1 1 0 6 1 +pinlabel=DQ3 +T 2350 8000 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7600 2400 7600 1 0 0 +{ +T 2500 7650 5 8 1 1 0 0 1 +pinnumber=18 +T 2500 7550 5 8 0 1 0 2 1 +pinseq=18 +T 2350 7600 9 8 1 1 0 6 1 +pinlabel=DQ4 +T 2350 7600 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7200 2400 7200 1 0 0 +{ +T 2500 7250 5 8 1 1 0 0 1 +pinnumber=19 +T 2500 7150 5 8 0 1 0 2 1 +pinseq=19 +T 2350 7200 9 8 1 1 0 6 1 +pinlabel=DQ5 +T 2350 7200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6800 2400 6800 1 0 0 +{ +T 2500 6850 5 8 1 1 0 0 1 +pinnumber=20 +T 2500 6750 5 8 0 1 0 2 1 +pinseq=20 +T 2350 6800 9 8 1 1 0 6 1 +pinlabel=DQ6 +T 2350 6800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6400 2400 6400 1 0 0 +{ +T 2500 6450 5 8 1 1 0 0 1 +pinnumber=21 +T 2500 6350 5 8 0 1 0 2 1 +pinseq=21 +T 2350 6400 9 8 1 1 0 6 1 +pinlabel=DQ7 +T 2350 6400 5 8 0 1 0 8 1 +pintype=tri +} +P 100 9200 400 9200 1 0 0 +{ +T 300 9250 5 8 1 1 0 6 1 +pinnumber=12 +T 300 9150 5 8 0 1 0 8 1 +pinseq=12 +T 450 9200 9 8 1 1 0 0 1 +pinlabel=A0 +T 450 9200 5 8 0 1 0 2 1 +pintype=in +} +P 100 8800 400 8800 1 0 0 +{ +T 300 8850 5 8 1 1 0 6 1 +pinnumber=11 +T 300 8750 5 8 0 1 0 8 1 +pinseq=11 +T 450 8800 9 8 1 1 0 0 1 +pinlabel=A1 +T 450 8800 5 8 0 1 0 2 1 +pintype=in +} +P 100 8400 400 8400 1 0 0 +{ +T 300 8450 5 8 1 1 0 6 1 +pinnumber=10 +T 300 8350 5 8 0 1 0 8 1 +pinseq=10 +T 450 8400 9 8 1 1 0 0 1 +pinlabel=A2 +T 450 8400 5 8 0 1 0 2 1 +pintype=in +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=9 +T 300 7950 5 8 0 1 0 8 1 +pinseq=9 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=A3 +T 450 8000 5 8 0 1 0 2 1 +pintype=in +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=8 +T 300 7550 5 8 0 1 0 8 1 +pinseq=8 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=A4 +T 450 7600 5 8 0 1 0 2 1 +pintype=in +} +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=7 +T 300 7150 5 8 0 1 0 8 1 +pinseq=7 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=A5 +T 450 7200 5 8 0 1 0 2 1 +pintype=in +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=6 +T 300 6750 5 8 0 1 0 8 1 +pinseq=6 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=A6 +T 450 6800 5 8 0 1 0 2 1 +pintype=in +} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=5 +T 300 6350 5 8 0 1 0 8 1 +pinseq=5 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=A7 +T 450 6400 5 8 0 1 0 2 1 +pintype=in +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=27 +T 300 5950 5 8 0 1 0 8 1 +pinseq=27 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=A8 +T 450 6000 5 8 0 1 0 2 1 +pintype=in +} +P 100 5600 400 5600 1 0 0 +{ +T 300 5650 5 8 1 1 0 6 1 +pinnumber=26 +T 300 5550 5 8 0 1 0 8 1 +pinseq=26 +T 450 5600 9 8 1 1 0 0 1 +pinlabel=A9 +T 450 5600 5 8 0 1 0 2 1 +pintype=in +} +P 100 5200 400 5200 1 0 0 +{ +T 300 5250 5 8 1 1 0 6 1 +pinnumber=23 +T 300 5150 5 8 0 1 0 8 1 +pinseq=23 +T 450 5200 9 8 1 1 0 0 1 +pinlabel=A10 +T 450 5200 5 8 0 1 0 2 1 +pintype=in +} +P 100 4800 400 4800 1 0 0 +{ +T 300 4850 5 8 1 1 0 6 1 +pinnumber=25 +T 300 4750 5 8 0 1 0 8 1 +pinseq=25 +T 450 4800 9 8 1 1 0 0 1 +pinlabel=A11 +T 450 4800 5 8 0 1 0 2 1 +pintype=in +} +P 100 4400 400 4400 1 0 0 +{ +T 300 4450 5 8 1 1 0 6 1 +pinnumber=4 +T 300 4350 5 8 0 1 0 8 1 +pinseq=4 +T 450 4400 9 8 1 1 0 0 1 +pinlabel=A12 +T 450 4400 5 8 0 1 0 2 1 +pintype=in +} +P 100 4000 400 4000 1 0 0 +{ +T 300 4050 5 8 1 1 0 6 1 +pinnumber=28 +T 300 3950 5 8 0 1 0 8 1 +pinseq=28 +T 450 4000 9 8 1 1 0 0 1 +pinlabel=A13 +T 450 4000 5 8 0 1 0 2 1 +pintype=in +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=3 +T 300 3550 5 8 0 1 0 8 1 +pinseq=3 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=A14 +T 450 3600 5 8 0 1 0 2 1 +pintype=in +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=31 +T 300 3150 5 8 0 1 0 8 1 +pinseq=31 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=A15 +T 450 3200 5 8 0 1 0 2 1 +pintype=in +} +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=2 +T 300 2750 5 8 0 1 0 8 1 +pinseq=2 +T 450 2800 9 8 1 1 0 0 1 +pinlabel=A16 +T 450 2800 5 8 0 1 0 2 1 +pintype=in +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=30 +T 300 2350 5 8 0 1 0 8 1 +pinseq=30 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=A17 +T 450 2400 5 8 0 1 0 2 1 +pintype=in +} +P 100 2000 400 2000 1 0 0 +{ +T 300 2050 5 8 1 1 0 6 1 +pinnumber=1 +T 300 1950 5 8 0 1 0 8 1 +pinseq=1 +T 450 2000 9 8 1 1 0 0 1 +pinlabel=A18 +T 450 2000 5 8 0 1 0 2 1 +pintype=in +} +P 100 1600 300 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=22 +T 300 1550 5 8 0 1 0 8 1 +pinseq=22 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=CS +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +V 350 1600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 1200 300 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=24 +T 300 1150 5 8 0 1 0 8 1 +pinseq=24 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=OE +T 450 1200 5 8 0 1 0 2 1 +pintype=in +} +V 350 1200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 800 300 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=29 +T 300 750 5 8 0 1 0 8 1 +pinseq=29 +T 450 800 9 8 1 1 0 0 1 +pinlabel=WE +T 450 800 5 8 0 1 0 2 1 +pintype=in +} +V 350 800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1400 100 1400 400 1 0 0 +{ +T 1450 200 5 8 1 1 0 0 1 +pinnumber=16 +T 1450 200 5 8 0 1 0 2 1 +pinseq=16 +T 1400 450 9 8 1 1 0 3 1 +pinlabel=GND +T 1400 600 5 8 0 1 0 3 1 +pintype=pwr +} +B 400 400 2000 9200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302.PQFP-pins Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,133 @@ +#Signal PQFP pin +A1 1 +A2 2 +A3 3 +GND 4 +A4 5 +A5 6 +A6 7 +A7 8 +A8 9 +A9 10 +A10 11 +A11 12 +GND 13 +A12 14 +A13 15 +A14 16 +A15 17 +VDD 18 +A16 19 +A17 20 +A18 21 +A19 22 +GND 23 +A20 24 +A21 25 +A22 26 +A23 27 +VDD 28 +GND 29 +D15 30 +D14 31 +D13 32 +D12 33 +GND 34 +D11 35 +D10 36 +D9 37 +D8 38 +VDD 39 +D7 40 +D6 41 +D5 42 +D4 43 +GND 44 +D3 45 +D2 46 +D1 47 +D0 48 +CTS3 49 +CD1 50 +CTS1 51 +RxD1 52 +RxD2 53 +TxD2 54 +RCLK2 55 +TCLK2 56 +GND 57 +CTS2 58 +RTS2 59 +CD2 60 +SDS2 61 +VDD 62 +RxD3 63 +TxD3 64 +RCLK3 65 +TCLK3 66 +GND 67 +PA12 68 +DREQ 69 +DACK 70 +DONE 71 +FRZ 72 +DISCPU 73 +BUSW 74 +NC3 75 +BRG1 76 +CD3 77 +RTS3 78 +RTS1 79 +TxD1 80 +TCLK1 81 +RCLK1 82 +VDD 83 +GND 84 +DTACK 85 +BCLR 86 +BG 87 +BGACK 88 +NC1 89 +BR 90 +HALT 91 +RESET 92 +AVEC 93 +BERR 94 +IPL2 95 +IPL1 96 +IPL0 97 +CLKO 98 +VDD 99 +EXTAL 100 +XTAL 101 +GND 102 +R/W 103 +AS 104 +LDS 105 +UDS 106 +GND 107 +IACK7 108 +IACK6 109 +IACK1 110 +TIN1 111 +VDD 112 +TOUT1 113 +TIN2 114 +TOUT2 115 +GND 116 +WDOG 117 +PB8 118 +PB9 119 +PB10 120 +PB11 121 +IAC 122 +RMC 123 +CS3 124 +CS2 125 +GND 126 +CS1 127 +CS0 128 +FC2 129 +FC1 130 +VDD 131 +FC0 132
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302.pins Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,149 @@ +#Signal PQFP PGA +A1 1 G1 +A2 2 G3 +A3 3 G2 +A4 5 F2 +A5 6 F3 +A6 7 E1 +A7 8 D1 +A8 9 E2 +A9 10 E3 +A10 11 C1 +A11 12 B1 +A12 14 D3 +A13 15 C2 +A14 16 A1 +A15 17 D4 +A16 19 D5 +A17 20 C3 +A18 21 B2 +A19 22 B3 +A20 24 B4 +A21 25 A2 +A22 26 A3 +A23 27 C5 +D0 48 B11 +D1 47 C10 +D2 46 B10 +D3 45 A12 +D4 43 C9 +D5 42 B9 +D6 41 A10 +D7 40 A9 +D8 38 B8 +D9 37 A8 +D10 36 B7 +D11 35 C7 +D12 33 A6 +D13 32 B6 +D14 31 C6 +D15 30 A5 + +AS 104 M6 +R/W 103 N6 +UDS/A0 106 N5 +LDS/DS 105 L6 +DTACK 85 K9 +RMC/IOUT1 123 K2 +IAC 122 K3 +BCLR 86 L11 + +BR 90 M10 +BG 87 M12 +BGACK 88 M11 + +RESET 92 N11 +HALT 91 N12 +BERR 94 M9 +BUSW 74 K13 +DISCPU 73 J13 + +IPL0/IRQ1 97 L8 +IPL1/IRQ6 96 N9 +IPL2/IRQ7 95 N10 +FC0 132 H1 +FC1 130 H3 +FC2 129 J1 +AVEC/IOUT0 93 L9 + +CS0/IOUT2 128 K1 +CS1 127 J2 +CS2 125 L1 +CS3 124 M1 + +RxD1/L1RxD 52 A13 +TxD1/L1TxD 80 K11 +RCLK1/L1CLK 82 N13 +TCLK1/L1SY0/SDS1 81 L12 +CD1/L1SY1 50 C11 +CTS1/L1GR 51 D10 +RTS1/L1RQ/GCIDCL 79 K12 +BRG1 76 J11 + +RxD2/PA0 53 D9 +TxD2/PA1 54 E10 +RCLK2/PA2 55 C12 +TCLK2/PA3 56 D11 +CTS2/PA4 58 B13 +RTS2/PA5 59 C13 +CD2/PA6 60 E11 +BRG2/SDS2/PA7 61 E12 + +RxD3/PA8 63 E13 +TxD3/PA9 64 F11 +RCLK3/PA10 65 F12 +TCLK3/PA11 66 F13 +CTS3/SPRxD 49 B12 +RTS3/SPTxD 78 M13 +CD3/SPCLK 77 L13 +BRG3/PA12 68 G11 + +DREQ/PA13 69 G12 +DACK/PA14 70 H13 +DONE/PA15 71 H12 + +IACK7/PB0 108 M5 +IACK6/PB1 109 L5 +IACK1/PB2 110 N3 + +TIN1/PB3 111 N2 +TOUT1/PB4 113 L4 +TIN2/PB5 114 M3 +TOUT2/PB6 115 M2 +WDOG/PB7 117 K5 + +PB8 118 J4 +PB9 119 K4 +PB10 120 N1 +PB11 121 L2 + +EXTAL 100 N7 +XTAL 101 L7 +CLKO 98 M8 +FRZ 72 H11 + +GND 4 N4 +GND 13 M7 +GND 23 L3 +GND 29 J3 +GND 34 J10 +GND 44 G13 +GND 57 F1 +GND 67 D2 +GND 84 D12 +GND 102 C4 +GND 107 A4 +GND 116 A7 +GND 126 A11 + +VDD 18 N8 +VDD 28 M4 +VDD 39 K10 +VDD 62 H2 +VDD 83 E4 +VDD 99 D13 +VDD 112 C8 +VDD 131 B5 + +NC1 89 L10 +NC3 75 J12
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302.pins.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,163 @@ +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +G1 1 tri line l A1 +G3 2 tri line l A2 +G2 3 tri line l A3 +F2 5 tri line l A4 +F3 6 tri line l A5 +E1 7 tri line l A6 +D1 8 tri line l A7 +E2 9 tri line l A8 +E3 10 tri line l A9 +C1 11 tri line l A10 +B1 12 tri line l A11 +D3 14 tri line l A12 +C2 15 tri line l A13 +A1 16 tri line l A14 +D4 17 tri line l A15 +D5 19 tri line l A16 +C3 20 tri line l A17 +B2 21 tri line l A18 +B3 22 tri line l A19 +B4 24 tri line l A20 +A2 25 tri line l A21 +A3 26 tri line l A22 +C5 27 tri line l A23 + +B11 48 tri line l D0 +C10 47 tri line l D1 +B10 46 tri line l D2 +A12 45 tri line l D3 +C9 43 tri line l D4 +B9 42 tri line l D5 +A10 41 tri line l D6 +A9 40 tri line l D7 +B8 38 tri line l D8 +A8 37 tri line l D9 +B7 36 tri line l D10 +C7 35 tri line l D11 +A6 33 tri line l D12 +B6 32 tri line l D13 +C6 31 tri line l D14 +A5 30 tri line l D15 + +M6 104 tri line l AS +N6 103 tri line l R/W +N5 106 tri line l UDS/A0 +L6 105 tri line l LDS/DS +K9 85 tri line l DTACK +K2 123 out line l RMC/IOUT1 +K3 122 out line l IAC +L11 86 oc line l BCLR + +M10 90 io line l BR +M12 87 io line l BG +M11 88 io line l BGACK + +N11 92 oc line l RESET +N12 91 oc line l HALT +M9 94 oc line l BERR +K13 74 in line l BUSW +J13 73 in line l DISCPU + +L8 97 in line l IPL0/IRQ1 +N9 96 in line l IPL1/IRQ6 +N10 95 in line l IPL2/IRQ7 +H1 132 tri line l FC0 +H3 130 tri line l FC1 +J1 129 tri line l FC2 +L9 93 io line l AVEC/IOUT0 + +K1 128 out line l CS0/IOUT2 +J2 127 out line l CS1 +L1 125 out line l CS2 +M1 124 out line l CS3 + +A13 52 in line l RxD1/L1RxD +K11 80 out line l TxD1/L1TxD +N13 82 io line l RCLK1/L1CLK +L12 81 io line l TCLK1/L1SY0/SDS1 +C11 50 in line l CD1/L1SY1 +D10 51 in line l CTS1/L1GR +K12 79 out line l RTS1/L1RQ/GCIDCL +J11 76 out line l BRG1 + +D9 53 io line l RxD2/PA0 +E10 54 io line l TxD2/PA1 +C12 55 io line l RCLK2/PA2 +D11 56 io line l TCLK2/PA3 +B13 58 io line l CTS2/PA4 +C13 59 io line l RTS2/PA5 +E11 60 io line l CD2/PA6 +E12 61 io line l BRG2/SDS2/PA7 + +E13 63 io line l RxD3/PA8 +F11 64 io line l TxD3/PA9 +F12 65 io line l RCLK3/PA10 +F13 66 io line l TCLK3/PA11 +B12 49 in line l CTS3/SPRxD +M13 78 out line l RTS3/SPTxD +L13 77 io line l CD3/SPCLK +G11 68 io line l BRG3/PA12 + +G12 69 io line l DREQ/PA13 +H13 70 io line l DACK/PA14 +H12 71 io line l DONE/PA15 + +M5 108 io line l IACK7/PB0 +L5 109 io line l IACK6/PB1 +N3 110 io line l IACK1/PB2 + +N2 111 io line l TIN1/PB3 +L4 113 io line l TOUT1/PB4 +M3 114 io line l TIN2/PB5 +M2 115 io line l TOUT2/PB6 +K5 117 io line l WDOG/PB7 + +J4 118 io line l PB8 +K4 119 io line l PB9 +N1 120 io line l PB10 +L2 121 io line l PB11 + +N7 100 clk line l EXTAL +L7 101 out line l XTAL +M8 98 out line l CLKO +H11 72 in line l FRZ + +N4 4 pwr line l GND +M7 13 pwr line l GND +L3 23 pwr line l GND +J3 29 pwr line l GND +J10 34 pwr line l GND +G13 44 pwr line l GND +F1 57 pwr line l GND +D2 67 pwr line l GND +D12 84 pwr line l GND +C4 102 pwr line l GND +A4 107 pwr line l GND +A7 116 pwr line l GND +A11 126 pwr line l GND + +N8 18 pwr line l VDD +M4 28 pwr line l VDD +K10 39 pwr line l VDD +H2 62 pwr line l VDD +E4 83 pwr line l VDD +D13 99 pwr line l VDD +C8 112 pwr line l VDD +B5 131 pwr line l VDD + +L10 89 out line l NC1 +J12 75 out line l NC3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302_PGA-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,778 @@ +v 20040111 1 +T 3300 16700 8 10 1 1 0 6 1 +refdes=U? +T 500 16650 9 10 1 0 0 0 1 +MC68302 +T 500 16850 5 10 0 0 0 0 1 +device=MC68302 +T 500 17050 5 10 0 0 0 0 1 +footprint=PGA132 +T 500 17250 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 500 17450 5 10 0 0 0 0 1 +documentation= +T 500 17650 5 10 0 0 0 0 1 +description=MC68302 IMP, M68K bus (1 of 3) +T 500 17850 5 10 0 0 0 0 1 +numslots=0 +T 500 18050 5 10 0 0 0 0 1 +comment=pinseq numbers are PQFP package pins +P 200 16200 500 16200 1 0 0 +{ +T 400 16250 5 8 1 1 0 6 1 +pinnumber=G1 +T 400 16150 5 8 0 1 0 8 1 +pinseq=1 +T 550 16200 9 8 1 1 0 0 1 +pinlabel=A1 +T 550 16200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 15800 500 15800 1 0 0 +{ +T 400 15850 5 8 1 1 0 6 1 +pinnumber=G3 +T 400 15750 5 8 0 1 0 8 1 +pinseq=2 +T 550 15800 9 8 1 1 0 0 1 +pinlabel=A2 +T 550 15800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 15400 500 15400 1 0 0 +{ +T 400 15450 5 8 1 1 0 6 1 +pinnumber=G2 +T 400 15350 5 8 0 1 0 8 1 +pinseq=3 +T 550 15400 9 8 1 1 0 0 1 +pinlabel=A3 +T 550 15400 5 8 0 1 0 2 1 +pintype=tri +} +P 200 15000 500 15000 1 0 0 +{ +T 400 15050 5 8 1 1 0 6 1 +pinnumber=F2 +T 400 14950 5 8 0 1 0 8 1 +pinseq=5 +T 550 15000 9 8 1 1 0 0 1 +pinlabel=A4 +T 550 15000 5 8 0 1 0 2 1 +pintype=tri +} +P 200 14600 500 14600 1 0 0 +{ +T 400 14650 5 8 1 1 0 6 1 +pinnumber=F3 +T 400 14550 5 8 0 1 0 8 1 +pinseq=6 +T 550 14600 9 8 1 1 0 0 1 +pinlabel=A5 +T 550 14600 5 8 0 1 0 2 1 +pintype=tri +} +P 200 14200 500 14200 1 0 0 +{ +T 400 14250 5 8 1 1 0 6 1 +pinnumber=E1 +T 400 14150 5 8 0 1 0 8 1 +pinseq=7 +T 550 14200 9 8 1 1 0 0 1 +pinlabel=A6 +T 550 14200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 13800 500 13800 1 0 0 +{ +T 400 13850 5 8 1 1 0 6 1 +pinnumber=D1 +T 400 13750 5 8 0 1 0 8 1 +pinseq=8 +T 550 13800 9 8 1 1 0 0 1 +pinlabel=A7 +T 550 13800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 13400 500 13400 1 0 0 +{ +T 400 13450 5 8 1 1 0 6 1 +pinnumber=E2 +T 400 13350 5 8 0 1 0 8 1 +pinseq=9 +T 550 13400 9 8 1 1 0 0 1 +pinlabel=A8 +T 550 13400 5 8 0 1 0 2 1 +pintype=tri +} +P 200 13000 500 13000 1 0 0 +{ +T 400 13050 5 8 1 1 0 6 1 +pinnumber=E3 +T 400 12950 5 8 0 1 0 8 1 +pinseq=10 +T 550 13000 9 8 1 1 0 0 1 +pinlabel=A9 +T 550 13000 5 8 0 1 0 2 1 +pintype=tri +} +P 200 12600 500 12600 1 0 0 +{ +T 400 12650 5 8 1 1 0 6 1 +pinnumber=C1 +T 400 12550 5 8 0 1 0 8 1 +pinseq=11 +T 550 12600 9 8 1 1 0 0 1 +pinlabel=A10 +T 550 12600 5 8 0 1 0 2 1 +pintype=tri +} +P 200 12200 500 12200 1 0 0 +{ +T 400 12250 5 8 1 1 0 6 1 +pinnumber=B1 +T 400 12150 5 8 0 1 0 8 1 +pinseq=12 +T 550 12200 9 8 1 1 0 0 1 +pinlabel=A11 +T 550 12200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 11800 500 11800 1 0 0 +{ +T 400 11850 5 8 1 1 0 6 1 +pinnumber=D3 +T 400 11750 5 8 0 1 0 8 1 +pinseq=14 +T 550 11800 9 8 1 1 0 0 1 +pinlabel=A12 +T 550 11800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 11400 500 11400 1 0 0 +{ +T 400 11450 5 8 1 1 0 6 1 +pinnumber=C2 +T 400 11350 5 8 0 1 0 8 1 +pinseq=15 +T 550 11400 9 8 1 1 0 0 1 +pinlabel=A13 +T 550 11400 5 8 0 1 0 2 1 +pintype=tri +} +P 200 11000 500 11000 1 0 0 +{ +T 400 11050 5 8 1 1 0 6 1 +pinnumber=A1 +T 400 10950 5 8 0 1 0 8 1 +pinseq=16 +T 550 11000 9 8 1 1 0 0 1 +pinlabel=A14 +T 550 11000 5 8 0 1 0 2 1 +pintype=tri +} +P 200 10600 500 10600 1 0 0 +{ +T 400 10650 5 8 1 1 0 6 1 +pinnumber=D4 +T 400 10550 5 8 0 1 0 8 1 +pinseq=17 +T 550 10600 9 8 1 1 0 0 1 +pinlabel=A15 +T 550 10600 5 8 0 1 0 2 1 +pintype=tri +} +P 200 10200 500 10200 1 0 0 +{ +T 400 10250 5 8 1 1 0 6 1 +pinnumber=D5 +T 400 10150 5 8 0 1 0 8 1 +pinseq=19 +T 550 10200 9 8 1 1 0 0 1 +pinlabel=A16 +T 550 10200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 9800 500 9800 1 0 0 +{ +T 400 9850 5 8 1 1 0 6 1 +pinnumber=C3 +T 400 9750 5 8 0 1 0 8 1 +pinseq=20 +T 550 9800 9 8 1 1 0 0 1 +pinlabel=A17 +T 550 9800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 9400 500 9400 1 0 0 +{ +T 400 9450 5 8 1 1 0 6 1 +pinnumber=B2 +T 400 9350 5 8 0 1 0 8 1 +pinseq=21 +T 550 9400 9 8 1 1 0 0 1 +pinlabel=A18 +T 550 9400 5 8 0 1 0 2 1 +pintype=tri +} +P 200 9000 500 9000 1 0 0 +{ +T 400 9050 5 8 1 1 0 6 1 +pinnumber=B3 +T 400 8950 5 8 0 1 0 8 1 +pinseq=22 +T 550 9000 9 8 1 1 0 0 1 +pinlabel=A19 +T 550 9000 5 8 0 1 0 2 1 +pintype=tri +} +P 200 8600 500 8600 1 0 0 +{ +T 400 8650 5 8 1 1 0 6 1 +pinnumber=B4 +T 400 8550 5 8 0 1 0 8 1 +pinseq=24 +T 550 8600 9 8 1 1 0 0 1 +pinlabel=A20 +T 550 8600 5 8 0 1 0 2 1 +pintype=tri +} +P 200 8200 500 8200 1 0 0 +{ +T 400 8250 5 8 1 1 0 6 1 +pinnumber=A2 +T 400 8150 5 8 0 1 0 8 1 +pinseq=25 +T 550 8200 9 8 1 1 0 0 1 +pinlabel=A21 +T 550 8200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 7800 500 7800 1 0 0 +{ +T 400 7850 5 8 1 1 0 6 1 +pinnumber=A3 +T 400 7750 5 8 0 1 0 8 1 +pinseq=26 +T 550 7800 9 8 1 1 0 0 1 +pinlabel=A22 +T 550 7800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 7400 500 7400 1 0 0 +{ +T 400 7450 5 8 1 1 0 6 1 +pinnumber=C5 +T 400 7350 5 8 0 1 0 8 1 +pinseq=27 +T 550 7400 9 8 1 1 0 0 1 +pinlabel=A23 +T 550 7400 5 8 0 1 0 2 1 +pintype=tri +} +P 200 6600 500 6600 1 0 0 +{ +T 400 6650 5 8 1 1 0 6 1 +pinnumber=B11 +T 400 6550 5 8 0 1 0 8 1 +pinseq=48 +T 550 6600 9 8 1 1 0 0 1 +pinlabel=D0 +T 550 6600 5 8 0 1 0 2 1 +pintype=tri +} +P 200 6200 500 6200 1 0 0 +{ +T 400 6250 5 8 1 1 0 6 1 +pinnumber=C10 +T 400 6150 5 8 0 1 0 8 1 +pinseq=47 +T 550 6200 9 8 1 1 0 0 1 +pinlabel=D1 +T 550 6200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 5800 500 5800 1 0 0 +{ +T 400 5850 5 8 1 1 0 6 1 +pinnumber=B10 +T 400 5750 5 8 0 1 0 8 1 +pinseq=46 +T 550 5800 9 8 1 1 0 0 1 +pinlabel=D2 +T 550 5800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 5400 500 5400 1 0 0 +{ +T 400 5450 5 8 1 1 0 6 1 +pinnumber=A12 +T 400 5350 5 8 0 1 0 8 1 +pinseq=45 +T 550 5400 9 8 1 1 0 0 1 +pinlabel=D3 +T 550 5400 5 8 0 1 0 2 1 +pintype=tri +} +P 200 5000 500 5000 1 0 0 +{ +T 400 5050 5 8 1 1 0 6 1 +pinnumber=C9 +T 400 4950 5 8 0 1 0 8 1 +pinseq=43 +T 550 5000 9 8 1 1 0 0 1 +pinlabel=D4 +T 550 5000 5 8 0 1 0 2 1 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8 1 +pintype=tri +} +L 2682 15124 2974 15124 3 0 0 0 -1 -1 +L 3046 15124 3250 15124 3 0 0 0 -1 -1 +P 3600 14600 3300 14600 1 0 0 +{ +T 3400 14650 5 8 1 1 0 0 1 +pinnumber=K9 +T 3400 14550 5 8 0 1 0 2 1 +pinseq=85 +T 3250 14600 9 8 1 1 0 6 1 +pinlabel=DTACK +T 3250 14600 5 8 0 1 0 8 1 +pintype=tri +} +L 2718 14724 3250 14724 3 0 0 0 -1 -1 +P 3600 14200 3300 14200 1 0 0 +{ +T 3400 14250 5 8 1 1 0 0 1 +pinnumber=K2 +T 3400 14150 5 8 0 1 0 2 1 +pinseq=123 +T 3250 14200 9 8 1 1 0 6 1 +pinlabel=RMC/IOUT1 +T 3250 14200 5 8 0 1 0 8 1 +pintype=out +} +L 2406 14324 2750 14324 3 0 0 0 -1 -1 +L 2822 14324 3250 14324 3 0 0 0 -1 -1 +P 3600 13800 3300 13800 1 0 0 +{ +T 3400 13850 5 8 1 1 0 0 1 +pinnumber=K3 +T 3400 13750 5 8 0 1 0 2 1 +pinseq=122 +T 3250 13800 9 8 1 1 0 6 1 +pinlabel=IAC +T 3250 13800 5 8 0 1 0 8 1 +pintype=out +} +P 3600 13400 3300 13400 1 0 0 +{ +T 3400 13450 5 8 1 1 0 0 1 +pinnumber=L11 +T 3400 13350 5 8 0 1 0 2 1 +pinseq=86 +T 3250 13400 9 8 1 1 0 6 1 +pinlabel=BCLR +T 3250 13400 5 8 0 1 0 8 1 +pintype=oc +} +L 2830 13524 3250 13524 3 0 0 0 -1 -1 +P 3600 12600 3300 12600 1 0 0 +{ +T 3400 12650 5 8 1 1 0 0 1 +pinnumber=M10 +T 3400 12550 5 8 0 1 0 2 1 +pinseq=90 +T 3250 12600 9 8 1 1 0 6 1 +pinlabel=BR +T 3250 12600 5 8 0 1 0 8 1 +pintype=io +} +L 3030 12724 3250 12724 3 0 0 0 -1 -1 +P 3600 12200 3300 12200 1 0 0 +{ +T 3400 12250 5 8 1 1 0 0 1 +pinnumber=M12 +T 3400 12150 5 8 0 1 0 2 1 +pinseq=87 +T 3250 12200 9 8 1 1 0 6 1 +pinlabel=BG +T 3250 12200 5 8 0 1 0 8 1 +pintype=io +} +L 3014 12324 3250 12324 3 0 0 0 -1 -1 +P 3600 11800 3300 11800 1 0 0 +{ +T 3400 11850 5 8 1 1 0 0 1 +pinnumber=M11 +T 3400 11750 5 8 0 1 0 2 1 +pinseq=88 +T 3250 11800 9 8 1 1 0 6 1 +pinlabel=BGACK +T 3250 11800 5 8 0 1 0 8 1 +pintype=io +} +L 2678 11924 3250 11924 3 0 0 0 -1 -1 +P 3600 11000 3300 11000 1 0 0 +{ +T 3400 11050 5 8 1 1 0 0 1 +pinnumber=N11 +T 3400 10950 5 8 0 1 0 2 1 +pinseq=92 +T 3250 11000 9 8 1 1 0 6 1 +pinlabel=RESET +T 3250 11000 5 8 0 1 0 8 1 +pintype=oc +} +L 2722 11124 3250 11124 3 0 0 0 -1 -1 +P 3600 10600 3300 10600 1 0 0 +{ +T 3400 10650 5 8 1 1 0 0 1 +pinnumber=N12 +T 3400 10550 5 8 0 1 0 2 1 +pinseq=91 +T 3250 10600 9 8 1 1 0 6 1 +pinlabel=HALT +T 3250 10600 5 8 0 1 0 8 1 +pintype=oc +} +L 2838 10724 3250 10724 3 0 0 0 -1 -1 +P 3600 10200 3300 10200 1 0 0 +{ +T 3400 10250 5 8 1 1 0 0 1 +pinnumber=M9 +T 3400 10150 5 8 0 1 0 2 1 +pinseq=94 +T 3250 10200 9 8 1 1 0 6 1 +pinlabel=BERR +T 3250 10200 5 8 0 1 0 8 1 +pintype=oc +} +L 2810 10324 3250 10324 3 0 0 0 -1 -1 +P 3600 9800 3300 9800 1 0 0 +{ +T 3400 9850 5 8 1 1 0 0 1 +pinnumber=K13 +T 3400 9750 5 8 0 1 0 2 1 +pinseq=74 +T 3250 9800 9 8 1 1 0 6 1 +pinlabel=BUSW +T 3250 9800 5 8 0 1 0 8 1 +pintype=in +} +P 3600 9400 3300 9400 1 0 0 +{ +T 3400 9450 5 8 1 1 0 0 1 +pinnumber=J13 +T 3400 9350 5 8 0 1 0 2 1 +pinseq=73 +T 3250 9400 9 8 1 1 0 6 1 +pinlabel=DISCPU +T 3250 9400 5 8 0 1 0 8 1 +pintype=in +} +P 3600 8600 3300 8600 1 0 0 +{ +T 3400 8650 5 8 1 1 0 0 1 +pinnumber=L8 +T 3400 8550 5 8 0 1 0 2 1 +pinseq=97 +T 3250 8600 9 8 1 1 0 6 1 +pinlabel=IPL0/IRQ1 +T 3250 8600 5 8 0 1 0 8 1 +pintype=in +} +L 2518 8724 2846 8724 3 0 0 0 -1 -1 +L 2918 8724 3250 8724 3 0 0 0 -1 -1 +P 3600 8200 3300 8200 1 0 0 +{ +T 3400 8250 5 8 1 1 0 0 1 +pinnumber=N9 +T 3400 8150 5 8 0 1 0 2 1 +pinseq=96 +T 3250 8200 9 8 1 1 0 6 1 +pinlabel=IPL1/IRQ6 +T 3250 8200 5 8 0 1 0 8 1 +pintype=in +} +L 2526 8324 2814 8324 3 0 0 0 -1 -1 +L 2886 8324 3250 8324 3 0 0 0 -1 -1 +P 3600 7800 3300 7800 1 0 0 +{ +T 3400 7850 5 8 1 1 0 0 1 +pinnumber=N10 +T 3400 7750 5 8 0 1 0 2 1 +pinseq=95 +T 3250 7800 9 8 1 1 0 6 1 +pinlabel=IPL2/IRQ7 +T 3250 7800 5 8 0 1 0 8 1 +pintype=in +} +L 2502 7924 2830 7924 3 0 0 0 -1 -1 +L 2902 7924 3250 7924 3 0 0 0 -1 -1 +P 3600 7400 3300 7400 1 0 0 +{ +T 3400 7450 5 8 1 1 0 0 1 +pinnumber=H1 +T 3400 7350 5 8 0 1 0 2 1 +pinseq=132 +T 3250 7400 9 8 1 1 0 6 1 +pinlabel=FC0 +T 3250 7400 5 8 0 1 0 8 1 +pintype=tri +} +P 3600 7000 3300 7000 1 0 0 +{ +T 3400 7050 5 8 1 1 0 0 1 +pinnumber=H3 +T 3400 6950 5 8 0 1 0 2 1 +pinseq=130 +T 3250 7000 9 8 1 1 0 6 1 +pinlabel=FC1 +T 3250 7000 5 8 0 1 0 8 1 +pintype=tri +} +P 3600 6600 3300 6600 1 0 0 +{ +T 3400 6650 5 8 1 1 0 0 1 +pinnumber=J1 +T 3400 6550 5 8 0 1 0 2 1 +pinseq=129 +T 3250 6600 9 8 1 1 0 6 1 +pinlabel=FC2 +T 3250 6600 5 8 0 1 0 8 1 +pintype=tri +} +P 3600 6200 3300 6200 1 0 0 +{ +T 3400 6250 5 8 1 1 0 0 1 +pinnumber=L9 +T 3400 6150 5 8 0 1 0 2 1 +pinseq=93 +T 3250 6200 9 8 1 1 0 6 1 +pinlabel=AVEC/IOUT0 +T 3250 6200 5 8 0 1 0 8 1 +pintype=io +} +L 2258 6324 2710 6324 3 0 0 0 -1 -1 +L 2782 6324 3250 6324 3 0 0 0 -1 -1 +P 3600 5400 3300 5400 1 0 0 +{ +T 3400 5450 5 8 1 1 0 0 1 +pinnumber=K1 +T 3400 5350 5 8 0 1 0 2 1 +pinseq=128 +T 3250 5400 9 8 1 1 0 6 1 +pinlabel=CS0/IOUT2 +T 3250 5400 5 8 0 1 0 8 1 +pintype=out +} +L 2394 5524 2710 5524 3 0 0 0 -1 -1 +L 2782 5524 3250 5524 3 0 0 0 -1 -1 +P 3600 5000 3300 5000 1 0 0 +{ +T 3400 5050 5 8 1 1 0 0 1 +pinnumber=J2 +T 3400 4950 5 8 0 1 0 2 1 +pinseq=127 +T 3250 5000 9 8 1 1 0 6 1 +pinlabel=CS1 +T 3250 5000 5 8 0 1 0 8 1 +pintype=out +} +L 2974 5124 3250 5124 3 0 0 0 -1 -1 +P 3600 4600 3300 4600 1 0 0 +{ +T 3400 4650 5 8 1 1 0 0 1 +pinnumber=L1 +T 3400 4550 5 8 0 1 0 2 1 +pinseq=125 +T 3250 4600 9 8 1 1 0 6 1 +pinlabel=CS2 +T 3250 4600 5 8 0 1 0 8 1 +pintype=out +} +L 2934 4724 3250 4724 3 0 0 0 -1 -1 +P 3600 4200 3300 4200 1 0 0 +{ +T 3400 4250 5 8 1 1 0 0 1 +pinnumber=M1 +T 3400 4150 5 8 0 1 0 2 1 +pinseq=124 +T 3250 4200 9 8 1 1 0 6 1 +pinlabel=CS3 +T 3250 4200 5 8 0 1 0 8 1 +pintype=out +} +L 2950 4324 3250 4324 3 0 0 0 -1 -1 +B 500 200 2800 16400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1500 2400 9 10 1 0 0 0 1 +M68K BUS +T 1700 2100 9 10 1 0 0 0 1 +1 OF 3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302_PGA-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,123 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=no +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MC68302 +device=MC68302 +refdes=U? +footprint=PGA132 +description=MC68302 IMP, M68K bus (1 of 3) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=pinseq numbers are PQFP package pins +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +G1 1 tri line l A1 +G3 2 tri line l A2 +G2 3 tri line l A3 +F2 5 tri line l A4 +F3 6 tri line l A5 +E1 7 tri line l A6 +D1 8 tri line l A7 +E2 9 tri line l A8 +E3 10 tri line l A9 +C1 11 tri line l A10 +B1 12 tri line l A11 +D3 14 tri line l A12 +C2 15 tri line l A13 +A1 16 tri line l A14 +D4 17 tri line l A15 +D5 19 tri line l A16 +C3 20 tri line l A17 +B2 21 tri line l A18 +B3 22 tri line l A19 +B4 24 tri line l A20 +A2 25 tri line l A21 +A3 26 tri line l A22 +C5 27 tri line l A23 +DUMMY1 1001 pas line l DUMMY1 +B11 48 tri line l D0 +C10 47 tri line l D1 +B10 46 tri line l D2 +A12 45 tri line l D3 +C9 43 tri line l D4 +B9 42 tri line l D5 +A10 41 tri line l D6 +A9 40 tri line l D7 +B8 38 tri line l D8 +A8 37 tri line l D9 +B7 36 tri line l D10 +C7 35 tri line l D11 +A6 33 tri line l D12 +B6 32 tri line l D13 +C6 31 tri line l D14 +A5 30 tri line l D15 + +M6 104 tri line r _AS_ +N6 103 tri line r R/_W_ +N5 106 tri line r _UDS_/A0 +L6 105 tri line r _LDS_/_DS_ +K9 85 tri line r _DTACK_ +K2 123 out line r _RMC_/_IOUT1_ +K3 122 out line r IAC +L11 86 oc line r _BCLR_ +DUMMY2 1002 pas line r DUMMY2 +M10 90 io line r _BR_ +M12 87 io line r _BG_ +M11 88 io line r _BGACK_ +DUMMY3 1003 pas line r DUMMY3 +N11 92 oc line r _RESET_ +N12 91 oc line r _HALT_ +M9 94 oc line r _BERR_ +K13 74 in line r BUSW +J13 73 in line r DISCPU +DUMMY4 1004 pas line r DUMMY4 +L8 97 in line r _IPL0_/_IRQ1_ +N9 96 in line r _IPL1_/_IRQ6_ +N10 95 in line r _IPL2_/_IRQ7_ +H1 132 tri line r FC0 +H3 130 tri line r FC1 +J1 129 tri line r FC2 +L9 93 io line r _AVEC_/_IOUT0_ +DUMMY5 1005 pas line r DUMMY5 +K1 128 out line r _CS0_/_IOUT2_ +J2 127 out line r _CS1_ +L1 125 out line r _CS2_ +M1 124 out line r _CS3_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302_PGA-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,471 @@ +v 20040111 1 +T 4100 11000 8 10 1 1 0 6 1 +refdes=U? +T 500 10950 9 10 1 0 0 0 1 +MC68302 +T 500 11150 5 10 0 0 0 0 1 +device=MC68302 +T 500 11350 5 10 0 0 0 0 1 +footprint=PGA132 +T 500 11550 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 500 11750 5 10 0 0 0 0 1 +documentation= +T 500 11950 5 10 0 0 0 0 1 +description=MC68302 IMP, peripherals (2 of 3) +T 500 12150 5 10 0 0 0 0 1 +numslots=0 +T 500 12350 5 10 0 0 0 0 1 +comment=pinseq numbers are PQFP package pins +P 4400 10500 4100 10500 1 0 0 +{ +T 4200 10550 5 8 1 1 0 0 1 +pinnumber=A13 +T 4200 10450 5 8 0 1 0 2 1 +pinseq=52 +T 4050 10500 9 8 1 1 0 6 1 +pinlabel=RxD1/L1RxD +T 4050 10500 5 8 0 1 0 8 1 +pintype=in +} +P 4400 10100 4100 10100 1 0 0 +{ +T 4200 10150 5 8 1 1 0 0 1 +pinnumber=K11 +T 4200 10050 5 8 0 1 0 2 1 +pinseq=80 +T 4050 10100 9 8 1 1 0 6 1 +pinlabel=TxD1/L1TxD +T 4050 10100 5 8 0 1 0 8 1 +pintype=out +} +P 4400 9700 4100 9700 1 0 0 +{ +T 4200 9750 5 8 1 1 0 0 1 +pinnumber=N13 +T 4200 9650 5 8 0 1 0 2 1 +pinseq=82 +T 4050 9700 9 8 1 1 0 6 1 +pinlabel=RCLK1/L1CLK +T 4050 9700 5 8 0 1 0 8 1 +pintype=io +} +P 4400 9300 4100 9300 1 0 0 +{ +T 4200 9350 5 8 1 1 0 0 1 +pinnumber=L12 +T 4200 9250 5 8 0 1 0 2 1 +pinseq=81 +T 4050 9300 9 8 1 1 0 6 1 +pinlabel=TCLK1/L1SY0/SDS1 +T 4050 9300 5 8 0 1 0 8 1 +pintype=io +} +P 4400 8900 4100 8900 1 0 0 +{ +T 4200 8950 5 8 1 1 0 0 1 +pinnumber=C11 +T 4200 8850 5 8 0 1 0 2 1 +pinseq=50 +T 4050 8900 9 8 1 1 0 6 1 +pinlabel=CD1/L1SY1 +T 4050 8900 5 8 0 1 0 8 1 +pintype=in +} +L 3282 9024 3562 9024 3 0 0 0 -1 -1 +P 4400 8500 4100 8500 1 0 0 +{ +T 4200 8550 5 8 1 1 0 0 1 +pinnumber=D10 +T 4200 8450 5 8 0 1 0 2 1 +pinseq=51 +T 4050 8500 9 8 1 1 0 6 1 +pinlabel=CTS1/L1GR +T 4050 8500 5 8 0 1 0 8 1 +pintype=in +} +L 3234 8624 3602 8624 3 0 0 0 -1 -1 +P 4400 8100 4100 8100 1 0 0 +{ +T 4200 8150 5 8 1 1 0 0 1 +pinnumber=K12 +T 4200 8050 5 8 0 1 0 2 1 +pinseq=79 +T 4050 8100 9 8 1 1 0 6 1 +pinlabel=RTS1/L1RQ/GCIDCL +T 4050 8100 5 8 0 1 0 8 1 +pintype=out +} +L 2590 8224 2950 8224 3 0 0 0 -1 -1 +P 4400 7700 4100 7700 1 0 0 +{ +T 4200 7750 5 8 1 1 0 0 1 +pinnumber=J11 +T 4200 7650 5 8 0 1 0 2 1 +pinseq=76 +T 4050 7700 9 8 1 1 0 6 1 +pinlabel=BRG1 +T 4050 7700 5 8 0 1 0 8 1 +pintype=out +} +P 4400 6900 4100 6900 1 0 0 +{ +T 4200 6950 5 8 1 1 0 0 1 +pinnumber=D9 +T 4200 6850 5 8 0 1 0 2 1 +pinseq=53 +T 4050 6900 9 8 1 1 0 6 1 +pinlabel=RxD2/PA0 +T 4050 6900 5 8 0 1 0 8 1 +pintype=io +} +P 4400 6500 4100 6500 1 0 0 +{ +T 4200 6550 5 8 1 1 0 0 1 +pinnumber=E10 +T 4200 6450 5 8 0 1 0 2 1 +pinseq=54 +T 4050 6500 9 8 1 1 0 6 1 +pinlabel=TxD2/PA1 +T 4050 6500 5 8 0 1 0 8 1 +pintype=io +} +P 4400 6100 4100 6100 1 0 0 +{ +T 4200 6150 5 8 1 1 0 0 1 +pinnumber=C12 +T 4200 6050 5 8 0 1 0 2 1 +pinseq=55 +T 4050 6100 9 8 1 1 0 6 1 +pinlabel=RCLK2/PA2 +T 4050 6100 5 8 0 1 0 8 1 +pintype=io +} +P 4400 5700 4100 5700 1 0 0 +{ +T 4200 5750 5 8 1 1 0 0 1 +pinnumber=D11 +T 4200 5650 5 8 0 1 0 2 1 +pinseq=56 +T 4050 5700 9 8 1 1 0 6 1 +pinlabel=TCLK2/PA3 +T 4050 5700 5 8 0 1 0 8 1 +pintype=io +} +P 4400 5300 4100 5300 1 0 0 +{ +T 4200 5350 5 8 1 1 0 0 1 +pinnumber=B13 +T 4200 5250 5 8 0 1 0 2 1 +pinseq=58 +T 4050 5300 9 8 1 1 0 6 1 +pinlabel=CTS2/PA4 +T 4050 5300 5 8 0 1 0 8 1 +pintype=io +} +L 3250 5424 3658 5424 3 0 0 0 -1 -1 +P 4400 4900 4100 4900 1 0 0 +{ +T 4200 4950 5 8 1 1 0 0 1 +pinnumber=C13 +T 4200 4850 5 8 0 1 0 2 1 +pinseq=59 +T 4050 4900 9 8 1 1 0 6 1 +pinlabel=RTS2/PA5 +T 4050 4900 5 8 0 1 0 8 1 +pintype=io +} +L 3282 5024 3682 5024 3 0 0 0 -1 -1 +P 4400 4500 4100 4500 1 0 0 +{ +T 4200 4550 5 8 1 1 0 0 1 +pinnumber=E11 +T 4200 4450 5 8 0 1 0 2 1 +pinseq=60 +T 4050 4500 9 8 1 1 0 6 1 +pinlabel=CD2/PA6 +T 4050 4500 5 8 0 1 0 8 1 +pintype=io +} +L 3346 4624 3666 4624 3 0 0 0 -1 -1 +P 4400 4100 4100 4100 1 0 0 +{ +T 4200 4150 5 8 1 1 0 0 1 +pinnumber=E12 +T 4200 4050 5 8 0 1 0 2 1 +pinseq=61 +T 4050 4100 9 8 1 1 0 6 1 +pinlabel=BRG2/SDS2/PA7 +T 4050 4100 5 8 0 1 0 8 1 +pintype=io +} +P 4400 3300 4100 3300 1 0 0 +{ +T 4200 3350 5 8 1 1 0 0 1 +pinnumber=E13 +T 4200 3250 5 8 0 1 0 2 1 +pinseq=63 +T 4050 3300 9 8 1 1 0 6 1 +pinlabel=RxD3/PA8 +T 4050 3300 5 8 0 1 0 8 1 +pintype=io +} +P 4400 2900 4100 2900 1 0 0 +{ +T 4200 2950 5 8 1 1 0 0 1 +pinnumber=F11 +T 4200 2850 5 8 0 1 0 2 1 +pinseq=64 +T 4050 2900 9 8 1 1 0 6 1 +pinlabel=TxD3/PA9 +T 4050 2900 5 8 0 1 0 8 1 +pintype=io +} +P 4400 2500 4100 2500 1 0 0 +{ +T 4200 2550 5 8 1 1 0 0 1 +pinnumber=F12 +T 4200 2450 5 8 0 1 0 2 1 +pinseq=65 +T 4050 2500 9 8 1 1 0 6 1 +pinlabel=RCLK3/PA10 +T 4050 2500 5 8 0 1 0 8 1 +pintype=io +} +P 4400 2100 4100 2100 1 0 0 +{ +T 4200 2150 5 8 1 1 0 0 1 +pinnumber=F13 +T 4200 2050 5 8 0 1 0 2 1 +pinseq=66 +T 4050 2100 9 8 1 1 0 6 1 +pinlabel=TCLK3/PA11 +T 4050 2100 5 8 0 1 0 8 1 +pintype=io +} +P 4400 1700 4100 1700 1 0 0 +{ +T 4200 1750 5 8 1 1 0 0 1 +pinnumber=B12 +T 4200 1650 5 8 0 1 0 2 1 +pinseq=49 +T 4050 1700 9 8 1 1 0 6 1 +pinlabel=CTS3/SPRxD +T 4050 1700 5 8 0 1 0 8 1 +pintype=in +} +L 3102 1824 3494 1824 3 0 0 0 -1 -1 +P 4400 1300 4100 1300 1 0 0 +{ +T 4200 1350 5 8 1 1 0 0 1 +pinnumber=M13 +T 4200 1250 5 8 0 1 0 2 1 +pinseq=78 +T 4050 1300 9 8 1 1 0 6 1 +pinlabel=RTS3/SPTxD +T 4050 1300 5 8 0 1 0 8 1 +pintype=out +} +L 3122 1424 3506 1424 3 0 0 0 -1 -1 +P 4400 900 4100 900 1 0 0 +{ +T 4200 950 5 8 1 1 0 0 1 +pinnumber=L13 +T 4200 850 5 8 0 1 0 2 1 +pinseq=77 +T 4050 900 9 8 1 1 0 6 1 +pinlabel=CD3/SPCLK +T 4050 900 5 8 0 1 0 8 1 +pintype=io +} +L 3166 1024 3470 1024 3 0 0 0 -1 -1 +P 4400 500 4100 500 1 0 0 +{ +T 4200 550 5 8 1 1 0 0 1 +pinnumber=G11 +T 4200 450 5 8 0 1 0 2 1 +pinseq=68 +T 4050 500 9 8 1 1 0 6 1 +pinlabel=BRG3/PA12 +T 4050 500 5 8 0 1 0 8 1 +pintype=io +} +P 200 10500 500 10500 1 0 0 +{ +T 400 10550 5 8 1 1 0 6 1 +pinnumber=G12 +T 400 10450 5 8 0 1 0 8 1 +pinseq=69 +T 550 10500 9 8 1 1 0 0 1 +pinlabel=DREQ/PA13 +T 550 10500 5 8 0 1 0 2 1 +pintype=io +} +L 550 10624 1002 10624 3 0 0 0 -1 -1 +P 200 10100 500 10100 1 0 0 +{ +T 400 10150 5 8 1 1 0 6 1 +pinnumber=H13 +T 400 10050 5 8 0 1 0 8 1 +pinseq=70 +T 550 10100 9 8 1 1 0 0 1 +pinlabel=DACK/PA14 +T 550 10100 5 8 0 1 0 2 1 +pintype=io +} +L 550 10224 990 10224 3 0 0 0 -1 -1 +P 200 9700 500 9700 1 0 0 +{ +T 400 9750 5 8 1 1 0 6 1 +pinnumber=H12 +T 400 9650 5 8 0 1 0 8 1 +pinseq=71 +T 550 9700 9 8 1 1 0 0 1 +pinlabel=DONE/PA15 +T 550 9700 5 8 0 1 0 2 1 +pintype=io +} +L 550 9824 1010 9824 3 0 0 0 -1 -1 +P 200 8900 500 8900 1 0 0 +{ +T 400 8950 5 8 1 1 0 6 1 +pinnumber=M5 +T 400 8850 5 8 0 1 0 8 1 +pinseq=108 +T 550 8900 9 8 1 1 0 0 1 +pinlabel=IACK7/PB0 +T 550 8900 5 8 0 1 0 2 1 +pintype=io +} +L 550 9024 1002 9024 3 0 0 0 -1 -1 +P 200 8500 500 8500 1 0 0 +{ +T 400 8550 5 8 1 1 0 6 1 +pinnumber=L5 +T 400 8450 5 8 0 1 0 8 1 +pinseq=109 +T 550 8500 9 8 1 1 0 0 1 +pinlabel=IACK6/PB1 +T 550 8500 5 8 0 1 0 2 1 +pintype=io +} +L 550 8624 1018 8624 3 0 0 0 -1 -1 +P 200 8100 500 8100 1 0 0 +{ +T 400 8150 5 8 1 1 0 6 1 +pinnumber=N3 +T 400 8050 5 8 0 1 0 8 1 +pinseq=110 +T 550 8100 9 8 1 1 0 0 1 +pinlabel=IACK1/PB2 +T 550 8100 5 8 0 1 0 2 1 +pintype=io +} +L 550 8224 986 8224 3 0 0 0 -1 -1 +P 200 7300 500 7300 1 0 0 +{ +T 400 7350 5 8 1 1 0 6 1 +pinnumber=N2 +T 400 7250 5 8 0 1 0 8 1 +pinseq=111 +T 550 7300 9 8 1 1 0 0 1 +pinlabel=TIN1/PB3 +T 550 7300 5 8 0 1 0 2 1 +pintype=io +} +P 200 6900 500 6900 1 0 0 +{ +T 400 6950 5 8 1 1 0 6 1 +pinnumber=L4 +T 400 6850 5 8 0 1 0 8 1 +pinseq=113 +T 550 6900 9 8 1 1 0 0 1 +pinlabel=TOUT1/PB4 +T 550 6900 5 8 0 1 0 2 1 +pintype=io +} +L 550 7024 1034 7024 3 0 0 0 -1 -1 +P 200 6500 500 6500 1 0 0 +{ +T 400 6550 5 8 1 1 0 6 1 +pinnumber=M3 +T 400 6450 5 8 0 1 0 8 1 +pinseq=114 +T 550 6500 9 8 1 1 0 0 1 +pinlabel=TIN2/PB5 +T 550 6500 5 8 0 1 0 2 1 +pintype=io +} +P 200 6100 500 6100 1 0 0 +{ +T 400 6150 5 8 1 1 0 6 1 +pinnumber=M2 +T 400 6050 5 8 0 1 0 8 1 +pinseq=115 +T 550 6100 9 8 1 1 0 0 1 +pinlabel=TOUT2/PB6 +T 550 6100 5 8 0 1 0 2 1 +pintype=io +} +L 550 6224 1074 6224 3 0 0 0 -1 -1 +P 200 5700 500 5700 1 0 0 +{ +T 400 5750 5 8 1 1 0 6 1 +pinnumber=K5 +T 400 5650 5 8 0 1 0 8 1 +pinseq=117 +T 550 5700 9 8 1 1 0 0 1 +pinlabel=WDOG/PB7 +T 550 5700 5 8 0 1 0 2 1 +pintype=io +} +L 550 5824 1050 5824 3 0 0 0 -1 -1 +P 200 4900 500 4900 1 0 0 +{ +T 400 4950 5 8 1 1 0 6 1 +pinnumber=J4 +T 400 4850 5 8 0 1 0 8 1 +pinseq=118 +T 550 4900 9 8 1 1 0 0 1 +pinlabel=PB8 +T 550 4900 5 8 0 1 0 2 1 +pintype=io +} +P 200 4500 500 4500 1 0 0 +{ +T 400 4550 5 8 1 1 0 6 1 +pinnumber=K4 +T 400 4450 5 8 0 1 0 8 1 +pinseq=119 +T 550 4500 9 8 1 1 0 0 1 +pinlabel=PB9 +T 550 4500 5 8 0 1 0 2 1 +pintype=io +} +P 200 4100 500 4100 1 0 0 +{ +T 400 4150 5 8 1 1 0 6 1 +pinnumber=N1 +T 400 4050 5 8 0 1 0 8 1 +pinseq=120 +T 550 4100 9 8 1 1 0 0 1 +pinlabel=PB10 +T 550 4100 5 8 0 1 0 2 1 +pintype=io +} +P 200 3700 500 3700 1 0 0 +{ +T 400 3750 5 8 1 1 0 6 1 +pinnumber=L2 +T 400 3650 5 8 0 1 0 8 1 +pinseq=121 +T 550 3700 9 8 1 1 0 0 1 +pinlabel=PB11 +T 550 3700 5 8 0 1 0 2 1 +pintype=io +} +B 500 100 3600 10800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1100 2500 9 10 1 0 0 0 1 +PERIPHERALS +T 1500 2200 9 10 1 0 0 0 1 +2 OF 3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302_PGA-2.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,96 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=no +sym_width=3600 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MC68302 +device=MC68302 +refdes=U? +footprint=PGA132 +description=MC68302 IMP, peripherals (2 of 3) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=pinseq numbers are PQFP package pins +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +A13 52 in line r RxD1/L1RxD +K11 80 out line r TxD1/L1TxD +N13 82 io line r RCLK1/L1CLK +L12 81 io line r TCLK1/L1SY0/SDS1 +C11 50 in line r _CD1_/L1SY1 +D10 51 in line r _CTS1_/L1GR +K12 79 out line r _RTS1_/L1RQ/GCIDCL +J11 76 out line r BRG1 +DUMMY1 1001 pas line r DUMMY1 +D9 53 io line r RxD2/PA0 +E10 54 io line r TxD2/PA1 +C12 55 io line r RCLK2/PA2 +D11 56 io line r TCLK2/PA3 +B13 58 io line r _CTS2_/PA4 +C13 59 io line r _RTS2_/PA5 +E11 60 io line r _CD2_/PA6 +E12 61 io line r BRG2/SDS2/PA7 +DUMMY2 1002 pas line r DUMMY2 +E13 63 io line r RxD3/PA8 +F11 64 io line r TxD3/PA9 +F12 65 io line r RCLK3/PA10 +F13 66 io line r TCLK3/PA11 +B12 49 in line r _CTS3_/SPRxD +M13 78 out line r _RTS3_/SPTxD +L13 77 io line r _CD3_/SPCLK +G11 68 io line r BRG3/PA12 + +G12 69 io line l _DREQ_/PA13 +H13 70 io line l _DACK_/PA14 +H12 71 io line l _DONE_/PA15 +DUMMY3 1003 pas line l DUMMY3 +M5 108 io line l _IACK7_/PB0 +L5 109 io line l _IACK6_/PB1 +N3 110 io line l _IACK1_/PB2 +DUMMY4 1004 pas line l DUMMY4 +N2 111 io line l TIN1/PB3 +L4 113 io line l _TOUT1_/PB4 +M3 114 io line l TIN2/PB5 +M2 115 io line l _TOUT2_/PB6 +K5 117 io line l _WDOG_/PB7 +DUMMY5 1005 pas line l DUMMY5 +J4 118 io line l PB8 +K4 119 io line l PB9 +N1 120 io line l PB10 +L2 121 io line l PB11
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302_PGA-3.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,322 @@ +v 20040111 1 +T 5600 3200 8 10 1 1 0 6 1 +refdes=U? +T 400 3150 9 10 1 0 0 0 1 +MC68302 +T 400 3350 5 10 0 0 0 0 1 +device=MC68302 +T 400 3550 5 10 0 0 0 0 1 +footprint=PGA132 +T 400 3750 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 3950 5 10 0 0 0 0 1 +documentation= +T 400 4150 5 10 0 0 0 0 1 +description=MC68302 IMP, power and clock (3 of 3) +T 400 4350 5 10 0 0 0 0 1 +numslots=0 +T 400 4550 5 10 0 0 0 0 1 +comment=pinseq numbers are PQFP package pins +P 100 2300 400 2300 1 0 0 +{ +T 300 2350 5 8 1 1 0 6 1 +pinnumber=N7 +T 300 2250 5 8 0 1 0 8 1 +pinseq=100 +T 450 2300 9 8 1 1 0 0 1 +pinlabel=EXTAL +T 450 2300 5 8 0 1 0 2 1 +pintype=clk +} +P 100 1900 400 1900 1 0 0 +{ +T 300 1950 5 8 1 1 0 6 1 +pinnumber=L7 +T 300 1850 5 8 0 1 0 8 1 +pinseq=101 +T 450 1900 9 8 1 1 0 0 1 +pinlabel=XTAL +T 450 1900 5 8 0 1 0 2 1 +pintype=out +} +P 100 1100 400 1100 1 0 0 +{ +T 300 1150 5 8 1 1 0 6 1 +pinnumber=H11 +T 300 1050 5 8 0 1 0 8 1 +pinseq=72 +T 450 1100 9 8 1 1 0 0 1 +pinlabel=FRZ +T 450 1100 5 8 0 1 0 2 1 +pintype=in +} +L 450 1224 746 1224 3 0 0 0 -1 -1 +P 5900 2300 5600 2300 1 0 0 +{ +T 5700 2350 5 8 1 1 0 0 1 +pinnumber=M8 +T 5700 2250 5 8 0 1 0 2 1 +pinseq=98 +T 5550 2300 9 8 1 1 0 6 1 +pinlabel=CLKO +T 5550 2300 5 8 0 1 0 8 1 +pintype=out +} +P 5900 1500 5600 1500 1 0 0 +{ +T 5700 1550 5 8 1 1 0 0 1 +pinnumber=L10 +T 5700 1450 5 8 0 1 0 2 1 +pinseq=89 +T 5550 1500 9 8 1 1 0 6 1 +pinlabel=NC1 +T 5550 1500 5 8 0 1 0 8 1 +pintype=out +} +P 5900 1100 5600 1100 1 0 0 +{ +T 5700 1150 5 8 1 1 0 0 1 +pinnumber=J12 +T 5700 1050 5 8 0 1 0 2 1 +pinseq=75 +T 5550 1100 9 8 1 1 0 6 1 +pinlabel=NC3 +T 5550 1100 5 8 0 1 0 8 1 +pintype=out +} +P 600 0 600 300 1 0 0 +{ +T 650 100 5 8 1 1 0 0 1 +pinnumber=N4 +T 650 100 5 8 0 1 0 2 1 +pinseq=4 +T 600 350 9 8 1 1 0 3 1 +pinlabel=GND +T 600 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=M7 +T 1050 100 5 8 0 1 0 2 1 +pinseq=13 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1400 0 1400 300 1 0 0 +{ +T 1450 100 5 8 1 1 0 0 1 +pinnumber=L3 +T 1450 100 5 8 0 1 0 2 1 +pinseq=23 +T 1400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1400 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1800 0 1800 300 1 0 0 +{ +T 1850 100 5 8 1 1 0 0 1 +pinnumber=J3 +T 1850 100 5 8 0 1 0 2 1 +pinseq=29 +T 1800 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1800 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 2200 0 2200 300 1 0 0 +{ +T 2250 100 5 8 1 1 0 0 1 +pinnumber=J10 +T 2250 100 5 8 0 1 0 2 1 +pinseq=34 +T 2200 350 9 8 1 1 0 3 1 +pinlabel=GND +T 2200 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 2600 0 2600 300 1 0 0 +{ +T 2650 100 5 8 1 1 0 0 1 +pinnumber=G13 +T 2650 100 5 8 0 1 0 2 1 +pinseq=44 +T 2600 350 9 8 1 1 0 3 1 +pinlabel=GND +T 2600 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 3000 0 3000 300 1 0 0 +{ +T 3050 100 5 8 1 1 0 0 1 +pinnumber=F1 +T 3050 100 5 8 0 1 0 2 1 +pinseq=57 +T 3000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 3000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 3400 0 3400 300 1 0 0 +{ +T 3450 100 5 8 1 1 0 0 1 +pinnumber=D2 +T 3450 100 5 8 0 1 0 2 1 +pinseq=67 +T 3400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 3400 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 3800 0 3800 300 1 0 0 +{ +T 3850 100 5 8 1 1 0 0 1 +pinnumber=D12 +T 3850 100 5 8 0 1 0 2 1 +pinseq=84 +T 3800 350 9 8 1 1 0 3 1 +pinlabel=GND +T 3800 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 4200 0 4200 300 1 0 0 +{ +T 4250 100 5 8 1 1 0 0 1 +pinnumber=C4 +T 4250 100 5 8 0 1 0 2 1 +pinseq=102 +T 4200 350 9 8 1 1 0 3 1 +pinlabel=GND +T 4200 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 4600 0 4600 300 1 0 0 +{ +T 4650 100 5 8 1 1 0 0 1 +pinnumber=A4 +T 4650 100 5 8 0 1 0 2 1 +pinseq=107 +T 4600 350 9 8 1 1 0 3 1 +pinlabel=GND +T 4600 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 5000 0 5000 300 1 0 0 +{ +T 5050 100 5 8 1 1 0 0 1 +pinnumber=A7 +T 5050 100 5 8 0 1 0 2 1 +pinseq=116 +T 5000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 5000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 5400 0 5400 300 1 0 0 +{ +T 5450 100 5 8 1 1 0 0 1 +pinnumber=A11 +T 5450 100 5 8 0 1 0 2 1 +pinseq=126 +T 5400 350 9 8 1 1 0 3 1 +pinlabel=GND +T 5400 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1400 3400 1400 3100 1 0 0 +{ +T 1450 3200 5 8 1 1 0 0 1 +pinnumber=N8 +T 1450 3200 5 8 0 1 0 2 1 +pinseq=18 +T 1400 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 1400 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 1900 3400 1900 3100 1 0 0 +{ +T 1950 3200 5 8 1 1 0 0 1 +pinnumber=M4 +T 1950 3200 5 8 0 1 0 2 1 +pinseq=28 +T 1900 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 1900 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 2400 3400 2400 3100 1 0 0 +{ +T 2450 3200 5 8 1 1 0 0 1 +pinnumber=K10 +T 2450 3200 5 8 0 1 0 2 1 +pinseq=39 +T 2400 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 2400 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 2900 3400 2900 3100 1 0 0 +{ +T 2950 3200 5 8 1 1 0 0 1 +pinnumber=H2 +T 2950 3200 5 8 0 1 0 2 1 +pinseq=62 +T 2900 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 2900 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 3400 3400 3400 3100 1 0 0 +{ +T 3450 3200 5 8 1 1 0 0 1 +pinnumber=E4 +T 3450 3200 5 8 0 1 0 2 1 +pinseq=83 +T 3400 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 3400 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 3900 3400 3900 3100 1 0 0 +{ +T 3950 3200 5 8 1 1 0 0 1 +pinnumber=D13 +T 3950 3200 5 8 0 1 0 2 1 +pinseq=99 +T 3900 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 3900 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 4400 3400 4400 3100 1 0 0 +{ +T 4450 3200 5 8 1 1 0 0 1 +pinnumber=C8 +T 4450 3200 5 8 0 1 0 2 1 +pinseq=112 +T 4400 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 4400 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 4900 3400 4900 3100 1 0 0 +{ +T 4950 3200 5 8 1 1 0 0 1 +pinnumber=B5 +T 4950 3200 5 8 0 1 0 2 1 +pinseq=131 +T 4900 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 4900 2900 5 8 0 1 0 5 1 +pintype=pwr +} +B 400 300 5200 2800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 2400 1800 9 10 1 0 0 0 1 +POWER & CLOCK +T 3000 1500 9 10 1 0 0 0 1 +3 OF 3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302_PGA-3.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,87 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=no +sym_width=5200 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MC68302 +device=MC68302 +refdes=U? +footprint=PGA132 +description=MC68302 IMP, power and clock (3 of 3) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +comment=pinseq numbers are PQFP package pins +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +DUMMY1 1001 pas line l DUMMY1 +N7 100 clk line l EXTAL +L7 101 out line l XTAL +DUMMY2 1002 pas line l DUMMY2 +H11 72 in line l _FRZ_ +DUMMY3 1003 pas line l DUMMY3 + +DUMMY4 1004 pas line r DUMMY4 +M8 98 out line r CLKO +DUMMY5 1005 pas line r DUMMY5 +L10 89 out line r NC1 +J12 75 out line r NC3 +DUMMY6 1006 pas line r DUMMY6 + +N4 4 pwr line b GND +M7 13 pwr line b GND +L3 23 pwr line b GND +J3 29 pwr line b GND +J10 34 pwr line b GND +G13 44 pwr line b GND +F1 57 pwr line b GND +D2 67 pwr line b GND +D12 84 pwr line b GND +C4 102 pwr line b GND +A4 107 pwr line b GND +A7 116 pwr line b GND +A11 126 pwr line b GND + +N8 18 pwr line t VDD +M4 28 pwr line t VDD +K10 39 pwr line t VDD +H2 62 pwr line t VDD +E4 83 pwr line t VDD +D13 99 pwr line t VDD +C8 112 pwr line t VDD +B5 131 pwr line t VDD
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/MC68302_PQFP-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,776 @@ +v 20040111 1 +T 3300 16700 8 10 1 1 0 6 1 +refdes=U? +T 500 16650 9 10 1 0 0 0 1 +MC68302 +T 500 16850 5 10 0 0 0 0 1 +device=MC68302 +T 500 17050 5 10 0 0 0 0 1 +footprint=QFP132 +T 500 17250 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 500 17450 5 10 0 0 0 0 1 +documentation= +T 500 17650 5 10 0 0 0 0 1 +description=MC68302 IMP, M68K bus (1 of 3) +T 500 17850 5 10 0 0 0 0 1 +numslots=0 +P 200 16200 500 16200 1 0 0 +{ +T 400 16250 5 8 1 1 0 6 1 +pinnumber=1 +T 400 16150 5 8 0 1 0 8 1 +pinseq=1 +T 550 16200 9 8 1 1 0 0 1 +pinlabel=A1 +T 550 16200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 15800 500 15800 1 0 0 +{ +T 400 15850 5 8 1 1 0 6 1 +pinnumber=2 +T 400 15750 5 8 0 1 0 8 1 +pinseq=2 +T 550 15800 9 8 1 1 0 0 1 +pinlabel=A2 +T 550 15800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 15400 500 15400 1 0 0 +{ +T 400 15450 5 8 1 1 0 6 1 +pinnumber=3 +T 400 15350 5 8 0 1 0 8 1 +pinseq=3 +T 550 15400 9 8 1 1 0 0 1 +pinlabel=A3 +T 550 15400 5 8 0 1 0 2 1 +pintype=tri +} +P 200 15000 500 15000 1 0 0 +{ +T 400 15050 5 8 1 1 0 6 1 +pinnumber=5 +T 400 14950 5 8 0 1 0 8 1 +pinseq=5 +T 550 15000 9 8 1 1 0 0 1 +pinlabel=A4 +T 550 15000 5 8 0 1 0 2 1 +pintype=tri +} +P 200 14600 500 14600 1 0 0 +{ +T 400 14650 5 8 1 1 0 6 1 +pinnumber=6 +T 400 14550 5 8 0 1 0 8 1 +pinseq=6 +T 550 14600 9 8 1 1 0 0 1 +pinlabel=A5 +T 550 14600 5 8 0 1 0 2 1 +pintype=tri +} +P 200 14200 500 14200 1 0 0 +{ +T 400 14250 5 8 1 1 0 6 1 +pinnumber=7 +T 400 14150 5 8 0 1 0 8 1 +pinseq=7 +T 550 14200 9 8 1 1 0 0 1 +pinlabel=A6 +T 550 14200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 13800 500 13800 1 0 0 +{ +T 400 13850 5 8 1 1 0 6 1 +pinnumber=8 +T 400 13750 5 8 0 1 0 8 1 +pinseq=8 +T 550 13800 9 8 1 1 0 0 1 +pinlabel=A7 +T 550 13800 5 8 0 1 0 2 1 +pintype=tri +} +P 200 13400 500 13400 1 0 0 +{ +T 400 13450 5 8 1 1 0 6 1 +pinnumber=9 +T 400 13350 5 8 0 1 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3400 3100 1 0 0 +{ +T 3450 3200 5 8 1 1 0 0 1 +pinnumber=83 +T 3450 3200 5 8 0 1 0 2 1 +pinseq=83 +T 3400 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 3400 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 3900 3400 3900 3100 1 0 0 +{ +T 3950 3200 5 8 1 1 0 0 1 +pinnumber=99 +T 3950 3200 5 8 0 1 0 2 1 +pinseq=99 +T 3900 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 3900 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 4400 3400 4400 3100 1 0 0 +{ +T 4450 3200 5 8 1 1 0 0 1 +pinnumber=112 +T 4450 3200 5 8 0 1 0 2 1 +pinseq=112 +T 4400 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 4400 2900 5 8 0 1 0 5 1 +pintype=pwr +} +P 4900 3400 4900 3100 1 0 0 +{ +T 4950 3200 5 8 1 1 0 0 1 +pinnumber=131 +T 4950 3200 5 8 0 1 0 2 1 +pinseq=131 +T 4900 3050 9 8 1 1 0 5 1 +pinlabel=VDD +T 4900 2900 5 8 0 1 0 5 1 +pintype=pwr +} +B 400 300 5200 2800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 2400 1800 9 10 1 0 0 0 1 +POWER & CLOCK +T 3000 1500 9 10 1 0 0 0 1 +3 OF 3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,306 @@ +v 20040111 1 +T 3200 10600 8 10 1 1 0 6 1 +refdes=U? +T 400 10550 9 10 1 0 0 0 1 +RS8973 +T 400 10750 5 10 0 0 0 0 1 +device=RS8973 +T 400 10950 5 10 0 0 0 0 1 +footprint=QFP100_R +T 400 11150 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 11350 5 10 0 0 0 0 1 +documentation= +T 400 11550 5 10 0 0 0 0 1 +description=RS8973 bitpump, MCI (1 of 5) +T 400 11750 5 10 0 0 0 0 1 +numslots=0 +P 100 10100 400 10100 1 0 0 +{ +T 300 10150 5 8 1 1 0 6 1 +pinnumber=19 +T 300 10050 5 8 0 1 0 8 1 +pinseq=19 +T 450 10100 9 8 1 1 0 0 1 +pinlabel=MOTEL +T 450 10100 5 8 0 1 0 2 1 +pintype=in +} +L 706 10224 1002 10224 3 0 0 0 -1 -1 +P 100 9700 400 9700 1 0 0 +{ +T 300 9750 5 8 1 1 0 6 1 +pinnumber=5 +T 300 9650 5 8 0 1 0 8 1 +pinseq=5 +T 450 9700 9 8 1 1 0 0 1 +pinlabel=ALE +T 450 9700 5 8 0 1 0 2 1 +pintype=in +} +P 100 9300 400 9300 1 0 0 +{ +T 300 9350 5 8 1 1 0 6 1 +pinnumber=2 +T 300 9250 5 8 0 1 0 8 1 +pinseq=2 +T 450 9300 9 8 1 1 0 0 1 +pinlabel=CS +T 450 9300 5 8 0 1 0 2 1 +pintype=in +} +L 450 9424 662 9424 3 0 0 0 -1 -1 +P 100 8900 400 8900 1 0 0 +{ +T 300 8950 5 8 1 1 0 6 1 +pinnumber=3 +T 300 8850 5 8 0 1 0 8 1 +pinseq=3 +T 450 8900 9 8 1 1 0 0 1 +pinlabel=RD/DS +T 450 8900 5 8 0 1 0 2 1 +pintype=in +} +L 450 9024 658 9024 3 0 0 0 -1 -1 +L 730 9024 934 9024 3 0 0 0 -1 -1 +P 100 8500 400 8500 1 0 0 +{ +T 300 8550 5 8 1 1 0 6 1 +pinnumber=4 +T 300 8450 5 8 0 1 0 8 1 +pinseq=4 +T 450 8500 9 8 1 1 0 0 1 +pinlabel=WR/R/W +T 450 8500 5 8 0 1 0 2 1 +pintype=in +} +L 450 8624 702 8624 3 0 0 0 -1 -1 +L 950 8624 1098 8624 3 0 0 0 -1 -1 +P 100 7700 400 7700 1 0 0 +{ +T 300 7750 5 8 1 1 0 6 1 +pinnumber=8 +T 300 7650 5 8 0 1 0 8 1 +pinseq=8 +T 450 7700 9 8 1 1 0 0 1 +pinlabel=AD0 +T 450 7700 5 8 0 1 0 2 1 +pintype=tri +} +P 100 7300 400 7300 1 0 0 +{ +T 300 7350 5 8 1 1 0 6 1 +pinnumber=9 +T 300 7250 5 8 0 1 0 8 1 +pinseq=9 +T 450 7300 9 8 1 1 0 0 1 +pinlabel=AD1 +T 450 7300 5 8 0 1 0 2 1 +pintype=tri +} +P 100 6900 400 6900 1 0 0 +{ +T 300 6950 5 8 1 1 0 6 1 +pinnumber=10 +T 300 6850 5 8 0 1 0 8 1 +pinseq=10 +T 450 6900 9 8 1 1 0 0 1 +pinlabel=AD2 +T 450 6900 5 8 0 1 0 2 1 +pintype=tri +} +P 100 6500 400 6500 1 0 0 +{ +T 300 6550 5 8 1 1 0 6 1 +pinnumber=11 +T 300 6450 5 8 0 1 0 8 1 +pinseq=11 +T 450 6500 9 8 1 1 0 0 1 +pinlabel=AD3 +T 450 6500 5 8 0 1 0 2 1 +pintype=tri +} +P 100 6100 400 6100 1 0 0 +{ +T 300 6150 5 8 1 1 0 6 1 +pinnumber=12 +T 300 6050 5 8 0 1 0 8 1 +pinseq=12 +T 450 6100 9 8 1 1 0 0 1 +pinlabel=AD4 +T 450 6100 5 8 0 1 0 2 1 +pintype=tri +} +P 100 5700 400 5700 1 0 0 +{ +T 300 5750 5 8 1 1 0 6 1 +pinnumber=13 +T 300 5650 5 8 0 1 0 8 1 +pinseq=13 +T 450 5700 9 8 1 1 0 0 1 +pinlabel=AD5 +T 450 5700 5 8 0 1 0 2 1 +pintype=tri +} +P 100 5300 400 5300 1 0 0 +{ +T 300 5350 5 8 1 1 0 6 1 +pinnumber=14 +T 300 5250 5 8 0 1 0 8 1 +pinseq=14 +T 450 5300 9 8 1 1 0 0 1 +pinlabel=AD6 +T 450 5300 5 8 0 1 0 2 1 +pintype=tri +} +P 100 4900 400 4900 1 0 0 +{ +T 300 4950 5 8 1 1 0 6 1 +pinnumber=18 +T 300 4850 5 8 0 1 0 8 1 +pinseq=18 +T 450 4900 9 8 1 1 0 0 1 +pinlabel=AD7 +T 450 4900 5 8 0 1 0 2 1 +pintype=tri +} +P 100 4100 400 4100 1 0 0 +{ +T 300 4150 5 8 1 1 0 6 1 +pinnumber=28 +T 300 4050 5 8 0 1 0 8 1 +pinseq=28 +T 450 4100 9 8 1 1 0 0 1 +pinlabel=ADDR0 +T 450 4100 5 8 0 1 0 2 1 +pintype=in +} +P 100 3700 400 3700 1 0 0 +{ +T 300 3750 5 8 1 1 0 6 1 +pinnumber=27 +T 300 3650 5 8 0 1 0 8 1 +pinseq=27 +T 450 3700 9 8 1 1 0 0 1 +pinlabel=ADDR1 +T 450 3700 5 8 0 1 0 2 1 +pintype=in +} +P 100 3300 400 3300 1 0 0 +{ +T 300 3350 5 8 1 1 0 6 1 +pinnumber=26 +T 300 3250 5 8 0 1 0 8 1 +pinseq=26 +T 450 3300 9 8 1 1 0 0 1 +pinlabel=ADDR2 +T 450 3300 5 8 0 1 0 2 1 +pintype=in +} +P 100 2900 400 2900 1 0 0 +{ +T 300 2950 5 8 1 1 0 6 1 +pinnumber=25 +T 300 2850 5 8 0 1 0 8 1 +pinseq=25 +T 450 2900 9 8 1 1 0 0 1 +pinlabel=ADDR3 +T 450 2900 5 8 0 1 0 2 1 +pintype=in +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=24 +T 300 2450 5 8 0 1 0 8 1 +pinseq=24 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=ADDR4 +T 450 2500 5 8 0 1 0 2 1 +pintype=in +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=23 +T 300 2050 5 8 0 1 0 8 1 +pinseq=23 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=ADDR5 +T 450 2100 5 8 0 1 0 2 1 +pintype=in +} +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=22 +T 300 1650 5 8 0 1 0 8 1 +pinseq=22 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=ADDR6 +T 450 1700 5 8 0 1 0 2 1 +pintype=in +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=21 +T 300 1250 5 8 0 1 0 8 1 +pinseq=21 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=ADDR7 +T 450 1300 5 8 0 1 0 2 1 +pintype=in +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=20 +T 300 450 5 8 0 1 0 8 1 +pinseq=20 +T 450 500 9 8 1 1 0 0 1 +pinlabel=MUXED +T 450 500 5 8 0 1 0 2 1 +pintype=in +} +P 3500 10100 3200 10100 1 0 0 +{ +T 3300 10150 5 8 1 1 0 0 1 +pinnumber=7 +T 3300 10050 5 8 0 1 0 2 1 +pinseq=7 +T 3150 10100 9 8 1 1 0 6 1 +pinlabel=READY +T 3150 10100 5 8 0 1 0 8 1 +pintype=oc +} +L 2610 10224 3150 10224 3 0 0 0 -1 -1 +P 3500 9700 3200 9700 1 0 0 +{ +T 3300 9750 5 8 1 1 0 0 1 +pinnumber=6 +T 3300 9650 5 8 0 1 0 2 1 +pinseq=6 +T 3150 9700 9 8 1 1 0 6 1 +pinlabel=IRQ +T 3150 9700 5 8 0 1 0 8 1 +pintype=oc +} +L 2882 9824 3150 9824 3 0 0 0 -1 -1 +P 3500 8900 3200 8900 1 0 0 +{ +T 3300 8950 5 8 1 1 0 0 1 +pinnumber=34 +T 3300 8850 5 8 0 1 0 2 1 +pinseq=34 +T 3150 8900 9 8 1 1 0 6 1 +pinlabel=RST +T 3150 8900 5 8 0 1 0 8 1 +pintype=in +} +L 2854 9024 3150 9024 3 0 0 0 -1 -1 +B 400 100 2800 10400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1800 5700 9 10 1 0 0 0 1 +MCI +T 1700 5400 9 10 1 0 0 0 1 +1 OF 5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,80 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=RS8973 +device=RS8973 +refdes=U? +footprint=QFP100 +description=RS8973 bitpump, MCI (1 of 5) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +19 in line l MO_TEL_ +5 in line l ALE +2 in line l _CS_ +3 in line l _RD_/_DS_ +4 in line l _WR_/R/_W_ +1001 pas line l DUMMY1 +8 tri line l AD0 +9 tri line l AD1 +10 tri line l AD2 +11 tri line l AD3 +12 tri line l AD4 +13 tri line l AD5 +14 tri line l AD6 +18 tri line l AD7 +1002 pas line l DUMMY2 +28 in line l ADDR0 +27 in line l ADDR1 +26 in line l ADDR2 +25 in line l ADDR3 +24 in line l ADDR4 +23 in line l ADDR5 +22 in line l ADDR6 +21 in line l ADDR7 +1003 pas line l DUMMY3 +20 in line l MUXED + +7 oc line r _READY_ +6 oc line r _IRQ_ +1004 pas line r DUMMY4 +34 in line r _RST_
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,169 @@ +v 20040111 1 +T 3200 4100 8 10 1 1 0 6 1 +refdes=U? +T 400 4050 9 10 1 0 0 0 1 +RS8973 +T 400 4250 5 10 0 0 0 0 1 +device=RS8973 +T 400 4450 5 10 0 0 0 0 1 +footprint=QFP100_R +T 400 4650 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 4850 5 10 0 0 0 0 1 +documentation= +T 400 5050 5 10 0 0 0 0 1 +description=RS8973 bitpump, data path (2 of 5) +T 400 5250 5 10 0 0 0 0 1 +numslots=0 +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=86 +T 300 3550 5 8 0 1 0 8 1 +pinseq=86 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=TQ0 +T 450 3600 5 8 0 1 0 2 1 +pintype=in +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=85 +T 300 3150 5 8 0 1 0 8 1 +pinseq=85 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=TQ1/TDAT +T 450 3200 5 8 0 1 0 2 1 +pintype=in +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=89 +T 300 2350 5 8 0 1 0 8 1 +pinseq=89 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=RQ0/BCLK +T 450 2400 5 8 0 1 0 2 1 +pintype=out +} +P 100 2000 400 2000 1 0 0 +{ +T 300 2050 5 8 1 1 0 6 1 +pinnumber=88 +T 300 1950 5 8 0 1 0 8 1 +pinseq=88 +T 450 2000 9 8 1 1 0 0 1 +pinlabel=RQ1/RDAT +T 450 2000 5 8 0 1 0 2 1 +pintype=out +} +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=87 +T 300 1550 5 8 0 1 0 8 1 +pinseq=87 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=QCLK +T 450 1600 5 8 0 1 0 2 1 +pintype=out +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=91 +T 300 750 5 8 0 1 0 8 1 +pinseq=91 +T 525 800 9 8 1 1 0 0 1 +pinlabel=TBCLK +T 525 800 5 8 0 1 0 2 1 +pintype=clk +} +L 500 800 400 875 3 0 0 0 -1 -1 +L 500 800 400 725 3 0 0 0 -1 -1 +P 100 400 400 400 1 0 0 +{ +T 300 450 5 8 1 1 0 6 1 +pinnumber=90 +T 300 350 5 8 0 1 0 8 1 +pinseq=90 +T 525 400 9 8 1 1 0 0 1 +pinlabel=RBCLK +T 525 400 5 8 0 1 0 2 1 +pintype=clk +} +L 500 400 400 475 3 0 0 0 -1 -1 +L 500 400 400 325 3 0 0 0 -1 -1 +P 3500 3600 3200 3600 1 0 0 +{ +T 3300 3650 5 8 1 1 0 0 1 +pinnumber=71 +T 3300 3550 5 8 0 1 0 2 1 +pinseq=71 +T 3150 3600 9 8 1 1 0 6 1 +pinlabel=TXP +T 3150 3600 5 8 0 1 0 8 1 +pintype=out +} +P 3500 3200 3200 3200 1 0 0 +{ +T 3300 3250 5 8 1 1 0 0 1 +pinnumber=74 +T 3300 3150 5 8 0 1 0 2 1 +pinseq=74 +T 3150 3200 9 8 1 1 0 6 1 +pinlabel=TXN +T 3150 3200 5 8 0 1 0 8 1 +pintype=out +} +P 3500 2400 3200 2400 1 0 0 +{ +T 3300 2450 5 8 1 1 0 0 1 +pinnumber=77 +T 3300 2350 5 8 0 1 0 2 1 +pinseq=77 +T 3150 2400 9 8 1 1 0 6 1 +pinlabel=RXP +T 3150 2400 5 8 0 1 0 8 1 +pintype=in +} +P 3500 2000 3200 2000 1 0 0 +{ +T 3300 2050 5 8 1 1 0 0 1 +pinnumber=78 +T 3300 1950 5 8 0 1 0 2 1 +pinseq=78 +T 3150 2000 9 8 1 1 0 6 1 +pinlabel=RXN +T 3150 2000 5 8 0 1 0 8 1 +pintype=in +} +P 3500 1200 3200 1200 1 0 0 +{ +T 3300 1250 5 8 1 1 0 0 1 +pinnumber=79 +T 3300 1150 5 8 0 1 0 2 1 +pinseq=79 +T 3150 1200 9 8 1 1 0 6 1 +pinlabel=RXBP +T 3150 1200 5 8 0 1 0 8 1 +pintype=in +} +P 3500 800 3200 800 1 0 0 +{ +T 3300 850 5 8 1 1 0 0 1 +pinnumber=80 +T 3300 750 5 8 0 1 0 2 1 +pinseq=80 +T 3150 800 9 8 1 1 0 6 1 +pinlabel=RXBN +T 3150 800 5 8 0 1 0 8 1 +pintype=in +} +B 400 0 2800 4000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1200 3700 9 10 1 0 0 0 1 +DATA PATH +T 1500 3400 9 10 1 0 0 0 1 +2 OF 5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-2.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,68 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=RS8973 +device=RS8973 +refdes=U? +footprint=QFP100 +description=RS8973 bitpump, data path (2 of 5) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +86 in line l TQ0 +85 in line l TQ1/TDAT +1001 pas line l DUMMY1 +89 out line l RQ0/BCLK +88 out line l RQ1/RDAT +87 out line l QCLK +1002 pas line l DUMMY2 +91 clk clk l TBCLK +90 clk clk l RBCLK + +71 out line r TXP +74 out line r TXN +1003 pas line r DUMMY3 +77 in line r RXP +78 in line r RXN +1004 pas line r DUMMY4 +79 in line r RXBP +80 in line r RXBN
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-3.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,156 @@ +v 20040111 1 +T 3100 3700 8 10 1 1 0 6 1 +refdes=U? +T 300 3650 9 10 1 0 0 0 1 +RS8973 +T 300 3850 5 10 0 0 0 0 1 +device=RS8973 +T 300 4050 5 10 0 0 0 0 1 +footprint=QFP100_R +T 300 4250 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 4450 5 10 0 0 0 0 1 +documentation= +T 300 4650 5 10 0 0 0 0 1 +description=RS8973 bitpump, clock and analog (3 of 5) +T 300 4850 5 10 0 0 0 0 1 +numslots=0 +P 3400 3200 3100 3200 1 0 0 +{ +T 3200 3250 5 8 1 1 0 0 1 +pinnumber=56 +T 3200 3150 5 8 0 1 0 2 1 +pinseq=56 +T 3050 3200 9 8 1 1 0 6 1 +pinlabel=RBIAS +T 3050 3200 5 8 0 1 0 8 1 +pintype=pas +} +P 3400 2800 3100 2800 1 0 0 +{ +T 3200 2850 5 8 1 1 0 0 1 +pinnumber=58 +T 3200 2750 5 8 0 1 0 2 1 +pinseq=58 +T 3050 2800 9 8 1 1 0 6 1 +pinlabel=VCOMO +T 3050 2800 5 8 0 1 0 8 1 +pintype=pas +} +P 3400 2400 3100 2400 1 0 0 +{ +T 3200 2450 5 8 1 1 0 0 1 +pinnumber=57 +T 3200 2350 5 8 0 1 0 2 1 +pinseq=57 +T 3050 2400 9 8 1 1 0 6 1 +pinlabel=VCOMI +T 3050 2400 5 8 0 1 0 8 1 +pintype=pas +} +P 3400 2000 3100 2000 1 0 0 +{ +T 3200 2050 5 8 1 1 0 0 1 +pinnumber=59 +T 3200 1950 5 8 0 1 0 2 1 +pinseq=59 +T 3050 2000 9 8 1 1 0 6 1 +pinlabel=VCCAP +T 3050 2000 5 8 0 1 0 8 1 +pintype=pas +} +P 3400 1600 3100 1600 1 0 0 +{ +T 3200 1650 5 8 1 1 0 0 1 +pinnumber=51 +T 3200 1550 5 8 0 1 0 2 1 +pinseq=51 +T 3050 1600 9 8 1 1 0 6 1 +pinlabel=VRXP +T 3050 1600 5 8 0 1 0 8 1 +pintype=pas +} +P 3400 1200 3100 1200 1 0 0 +{ +T 3200 1250 5 8 1 1 0 0 1 +pinnumber=52 +T 3200 1150 5 8 0 1 0 2 1 +pinseq=52 +T 3050 1200 9 8 1 1 0 6 1 +pinlabel=VRXN +T 3050 1200 5 8 0 1 0 8 1 +pintype=pas +} +P 3400 800 3100 800 1 0 0 +{ +T 3200 850 5 8 1 1 0 0 1 +pinnumber=60 +T 3200 750 5 8 0 1 0 2 1 +pinseq=60 +T 3050 800 9 8 1 1 0 6 1 +pinlabel=VTXP +T 3050 800 5 8 0 1 0 8 1 +pintype=pas +} +P 3400 400 3100 400 1 0 0 +{ +T 3200 450 5 8 1 1 0 0 1 +pinnumber=61 +T 3200 350 5 8 0 1 0 2 1 +pinseq=61 +T 3050 400 9 8 1 1 0 6 1 +pinlabel=VTXN +T 3050 400 5 8 0 1 0 8 1 +pintype=pas +} +P 0 3200 300 3200 1 0 0 +{ +T 200 3250 5 8 1 1 0 6 1 +pinnumber=40 +T 200 3150 5 8 0 1 0 8 1 +pinseq=40 +T 425 3200 9 8 1 1 0 0 1 +pinlabel=XTALI/MCLK +T 425 3200 5 8 0 1 0 2 1 +pintype=clk +} +L 400 3200 300 3275 3 0 0 0 -1 -1 +L 400 3200 300 3125 3 0 0 0 -1 -1 +P 0 2800 300 2800 1 0 0 +{ +T 200 2850 5 8 1 1 0 6 1 +pinnumber=39 +T 200 2750 5 8 0 1 0 8 1 +pinseq=39 +T 350 2800 9 8 1 1 0 0 1 +pinlabel=XTALO +T 350 2800 5 8 0 1 0 2 1 +pintype=out +} +P 0 2400 300 2400 1 0 0 +{ +T 200 2450 5 8 1 1 0 6 1 +pinnumber=35 +T 200 2350 5 8 0 1 0 8 1 +pinseq=35 +T 350 2400 9 8 1 1 0 0 1 +pinlabel=HCLK +T 350 2400 5 8 0 1 0 2 1 +pintype=out +} +P 0 2000 300 2000 1 0 0 +{ +T 200 2050 5 8 1 1 0 6 1 +pinnumber=36 +T 200 1950 5 8 0 1 0 8 1 +pinseq=36 +T 350 2000 9 8 1 1 0 0 1 +pinlabel=XOUT +T 350 2000 5 8 0 1 0 2 1 +pintype=out +} +B 300 0 2800 3600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 500 1300 9 10 1 0 0 0 1 +CLOCK & ANALOG +T 1100 1000 9 10 1 0 0 0 1 +3 OF 5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-3.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,63 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=RS8973 +device=RS8973 +refdes=U? +footprint=QFP100 +description=RS8973 bitpump, clock and analog (3 of 5) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +56 pas line r RBIAS +58 pas line r VCOMO +57 pas line r VCOMI +59 pas line r VCCAP +51 pas line r VRXP +52 pas line r VRXN +60 pas line r VTXP +61 pas line r VTXN + +40 clk clk l XTALI/MCLK +39 out line l XTALO +35 out line l HCLK +36 out line l XOUT
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-4.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,213 @@ +v 20040111 1 +T 2400 4500 8 10 1 1 0 6 1 +refdes=U? +T 400 4450 9 10 1 0 0 0 1 +RS8973 +T 400 4650 5 10 0 0 0 0 1 +device=RS8973 +T 400 4850 5 10 0 0 0 0 1 +footprint=QFP100_R +T 400 5050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 5250 5 10 0 0 0 0 1 +documentation= +T 400 5450 5 10 0 0 0 0 1 +description=RS8973 bitpump, test (4 of 5) +T 400 5650 5 10 0 0 0 0 1 +numslots=0 +P 100 4000 400 4000 1 0 0 +{ +T 300 4050 5 8 1 1 0 6 1 +pinnumber=95 +T 300 3950 5 8 0 1 0 8 1 +pinseq=95 +T 450 4000 9 8 1 1 0 0 1 +pinlabel=TDI +T 450 4000 5 8 0 1 0 2 1 +pintype=in +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=96 +T 300 3550 5 8 0 1 0 8 1 +pinseq=96 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=TMS +T 450 3600 5 8 0 1 0 2 1 +pintype=in +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=94 +T 300 3150 5 8 0 1 0 8 1 +pinseq=94 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=TDO +T 450 3200 5 8 0 1 0 2 1 +pintype=out +} +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=97 +T 300 2750 5 8 0 1 0 8 1 +pinseq=97 +T 525 2800 9 8 1 1 0 0 1 +pinlabel=TCK +T 525 2800 5 8 0 1 0 2 1 +pintype=clk +} +L 500 2800 400 2875 3 0 0 0 -1 -1 +L 500 2800 400 2725 3 0 0 0 -1 -1 +P 2700 4000 2400 4000 1 0 0 +{ +T 2500 4050 5 8 1 1 0 0 1 +pinnumber=29 +T 2500 3950 5 8 0 1 0 2 1 +pinseq=29 +T 2350 4000 9 8 1 1 0 6 1 +pinlabel=SMON +T 2350 4000 5 8 0 1 0 8 1 +pintype=out +} +P 2700 3600 2400 3600 1 0 0 +{ +T 2500 3650 5 8 1 1 0 0 1 +pinnumber=92 +T 2500 3550 5 8 0 1 0 2 1 +pinseq=92 +T 2350 3600 9 8 1 1 0 6 1 +pinlabel=DTEST5 +T 2350 3600 5 8 0 1 0 8 1 +pintype=in +} +L 1766 3724 2350 3724 3 0 0 0 -1 -1 +P 2700 3200 2400 3200 1 0 0 +{ +T 2500 3250 5 8 1 1 0 0 1 +pinnumber=93 +T 2500 3150 5 8 0 1 0 2 1 +pinseq=93 +T 2350 3200 9 8 1 1 0 6 1 +pinlabel=DTEST6 +T 2350 3200 5 8 0 1 0 8 1 +pintype=in +} +L 1750 3324 2350 3324 3 0 0 0 -1 -1 +P 2700 2800 2400 2800 1 0 0 +{ +T 2500 2850 5 8 1 1 0 0 1 +pinnumber=43 +T 2500 2750 5 8 0 1 0 2 1 +pinseq=43 +T 2350 2800 9 8 1 1 0 6 1 +pinlabel=DTEST1 +T 2350 2800 5 8 0 1 0 8 1 +pintype=in +} +P 2700 2400 2400 2400 1 0 0 +{ +T 2500 2450 5 8 1 1 0 0 1 +pinnumber=44 +T 2500 2350 5 8 0 1 0 2 1 +pinseq=44 +T 2350 2400 9 8 1 1 0 6 1 +pinlabel=DTEST2 +T 2350 2400 5 8 0 1 0 8 1 +pintype=in +} +P 2700 2000 2400 2000 1 0 0 +{ +T 2500 2050 5 8 1 1 0 0 1 +pinnumber=45 +T 2500 1950 5 8 0 1 0 2 1 +pinseq=45 +T 2350 2000 9 8 1 1 0 6 1 +pinlabel=DTEST3 +T 2350 2000 5 8 0 1 0 8 1 +pintype=in +} +P 2700 1600 2400 1600 1 0 0 +{ +T 2500 1650 5 8 1 1 0 0 1 +pinnumber=48 +T 2500 1550 5 8 0 1 0 2 1 +pinseq=48 +T 2350 1600 9 8 1 1 0 6 1 +pinlabel=DTEST4 +T 2350 1600 5 8 0 1 0 8 1 +pintype=in +} +P 2700 1200 2400 1200 1 0 0 +{ +T 2500 1250 5 8 1 1 0 0 1 +pinnumber=65 +T 2500 1150 5 8 0 1 0 2 1 +pinseq=65 +T 2350 1200 9 8 1 1 0 6 1 +pinlabel=ATEST1 +T 2350 1200 5 8 0 1 0 8 1 +pintype=in +} +P 2700 800 2400 800 1 0 0 +{ +T 2500 850 5 8 1 1 0 0 1 +pinnumber=66 +T 2500 750 5 8 0 1 0 2 1 +pinseq=66 +T 2350 800 9 8 1 1 0 6 1 +pinlabel=ATEST2 +T 2350 800 5 8 0 1 0 8 1 +pintype=in +} +P 800 100 800 400 1 0 0 +{ +T 850 200 5 8 1 1 0 0 1 +pinnumber=67 +T 850 200 5 8 0 1 0 2 1 +pinseq=67 +T 800 450 9 8 1 1 0 3 1 +pinlabel=NC +T 800 600 5 8 0 1 0 3 1 +pintype=pas +} +P 1200 100 1200 400 1 0 0 +{ +T 1250 200 5 8 1 1 0 0 1 +pinnumber=68 +T 1250 200 5 8 0 1 0 2 1 +pinseq=68 +T 1200 450 9 8 1 1 0 3 1 +pinlabel=NC +T 1200 600 5 8 0 1 0 3 1 +pintype=pas +} +P 1600 100 1600 400 1 0 0 +{ +T 1650 200 5 8 1 1 0 0 1 +pinnumber=69 +T 1650 200 5 8 0 1 0 2 1 +pinseq=69 +T 1600 450 9 8 1 1 0 3 1 +pinlabel=NC +T 1600 600 5 8 0 1 0 3 1 +pintype=pas +} +P 2000 100 2000 400 1 0 0 +{ +T 2050 200 5 8 1 1 0 0 1 +pinnumber=70 +T 2050 200 5 8 0 1 0 2 1 +pinseq=70 +T 2000 450 9 8 1 1 0 3 1 +pinlabel=NC +T 2000 600 5 8 0 1 0 3 1 +pintype=pas +} +B 400 400 2000 4000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 700 1700 9 10 1 0 0 0 1 +TEST +T 600 1400 9 10 1 0 0 0 1 +4 OF 5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-4.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,69 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=2000 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=RS8973 +device=RS8973 +refdes=U? +footprint=QFP100 +description=RS8973 bitpump, test (4 of 5) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +95 in line l TDI +96 in line l TMS +94 out line l TDO +97 clk clk l TCK + +29 out line r SMON +92 in line r _DTEST5_ +93 in line r _DTEST6_ +43 in line r DTEST1 +44 in line r DTEST2 +45 in line r DTEST3 +48 in line r DTEST4 +65 in line r ATEST1 +66 in line r ATEST2 + +67 pas line b NC +68 pas line b NC +69 pas line b NC +70 pas line b NC
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-5.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,383 @@ +v 20040111 1 +T 9700 1700 8 10 1 1 0 6 1 +refdes=U? +T 0 1650 9 10 1 0 0 0 1 +RS8973 +T 0 1850 5 10 0 0 0 0 1 +device=RS8973 +T 0 2050 5 10 0 0 0 0 1 +footprint=QFP100_R +T 0 2250 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 0 2450 5 10 0 0 0 0 1 +documentation= +T 0 2650 5 10 0 0 0 0 1 +description=RS8973 bitpump, power (5 of 5) +T 0 2850 5 10 0 0 0 0 1 +numslots=0 +P 1000 1900 1000 1600 1 0 0 +{ +T 1050 1700 5 8 1 1 0 0 1 +pinnumber=1 +T 1050 1700 5 8 0 1 0 2 1 +pinseq=1 +T 1000 1550 9 8 1 1 0 5 1 +pinlabel=VDD1 +T 1000 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 1400 1900 1400 1600 1 0 0 +{ +T 1450 1700 5 8 1 1 0 0 1 +pinnumber=30 +T 1450 1700 5 8 0 1 0 2 1 +pinseq=30 +T 1400 1550 9 8 1 1 0 5 1 +pinlabel=VDD1 +T 1400 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 1800 1900 1800 1600 1 0 0 +{ +T 1850 1700 5 8 1 1 0 0 1 +pinnumber=38 +T 1850 1700 5 8 0 1 0 2 1 +pinseq=38 +T 1800 1550 9 8 1 1 0 5 1 +pinlabel=VDD1 +T 1800 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2200 1900 2200 1600 1 0 0 +{ +T 2250 1700 5 8 1 1 0 0 1 +pinnumber=83 +T 2250 1700 5 8 0 1 0 2 1 +pinseq=83 +T 2200 1550 9 8 1 1 0 5 1 +pinlabel=VDD1 +T 2200 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2900 1900 2900 1600 1 0 0 +{ +T 2950 1700 5 8 1 1 0 0 1 +pinnumber=17 +T 2950 1700 5 8 0 1 0 2 1 +pinseq=17 +T 2900 1550 9 8 1 1 0 5 1 +pinlabel=VDD2 +T 2900 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 3400 1900 3400 1600 1 0 0 +{ +T 3450 1700 5 8 1 1 0 0 1 +pinnumber=33 +T 3450 1700 5 8 0 1 0 2 1 +pinseq=33 +T 3400 1550 9 8 1 1 0 5 1 +pinlabel=VDD2 +T 3400 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 3900 1900 3900 1600 1 0 0 +{ +T 3950 1700 5 8 1 1 0 0 1 +pinnumber=98 +T 3950 1700 5 8 0 1 0 2 1 +pinseq=98 +T 3900 1550 9 8 1 1 0 5 1 +pinlabel=VDD2 +T 3900 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 4600 1900 4600 1600 1 0 0 +{ +T 4650 1700 5 8 1 1 0 0 1 +pinnumber=41 +T 4650 1700 5 8 0 1 0 2 1 +pinseq=41 +T 4600 1550 9 8 1 1 0 5 1 +pinlabel=VPLL +T 4600 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 5100 1900 5100 1600 1 0 0 +{ +T 5150 1700 5 8 1 1 0 0 1 +pinnumber=46 +T 5150 1700 5 8 0 1 0 2 1 +pinseq=46 +T 5100 1550 9 8 1 1 0 5 1 +pinlabel=VPLL +T 5100 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 4600 100 4600 400 1 0 0 +{ +T 4650 200 5 8 1 1 0 0 1 +pinnumber=42 +T 4650 200 5 8 0 1 0 2 1 +pinseq=42 +T 4600 450 9 8 1 1 0 3 1 +pinlabel=PGND +T 4600 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 5100 100 5100 400 1 0 0 +{ +T 5150 200 5 8 1 1 0 0 1 +pinnumber=47 +T 5150 200 5 8 0 1 0 2 1 +pinseq=47 +T 5100 450 9 8 1 1 0 3 1 +pinlabel=PGND +T 5100 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 400 100 400 400 1 0 0 +{ +T 450 200 5 8 1 1 0 0 1 +pinnumber=15 +T 450 200 5 8 0 1 0 2 1 +pinseq=15 +T 400 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 400 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 900 100 900 400 1 0 0 +{ +T 950 200 5 8 1 1 0 0 1 +pinnumber=16 +T 950 200 5 8 0 1 0 2 1 +pinseq=16 +T 900 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 900 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 1400 100 1400 400 1 0 0 +{ +T 1450 200 5 8 1 1 0 0 1 +pinnumber=31 +T 1450 200 5 8 0 1 0 2 1 +pinseq=31 +T 1400 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 1400 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 1900 100 1900 400 1 0 0 +{ +T 1950 200 5 8 1 1 0 0 1 +pinnumber=32 +T 1950 200 5 8 0 1 0 2 1 +pinseq=32 +T 1900 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 1900 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 2400 100 2400 400 1 0 0 +{ +T 2450 200 5 8 1 1 0 0 1 +pinnumber=37 +T 2450 200 5 8 0 1 0 2 1 +pinseq=37 +T 2400 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 2400 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 2900 100 2900 400 1 0 0 +{ +T 2950 200 5 8 1 1 0 0 1 +pinnumber=84 +T 2950 200 5 8 0 1 0 2 1 +pinseq=84 +T 2900 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 2900 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 3400 100 3400 400 1 0 0 +{ +T 3450 200 5 8 1 1 0 0 1 +pinnumber=99 +T 3450 200 5 8 0 1 0 2 1 +pinseq=99 +T 3400 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 3400 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 3900 100 3900 400 1 0 0 +{ +T 3950 200 5 8 1 1 0 0 1 +pinnumber=100 +T 3950 200 5 8 0 1 0 2 1 +pinseq=100 +T 3900 450 9 8 1 1 0 3 1 +pinlabel=DGND +T 3900 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 6300 1900 6300 1600 1 0 0 +{ +T 6350 1700 5 8 1 1 0 0 1 +pinnumber=54 +T 6350 1700 5 8 0 1 0 2 1 +pinseq=54 +T 6300 1550 9 8 1 1 0 5 1 +pinlabel=VAA +T 6300 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 6800 1900 6800 1600 1 0 0 +{ +T 6850 1700 5 8 1 1 0 0 1 +pinnumber=55 +T 6850 1700 5 8 0 1 0 2 1 +pinseq=55 +T 6800 1550 9 8 1 1 0 5 1 +pinlabel=VAA +T 6800 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 7300 1900 7300 1600 1 0 0 +{ +T 7350 1700 5 8 1 1 0 0 1 +pinnumber=63 +T 7350 1700 5 8 0 1 0 2 1 +pinseq=63 +T 7300 1550 9 8 1 1 0 5 1 +pinlabel=VAA +T 7300 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 7800 1900 7800 1600 1 0 0 +{ +T 7850 1700 5 8 1 1 0 0 1 +pinnumber=64 +T 7850 1700 5 8 0 1 0 2 1 +pinseq=64 +T 7800 1550 9 8 1 1 0 5 1 +pinlabel=VAA +T 7800 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 8300 1900 8300 1600 1 0 0 +{ +T 8350 1700 5 8 1 1 0 0 1 +pinnumber=72 +T 8350 1700 5 8 0 1 0 2 1 +pinseq=72 +T 8300 1550 9 8 1 1 0 5 1 +pinlabel=VAA +T 8300 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 8800 1900 8800 1600 1 0 0 +{ +T 8850 1700 5 8 1 1 0 0 1 +pinnumber=81 +T 8850 1700 5 8 0 1 0 2 1 +pinseq=81 +T 8800 1550 9 8 1 1 0 5 1 +pinlabel=VAA +T 8800 1400 5 8 0 1 0 5 1 +pintype=pwr +} +P 5800 100 5800 400 1 0 0 +{ +T 5850 200 5 8 1 1 0 0 1 +pinnumber=49 +T 5850 200 5 8 0 1 0 2 1 +pinseq=49 +T 5800 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 5800 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 6300 100 6300 400 1 0 0 +{ +T 6350 200 5 8 1 1 0 0 1 +pinnumber=50 +T 6350 200 5 8 0 1 0 2 1 +pinseq=50 +T 6300 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 6300 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 6800 100 6800 400 1 0 0 +{ +T 6850 200 5 8 1 1 0 0 1 +pinnumber=53 +T 6850 200 5 8 0 1 0 2 1 +pinseq=53 +T 6800 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 6800 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 7300 100 7300 400 1 0 0 +{ +T 7350 200 5 8 1 1 0 0 1 +pinnumber=62 +T 7350 200 5 8 0 1 0 2 1 +pinseq=62 +T 7300 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 7300 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 7800 100 7800 400 1 0 0 +{ +T 7850 200 5 8 1 1 0 0 1 +pinnumber=73 +T 7850 200 5 8 0 1 0 2 1 +pinseq=73 +T 7800 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 7800 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 8300 100 8300 400 1 0 0 +{ +T 8350 200 5 8 1 1 0 0 1 +pinnumber=75 +T 8350 200 5 8 0 1 0 2 1 +pinseq=75 +T 8300 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 8300 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 8800 100 8800 400 1 0 0 +{ +T 8850 200 5 8 1 1 0 0 1 +pinnumber=76 +T 8850 200 5 8 0 1 0 2 1 +pinseq=76 +T 8800 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 8800 600 5 8 0 1 0 3 1 +pintype=pwr +} +P 9300 100 9300 400 1 0 0 +{ +T 9350 200 5 8 1 1 0 0 1 +pinnumber=82 +T 9350 200 5 8 0 1 0 2 1 +pinseq=82 +T 9300 450 9 8 1 1 0 3 1 +pinlabel=AGND +T 9300 600 5 8 0 1 0 3 1 +pintype=pwr +} +B 0 400 9700 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 4000 900 9 10 1 0 0 0 1 +POWER (5 OF 5)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973-5.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,83 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=9000 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=RS8973 +device=RS8973 +refdes=U? +footprint=QFP100 +description=RS8973 bitpump, power (5 of 5) +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pwr line t VDD1 +30 pwr line t VDD1 +38 pwr line t VDD1 +83 pwr line t VDD1 +17 pwr line t VDD2 +33 pwr line t VDD2 +98 pwr line t VDD2 +41 pwr line t VPLL +46 pwr line t VPLL +42 pwr line b PGND +47 pwr line b PGND +15 pwr line b DGND +16 pwr line b DGND +31 pwr line b DGND +32 pwr line b DGND +37 pwr line b DGND +84 pwr line b DGND +99 pwr line b DGND +100 pwr line b DGND +54 pwr line t VAA +55 pwr line t VAA +63 pwr line t VAA +64 pwr line t VAA +72 pwr line t VAA +81 pwr line t VAA +49 pwr line b AGND +50 pwr line b AGND +53 pwr line b AGND +62 pwr line b AGND +73 pwr line b AGND +75 pwr line b AGND +76 pwr line b AGND +82 pwr line b AGND
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973.pins Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,114 @@ +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 line l VDD1 +2 line l CS +3 line l RD/DS +4 line l WR/R/W +5 line l ALE +6 line l IRQ +7 line l READY +8 line l AD0 +9 line l AD1 +10 line l AD2 +11 line l AD3 +12 line l AD4 +13 line l AD5 +14 line l AD6 +15 line l DGND +16 line l DGND +17 line l VDD2 +18 line l AD7 +19 line l MOTEL +20 line l MUXED +21 line l ADDR7 +22 line l ADDR6 +23 line l ADDR5 +24 line l ADDR4 +25 line l ADDR3 +26 line l ADDR2 +27 line l ADDR1 +28 line l ADDR0 +29 line l SMON +30 line l VDD1 +31 line l DGND +32 line l DGND +33 line l VDD2 +34 line l RST +35 line l HCLK +36 line l XOUT +37 line l DGND +38 line l VDD1 +39 line l XTALO +40 line l XTALI/MCLK +41 line l VPLL +42 line l PGND +43 line l DTEST1 +44 line l DTEST2 +45 line l DTEST3 +46 line l VPLL +47 line l PGND +48 line l DTEST4 +49 line l AGND +50 line l AGND +51 line l VRXP +52 line l VRXN +53 line l AGND +54 line l VAA +55 line l VAA +56 line l RBIAS +57 line l VCOMI +58 line l VCOMO +59 line l VCCAP +60 line l VTXP +61 line l VTXN +62 line l AGND +63 line l VAA +64 line l VAA +65 line l ATEST1 +66 line l ATEST2 +67 line l NC +68 line l NC +69 line l NC +70 line l NC +71 line l TXP +72 line l VAA +73 line l AGND +74 line l TXN +75 line l AGND +76 line l AGND +77 line l RXP +78 line l RXN +79 line l RXBP +80 line l RXBN +81 line l VAA +82 line l AGND +83 line l VDD1 +84 line l DGND +85 line l TQ1/TDAT +86 line l TQ0 +87 line l QCLK +88 line l RQ1/RDAT +89 line l RQ0/BCLK +90 line l RBCLK +91 line l TBCLK +92 line l DTEST5 +93 line l DTEST6 +94 line l TDO +95 line l TDI +96 line l TMS +97 line l TCK +98 line l VDD2 +99 line l DGND +100 line l DGND
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/RS8973.pins.sorted Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,121 @@ +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +19 in line l MOTEL +5 in line l ALE +2 in line l CS +3 in line l RD/DS +4 in line l WR/R/W +8 tri line l AD0 +9 tri line l AD1 +10 tri line l AD2 +11 tri line l AD3 +12 tri line l AD4 +13 tri line l AD5 +14 tri line l AD6 +18 tri line l AD7 +28 in line l ADDR0 +27 in line l ADDR1 +26 in line l ADDR2 +25 in line l ADDR3 +24 in line l ADDR4 +23 in line l ADDR5 +22 in line l ADDR6 +21 in line l ADDR7 +20 in line l MUXED +7 oc line l READY +6 oc line l IRQ +34 in line l RST + +89 out line l RQ0/BCLK +88 out line l RQ1/RDAT +86 in line l TQ0 +85 in line l TQ1/TDAT +87 out line l QCLK +91 clk clk l TBCLK +90 clk clk l RBCLK + +71 out line l TXP +74 out line l TXN +77 in line l RXP +78 in line l RXN +79 in line l RXBP +80 in line l RXBN + +56 pas line l RBIAS +58 pas line l VCOMO +57 pas line l VCOMI +59 pas line l VCCAP +51 pas line l VRXP +52 pas line l VRXN +60 pas line l VTXP +61 pas line l VTXN + +40 clk clk l XTALI/MCLK +39 out line l XTALO +35 out line l HCLK +36 out line l XOUT + +95 in line l TDI +96 in line l TMS +94 out line l TDO +97 clk clk l TCK +29 out line l SMON +43 in line l DTEST1 +44 in line l DTEST2 +45 in line l DTEST3 +48 in line l DTEST4 +92 in line l DTEST5 +93 in line l DTEST6 +65 in line l ATEST1 +66 in line l ATEST2 + +1 pwr line l VDD1 +30 pwr line l VDD1 +38 pwr line l VDD1 +83 pwr line l VDD1 +17 pwr line l VDD2 +33 pwr line l VDD2 +98 pwr line l VDD2 +41 pwr line l VPLL +46 pwr line l VPLL +42 pwr line l PGND +47 pwr line l PGND +15 pwr line l DGND +16 pwr line l DGND +31 pwr line l DGND +32 pwr line l DGND +37 pwr line l DGND +84 pwr line l DGND +99 pwr line l DGND +100 pwr line l DGND +54 pwr line l VAA +55 pwr line l VAA +63 pwr line l VAA +64 pwr line l VAA +72 pwr line l VAA +81 pwr line l VAA +49 pwr line l AGND +50 pwr line l AGND +53 pwr line l AGND +62 pwr line l AGND +73 pwr line l AGND +75 pwr line l AGND +76 pwr line l AGND +82 pwr line l AGND + +67 pas line l NC +68 pas line l NC +69 pas line l NC +70 pas line l NC
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/SN75LBC784-com.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,102 @@ +v 20040111 1 +T 3100 2400 8 10 1 1 0 6 1 +refdes=U? +T 300 2350 9 10 1 1 0 0 1 +device=SN75LBC784 +T 300 2750 5 10 0 0 0 0 1 +footprint=SO28 +T 300 2950 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 3350 5 10 0 0 0 0 1 +description=Quad EIA-423-B transceiver +T 300 3550 5 10 0 0 0 0 1 +numslots=0 +P 0 1900 300 1900 1 0 0 +{ +T 200 1950 5 8 1 1 0 6 1 +pinnumber=3 +T 200 1850 5 8 0 1 0 8 1 +pinseq=3 +T 350 1900 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 1900 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 1500 300 1500 1 0 0 +{ +T 200 1550 5 8 1 1 0 6 1 +pinnumber=6 +T 200 1450 5 8 0 1 0 8 1 +pinseq=6 +T 350 1500 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 1500 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 1100 300 1100 1 0 0 +{ +T 200 1150 5 8 1 1 0 6 1 +pinnumber=25 +T 200 1050 5 8 0 1 0 8 1 +pinseq=25 +T 350 1100 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 1100 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 700 300 700 1 0 0 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=28 +T 200 650 5 8 0 1 0 8 1 +pinseq=28 +T 350 700 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 700 5 8 0 1 0 2 1 +pintype=pwr +} +P 3400 700 3100 700 1 0 0 +{ +T 3200 750 5 8 1 1 0 0 1 +pinnumber=22 +T 3200 650 5 8 0 1 0 2 1 +pinseq=22 +T 3050 700 9 8 1 1 0 6 1 +pinlabel=Rws +T 3050 700 5 8 0 1 0 8 1 +pintype=pas +} +P 1700 2600 1700 2300 1 0 0 +{ +T 1750 2400 5 8 1 1 0 0 1 +pinnumber=21 +T 1750 2400 5 8 0 1 0 2 1 +pinseq=21 +T 1700 2250 9 8 1 1 0 5 1 +pinlabel=VDD +T 1700 2100 5 8 0 1 0 5 1 +pintype=pwr +} +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=8 +T 1050 100 5 8 0 1 0 2 1 +pinseq=8 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1700 0 1700 300 1 0 0 +{ +T 1750 100 5 8 1 1 0 0 1 +pinnumber=7 +T 1750 100 5 8 0 1 0 2 1 +pinseq=7 +T 1700 350 9 8 1 1 0 3 1 +pinlabel=VSS +T 1700 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 300 300 2800 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/SN75LBC784-com.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,61 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=SN75LBC784 +device=SN75LBC784 +refdes=U? +footprint=SO28 +description=Quad EIA-423-B transceiver +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +3 pwr line l BIAS +6 pwr line l BIAS +25 pwr line l BIAS +28 pwr line l BIAS + +22 pas line r Rws + +21 pwr line t VDD +8 pwr line b GND +7 pwr line b VSS
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/SN75LBC784-drvr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,48 @@ +v 20040111 1 +L 300 800 800 500 3 0 0 0 -1 -1 +T 600 1100 5 10 0 0 0 0 1 +slot=1 +T 600 1300 5 10 0 0 0 0 1 +numslots=4 +T 600 1500 5 10 0 0 0 0 1 +slotdef=1:23,20 +T 600 1700 5 10 0 0 0 0 1 +slotdef=2:26,18 +T 600 1900 5 10 0 0 0 0 1 +slotdef=3:1,12 +T 600 2100 5 10 0 0 0 0 1 +slotdef=4:4,10 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +V 850 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=23 +T 200 450 5 8 0 1 0 8 1 +pinseq=1 +T 350 500 9 8 0 1 0 0 1 +pinlabel=A +T 350 500 5 8 0 1 0 2 1 +pintype=in +} +P 1100 500 900 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=20 +T 900 450 5 8 0 1 0 2 1 +pinseq=2 +T 750 500 9 8 0 1 0 6 1 +pinlabel=Y +T 750 500 5 8 0 1 0 8 1 +pintype=out +} +T 100 0 9 8 1 1 0 0 1 +device=SN75LBC784 +T 300 900 8 10 1 1 0 0 1 +refdes=U? +T 600 3500 5 10 0 0 0 0 1 +footprint=SO28 +T 600 3700 5 10 0 0 0 0 1 +description=Quad EIA-423-B transceiver
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/SN75LBC784-rcvr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,60 @@ +v 20040111 1 +L 200 1000 200 200 3 0 0 0 -1 -1 +L 200 1000 800 600 3 0 0 0 -1 -1 +T 100 0 9 8 1 1 0 0 1 +device=SN75LBC784 +L 800 600 200 200 3 0 0 0 -1 -1 +L 300 450 300 350 3 0 0 0 -1 -1 +L 250 400 350 400 3 0 0 0 -1 -1 +L 250 800 350 800 3 0 0 0 -1 -1 +P 0 400 200 400 1 0 0 +{ +T 0 450 5 10 1 1 0 0 1 +pinnumber=15 +T 0 450 5 10 0 0 0 0 1 +pinseq=2 +T 0 450 5 10 0 0 0 0 1 +pintype=in +T 0 450 5 10 0 0 0 0 1 +pinlabel=C +} +P 0 800 200 800 1 0 0 +{ +T 0 850 5 10 1 1 0 0 1 +pinnumber=19 +T 0 850 5 10 0 0 0 0 1 +pinseq=1 +T 0 850 5 10 0 0 0 0 1 +pintype=in +T 0 850 5 10 0 0 0 0 1 +pinlabel=B +} +P 800 600 1000 600 1 0 1 +{ +T 800 650 5 10 1 1 0 0 1 +pinnumber=27 +T 800 650 5 10 0 0 0 0 1 +pinseq=3 +T 800 650 5 10 0 0 0 0 1 +pintype=out +T 800 650 5 10 0 0 0 0 1 +pinlabel=Y +} +T 200 1100 8 10 1 1 0 0 1 +refdes=U? +T 200 1300 5 10 0 0 0 0 1 +slot=1 +T 200 1700 5 10 0 0 0 0 1 +numslots=4 +T 200 1500 5 10 0 0 0 0 1 +footprint=SO28 +T 200 1900 5 10 0 0 0 0 1 +slotdef=3:11,13,2 +T 200 2100 5 10 0 0 0 0 1 +slotdef=4:9,14,5 +T 200 2300 5 10 0 0 0 0 1 +slotdef=1:19,15,27 +T 200 2500 5 10 0 0 0 0 1 +slotdef=2:17,16,24 +T 200 2700 5 10 0 0 0 0 1 +description=Quad EIA-423-B transceiver
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/agnd-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +v 20031231 1 +P 100 100 100 300 1 0 1 +{ +T 158 161 5 4 0 1 0 0 1 +pinnumber=1 +T 158 161 5 4 0 0 0 0 1 +pinseq=1 +T 158 161 5 4 0 1 0 0 1 +pinlabel=1 +T 158 161 5 4 0 1 0 0 1 +pintype=pwr +} +L 0 100 200 100 3 0 0 0 -1 -1 +L 0 100 100 0 3 0 0 0 -1 -1 +L 200 100 100 0 3 0 0 0 -1 -1 +T 300 50 8 10 0 0 0 0 1 +net=GND:1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/biled-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,49 @@ +v 20031231 1 +L 600 0 600 400 3 0 0 0 -1 -1 +L 600 0 300 200 3 0 0 0 -1 -1 +T 950 650 5 10 0 0 0 0 1 +device=LED +L 300 200 600 400 3 0 0 0 -1 -1 +L 300 0 300 400 3 0 0 0 -1 -1 +P 0 200 200 200 1 0 0 +{ +T 200 150 5 8 1 1 180 0 1 +pinnumber=1 +T 800 650 9 8 0 1 180 0 1 +pinlabel=CATHODE +T 900 850 5 8 0 0 180 0 1 +pintype=pas +T 600 950 5 8 0 0 180 0 1 +pinseq=1 +} +P 900 200 700 200 1 0 0 +{ +T 800 150 5 8 1 1 180 0 1 +pinnumber=2 +T 1400 150 9 8 0 1 180 0 1 +pinlabel=ANODE +T 1000 350 5 8 0 0 180 8 1 +pintype=pas +T 1000 250 5 8 0 0 180 8 1 +pinseq=2 +} +L 200 200 300 200 3 0 0 0 -1 -1 +L 600 200 700 200 3 0 0 0 -1 -1 +T 450 550 8 10 1 1 0 0 1 +refdes=D? +L 500 400 400 500 3 0 0 0 -1 -1 +L 400 400 300 500 3 0 0 0 -1 -1 +L 300 500 325 450 3 0 0 0 -1 -1 +L 300 500 350 475 3 0 0 0 -1 -1 +L 400 500 425 450 3 0 0 0 -1 -1 +L 400 500 450 475 3 0 0 0 -1 -1 +T 950 550 5 10 0 0 0 0 1 +description=Bicolor LED +T 950 450 5 10 0 0 0 0 1 +numslots=2 +T 950 350 5 10 0 0 0 0 1 +slot=1 +T 950 250 5 10 0 0 0 0 1 +slotdef=1:1,2 +T 950 150 5 10 0 0 0 0 1 +slotdef=2:4,3
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/diodepair-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,50 @@ +v 20040111 1 +L 0 1000 400 1000 3 0 0 0 -1 -1 +L 0 1000 200 1300 3 0 0 0 -1 -1 +T 100 400 5 10 0 0 0 0 1 +device=DIODE +L 200 1300 400 1000 3 0 0 0 -1 -1 +L 0 1300 400 1300 3 0 0 0 -1 -1 +P 200 0 200 200 1 0 0 +{ +T 100 150 5 8 1 1 180 0 1 +pinnumber=1 +T 150 100 5 8 0 0 90 0 1 +pinseq=1 +T 150 100 5 8 0 1 90 0 1 +pinlabel=1 +T 150 100 5 8 0 1 90 0 1 +pintype=pas +} +P 200 1600 200 1400 1 0 0 +{ +T 100 1450 5 8 1 1 180 0 1 +pinnumber=2 +T 150 1400 5 8 0 0 90 0 1 +pinseq=2 +T 150 1400 5 8 0 1 90 0 1 +pinlabel=2 +T 150 1400 5 8 0 1 90 0 1 +pintype=pas +} +L 200 1400 200 1300 3 0 0 0 -1 -1 +T 500 1200 8 10 1 1 0 0 1 +refdes=D? +L 0 300 400 300 3 0 0 0 -1 -1 +L 0 300 200 600 3 0 0 0 -1 -1 +L 200 600 400 300 3 0 0 0 -1 -1 +L 0 600 400 600 3 0 0 0 -1 -1 +L 200 300 200 200 3 0 0 0 -1 -1 +L 200 1000 200 600 3 0 0 0 -1 -1 +P 600 800 400 800 1 0 0 +{ +T 500 850 5 8 1 1 0 0 1 +pinnumber=3 +T 500 850 5 8 0 1 0 0 1 +pinseq=3 +T 500 850 5 8 0 1 0 0 1 +pinlabel=3 +T 500 850 5 8 0 1 0 0 1 +pintype=pas +} +L 200 800 400 800 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/dpr-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,39 @@ +v 20040111 1 +L 400 1100 400 950 3 0 0 2 50 50 +L 400 200 400 350 3 0 0 2 50 50 +B 300 350 200 600 3 0 0 2 50 50 0 -1 -1 -1 -1 -1 +B 300 1100 200 200 1 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 +B 300 0 200 200 1 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 +T 600 1650 5 10 0 0 0 0 1 +device=RESISTOR +T 200 900 8 10 1 1 90 0 1 +refdes=R? +B 300 1450 200 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 400 1300 400 1450 3 0 0 0 -1 -1 +L 400 2200 400 2050 3 0 0 0 -1 -1 +B 300 2200 200 200 1 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 +P 500 1200 800 1200 1 0 1 +{ +T 550 1250 5 10 1 1 0 0 1 +pinnumber=2 +T 550 1250 5 10 0 1 0 0 1 +pinseq=2 +} +P 0 100 300 100 1 0 0 +{ +T 150 150 5 10 1 1 0 0 1 +pinnumber=3 +T 150 150 5 10 0 1 0 0 1 +pinseq=3 +} +P 0 2300 300 2300 1 0 0 +{ +T 150 2350 5 10 1 1 0 0 1 +pinnumber=1 +T 150 2350 5 10 0 1 0 0 1 +pinseq=1 +} +T 350 1700 9 10 1 0 0 0 1 +A +T 350 600 9 10 1 0 0 0 1 +B
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/dpr-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,39 @@ +v 20040111 1 +L 400 1100 400 950 3 0 0 0 -1 -1 +L 400 200 400 350 3 0 0 0 -1 -1 +B 300 350 200 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 300 1100 200 200 1 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 +B 300 0 200 200 1 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 +T 600 1650 5 10 0 0 0 0 1 +device=RESISTOR +T 200 900 8 10 1 1 90 0 1 +refdes=R? +B 300 1450 200 600 3 0 0 2 50 50 0 -1 -1 -1 -1 -1 +L 400 1300 400 1450 3 0 0 2 50 50 +L 400 2200 400 2050 3 0 0 2 50 50 +B 300 2200 200 200 1 0 0 0 -1 -1 1 -1 -1 -1 -1 -1 +P 500 1200 800 1200 1 0 1 +{ +T 550 1250 5 10 1 1 0 0 1 +pinnumber=2 +T 550 1250 5 10 0 1 0 0 1 +pinseq=2 +} +P 0 100 300 100 1 0 0 +{ +T 150 150 5 10 1 1 0 0 1 +pinnumber=3 +T 150 150 5 10 0 1 0 0 1 +pinseq=3 +} +P 0 2300 300 2300 1 0 0 +{ +T 150 2350 5 10 1 1 0 0 1 +pinnumber=1 +T 150 2350 5 10 0 1 0 0 1 +pinseq=1 +} +T 350 1700 9 10 1 0 0 0 1 +A +T 350 600 9 10 1 0 0 0 1 +B
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/egnd-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,28 @@ +v 20060123 1 +P 100 100 100 300 1 0 1 +{ +T 158 161 5 4 0 1 0 0 1 +pinnumber=1 +T 158 161 5 4 0 0 0 0 1 +pinseq=1 +T 158 161 5 4 0 1 0 0 1 +pinlabel=1 +T 158 161 5 4 0 1 0 0 1 +pintype=pwr +} +L 0 100 200 100 3 0 0 0 -1 -1 +T 300 50 8 10 0 0 0 0 1 +net=Chassis_GND:1 +L 0 100 25 25 3 0 0 0 -1 -1 +L 50 100 75 25 3 0 0 0 -1 -1 +L 100 100 125 25 3 0 0 0 -1 -1 +L 150 100 175 25 3 0 0 0 -1 -1 +L 200 100 225 25 3 0 0 0 -1 -1 +T 0 0 9 10 0 0 0 0 1 +author=DJ Delorie, modified by Michael Sokolov +T 0 0 9 10 0 0 0 0 1 +copyright=2006 DJ Delorie +T 0 0 9 10 0 0 0 0 1 +dist-license=GPL +T 0 0 9 10 0 0 0 0 1 +use-license=unlimited
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/fixpinseq.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,40 @@ +#include <sys/param.h> +#include <stdio.h> + +main(argc, argv) + char **argv; +{ + char *infile, outfile[MAXPATHLEN]; + FILE *inf, *of; + char line[1024]; + int pinnum; + + if (argc != 2) { + fprintf(stderr, "usage: %s symfile\n", argv[0]); + exit(1); + } + infile = argv[1]; + inf = fopen(infile, "r"); + if (!inf) { + perror(infile); + exit(1); + } + strcpy(outfile, infile); + strcat(outfile, ".fix"); + of = fopen(outfile, "w"); + if (!of) { + perror(outfile); + exit(1); + } + + while (fgets(line, sizeof line, inf)) { + if (!strncmp(line, "pinnumber=", 10)) + pinnum = atoi(line + 10); + else if (!strncmp(line, "pinseq=", 7)) + sprintf(line, "pinseq=%d\n", pinnum); + fputs(line, of); + } + fclose(inf); + fclose(of); + exit(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/jumper-3pin.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,44 @@ +v 20040111 1 +P 100 1000 100 750 1 0 0 +{ +T 150 850 5 8 1 1 0 0 1 +pinnumber=3 +T 150 850 5 8 0 0 0 0 1 +pinseq=3 +T 150 850 5 8 0 1 0 0 1 +pinlabel=3 +T 150 850 5 8 0 1 0 0 1 +pintype=pas +} +P 400 500 150 500 1 0 0 +{ +T 250 550 5 8 1 1 0 0 1 +pinnumber=2 +T 250 550 5 8 0 0 0 0 1 +pinseq=2 +T 250 550 5 8 0 1 0 0 1 +pinlabel=2 +T 250 550 5 8 0 1 0 0 1 +pintype=pas +} +P 100 0 100 250 1 0 0 +{ +T 150 50 5 8 1 1 0 0 1 +pinnumber=1 +T 150 50 5 8 0 0 0 0 1 +pinseq=1 +T 150 50 5 8 0 1 0 0 1 +pinlabel=1 +T 150 50 5 8 0 1 0 0 1 +pintype=pas +} +V 100 700 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 100 500 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 100 300 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 0 200 200 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 250 300 5 8 0 0 0 0 1 +device=JUMPER +T 250 500 5 8 0 0 0 0 1 +footprint=JUMPER3 +T 250 700 8 10 1 1 0 0 1 +refdes=J?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/mkpqfp.awk Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,3 @@ +(NF == 3) { + printf "s/^pinnumber=%s$/pinnumber=%s/\n", $3, $2; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/mkpqfp.sed Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,132 @@ +s/^pinnumber=G1$/pinnumber=1/ +s/^pinnumber=G3$/pinnumber=2/ +s/^pinnumber=G2$/pinnumber=3/ +s/^pinnumber=F2$/pinnumber=5/ +s/^pinnumber=F3$/pinnumber=6/ +s/^pinnumber=E1$/pinnumber=7/ +s/^pinnumber=D1$/pinnumber=8/ +s/^pinnumber=E2$/pinnumber=9/ +s/^pinnumber=E3$/pinnumber=10/ +s/^pinnumber=C1$/pinnumber=11/ +s/^pinnumber=B1$/pinnumber=12/ +s/^pinnumber=D3$/pinnumber=14/ +s/^pinnumber=C2$/pinnumber=15/ +s/^pinnumber=A1$/pinnumber=16/ +s/^pinnumber=D4$/pinnumber=17/ +s/^pinnumber=D5$/pinnumber=19/ +s/^pinnumber=C3$/pinnumber=20/ +s/^pinnumber=B2$/pinnumber=21/ +s/^pinnumber=B3$/pinnumber=22/ +s/^pinnumber=B4$/pinnumber=24/ +s/^pinnumber=A2$/pinnumber=25/ +s/^pinnumber=A3$/pinnumber=26/ +s/^pinnumber=C5$/pinnumber=27/ +s/^pinnumber=B11$/pinnumber=48/ +s/^pinnumber=C10$/pinnumber=47/ +s/^pinnumber=B10$/pinnumber=46/ +s/^pinnumber=A12$/pinnumber=45/ +s/^pinnumber=C9$/pinnumber=43/ +s/^pinnumber=B9$/pinnumber=42/ +s/^pinnumber=A10$/pinnumber=41/ +s/^pinnumber=A9$/pinnumber=40/ +s/^pinnumber=B8$/pinnumber=38/ +s/^pinnumber=A8$/pinnumber=37/ +s/^pinnumber=B7$/pinnumber=36/ +s/^pinnumber=C7$/pinnumber=35/ +s/^pinnumber=A6$/pinnumber=33/ +s/^pinnumber=B6$/pinnumber=32/ +s/^pinnumber=C6$/pinnumber=31/ +s/^pinnumber=A5$/pinnumber=30/ +s/^pinnumber=M6$/pinnumber=104/ +s/^pinnumber=N6$/pinnumber=103/ +s/^pinnumber=N5$/pinnumber=106/ +s/^pinnumber=L6$/pinnumber=105/ +s/^pinnumber=K9$/pinnumber=85/ +s/^pinnumber=K2$/pinnumber=123/ +s/^pinnumber=K3$/pinnumber=122/ +s/^pinnumber=L11$/pinnumber=86/ +s/^pinnumber=M10$/pinnumber=90/ +s/^pinnumber=M12$/pinnumber=87/ +s/^pinnumber=M11$/pinnumber=88/ +s/^pinnumber=N11$/pinnumber=92/ +s/^pinnumber=N12$/pinnumber=91/ +s/^pinnumber=M9$/pinnumber=94/ +s/^pinnumber=K13$/pinnumber=74/ +s/^pinnumber=J13$/pinnumber=73/ +s/^pinnumber=L8$/pinnumber=97/ +s/^pinnumber=N9$/pinnumber=96/ +s/^pinnumber=N10$/pinnumber=95/ +s/^pinnumber=H1$/pinnumber=132/ +s/^pinnumber=H3$/pinnumber=130/ +s/^pinnumber=J1$/pinnumber=129/ +s/^pinnumber=L9$/pinnumber=93/ +s/^pinnumber=K1$/pinnumber=128/ +s/^pinnumber=J2$/pinnumber=127/ +s/^pinnumber=L1$/pinnumber=125/ +s/^pinnumber=M1$/pinnumber=124/ +s/^pinnumber=A13$/pinnumber=52/ +s/^pinnumber=K11$/pinnumber=80/ +s/^pinnumber=N13$/pinnumber=82/ +s/^pinnumber=L12$/pinnumber=81/ +s/^pinnumber=C11$/pinnumber=50/ +s/^pinnumber=D10$/pinnumber=51/ +s/^pinnumber=K12$/pinnumber=79/ +s/^pinnumber=J11$/pinnumber=76/ +s/^pinnumber=D9$/pinnumber=53/ +s/^pinnumber=E10$/pinnumber=54/ +s/^pinnumber=C12$/pinnumber=55/ +s/^pinnumber=D11$/pinnumber=56/ +s/^pinnumber=B13$/pinnumber=58/ +s/^pinnumber=C13$/pinnumber=59/ +s/^pinnumber=E11$/pinnumber=60/ +s/^pinnumber=E12$/pinnumber=61/ +s/^pinnumber=E13$/pinnumber=63/ +s/^pinnumber=F11$/pinnumber=64/ +s/^pinnumber=F12$/pinnumber=65/ +s/^pinnumber=F13$/pinnumber=66/ +s/^pinnumber=B12$/pinnumber=49/ +s/^pinnumber=M13$/pinnumber=78/ +s/^pinnumber=L13$/pinnumber=77/ +s/^pinnumber=G11$/pinnumber=68/ +s/^pinnumber=G12$/pinnumber=69/ +s/^pinnumber=H13$/pinnumber=70/ +s/^pinnumber=H12$/pinnumber=71/ +s/^pinnumber=M5$/pinnumber=108/ +s/^pinnumber=L5$/pinnumber=109/ +s/^pinnumber=N3$/pinnumber=110/ +s/^pinnumber=N2$/pinnumber=111/ +s/^pinnumber=L4$/pinnumber=113/ +s/^pinnumber=M3$/pinnumber=114/ +s/^pinnumber=M2$/pinnumber=115/ +s/^pinnumber=K5$/pinnumber=117/ +s/^pinnumber=J4$/pinnumber=118/ +s/^pinnumber=K4$/pinnumber=119/ +s/^pinnumber=N1$/pinnumber=120/ +s/^pinnumber=L2$/pinnumber=121/ +s/^pinnumber=N7$/pinnumber=100/ +s/^pinnumber=L7$/pinnumber=101/ +s/^pinnumber=M8$/pinnumber=98/ +s/^pinnumber=H11$/pinnumber=72/ +s/^pinnumber=N4$/pinnumber=4/ +s/^pinnumber=M7$/pinnumber=13/ +s/^pinnumber=L3$/pinnumber=23/ +s/^pinnumber=J3$/pinnumber=29/ +s/^pinnumber=J10$/pinnumber=34/ +s/^pinnumber=G13$/pinnumber=44/ +s/^pinnumber=F1$/pinnumber=57/ +s/^pinnumber=D2$/pinnumber=67/ +s/^pinnumber=D12$/pinnumber=84/ +s/^pinnumber=C4$/pinnumber=102/ +s/^pinnumber=A4$/pinnumber=107/ +s/^pinnumber=A7$/pinnumber=116/ +s/^pinnumber=A11$/pinnumber=126/ +s/^pinnumber=N8$/pinnumber=18/ +s/^pinnumber=M4$/pinnumber=28/ +s/^pinnumber=K10$/pinnumber=39/ +s/^pinnumber=H2$/pinnumber=62/ +s/^pinnumber=E4$/pinnumber=83/ +s/^pinnumber=D13$/pinnumber=99/ +s/^pinnumber=C8$/pinnumber=112/ +s/^pinnumber=B5$/pinnumber=131/ +s/^pinnumber=L10$/pinnumber=89/ +s/^pinnumber=J12$/pinnumber=75/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/modjack-6.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,90 @@ +v 20040111 1 +B 0 0 600 1400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 900 1200 600 1200 1 0 0 +{ +T 700 1250 5 8 1 1 0 0 1 +pinnumber=1 +T 700 1250 5 8 0 1 0 0 1 +pinseq=1 +T 700 1250 5 8 0 1 0 6 1 +pinlabel=I0 +T 700 1250 5 8 0 1 0 8 1 +pintype=in +} +V 400 1200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 1200 600 1200 3 0 0 0 -1 -1 +P 900 1000 600 1000 1 0 0 +{ +T 700 1050 5 8 1 1 0 0 1 +pinnumber=2 +T 700 1050 5 8 0 1 0 0 1 +pinseq=2 +T 700 1050 5 8 0 1 0 6 1 +pinlabel=I1 +T 700 1050 5 8 0 1 0 8 1 +pintype=in +} +V 200 1000 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 1000 600 1000 3 0 0 0 -1 -1 +P 900 800 600 800 1 0 0 +{ +T 700 850 5 8 1 1 0 0 1 +pinnumber=3 +T 700 850 5 8 0 1 0 0 1 +pinseq=3 +T 700 850 5 8 0 1 0 6 1 +pinlabel=I2 +T 700 850 5 8 0 1 0 8 1 +pintype=in +} +V 400 800 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 800 600 800 3 0 0 0 -1 -1 +P 900 600 600 600 1 0 0 +{ +T 700 650 5 8 1 1 0 0 1 +pinnumber=4 +T 700 650 5 8 0 1 0 0 1 +pinseq=4 +T 700 650 5 8 0 1 0 6 1 +pinlabel=I3 +T 700 650 5 8 0 1 0 8 1 +pintype=in +} +V 200 600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 600 600 600 3 0 0 0 -1 -1 +P 900 400 600 400 1 0 0 +{ +T 700 450 5 8 1 1 0 0 1 +pinnumber=5 +T 700 450 5 8 0 1 0 0 1 +pinseq=5 +T 700 450 5 8 0 1 0 6 1 +pinlabel=I4 +T 700 450 5 8 0 1 0 8 1 +pintype=in +} +V 400 400 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 400 600 400 3 0 0 0 -1 -1 +P 900 200 600 200 1 0 0 +{ +T 700 250 5 8 1 1 0 0 1 +pinnumber=6 +T 700 250 5 8 0 1 0 0 1 +pinseq=6 +T 700 250 5 8 0 1 0 6 1 +pinlabel=I5 +T 700 250 5 8 0 1 0 8 1 +pintype=in +} +V 200 200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 200 600 200 3 0 0 0 -1 -1 +T 0 1700 9 10 1 1 0 0 1 +device=MODJACK +T 0 2300 5 10 0 0 0 0 1 +footprint=RJ12 +T 0 2100 5 10 0 0 0 0 1 +description=6-position modular jack +T 0 1500 8 10 1 1 0 0 1 +refdes=J? +T 0 2700 5 10 0 0 0 0 1 +numslots=0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/modjack-8.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,116 @@ +v 20031231 1 +B 0 0 600 1800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 900 1600 600 1600 1 0 0 +{ +T 700 1650 5 8 1 1 0 0 1 +pinnumber=1 +T 700 1650 5 8 0 1 0 0 1 +pinseq=1 +T 700 1650 5 8 0 1 0 6 1 +pinlabel=I0 +T 700 1650 5 8 0 1 0 8 1 +pintype=in +} +V 400 1600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 1600 600 1600 3 0 0 0 -1 -1 +P 900 1400 600 1400 1 0 0 +{ +T 700 1450 5 8 1 1 0 0 1 +pinnumber=2 +T 700 1450 5 8 0 1 0 0 1 +pinseq=2 +T 700 1450 5 8 0 1 0 6 1 +pinlabel=I1 +T 700 1450 5 8 0 1 0 8 1 +pintype=in +} +V 200 1400 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 1400 600 1400 3 0 0 0 -1 -1 +P 900 1200 600 1200 1 0 0 +{ +T 700 1250 5 8 1 1 0 0 1 +pinnumber=3 +T 700 1250 5 8 0 1 0 0 1 +pinseq=3 +T 700 1250 5 8 0 1 0 6 1 +pinlabel=I2 +T 700 1250 5 8 0 1 0 8 1 +pintype=in +} +V 400 1200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 1200 600 1200 3 0 0 0 -1 -1 +P 900 1000 600 1000 1 0 0 +{ +T 700 1050 5 8 1 1 0 0 1 +pinnumber=4 +T 700 1050 5 8 0 1 0 0 1 +pinseq=4 +T 700 1050 5 8 0 1 0 6 1 +pinlabel=I3 +T 700 1050 5 8 0 1 0 8 1 +pintype=in +} +V 200 1000 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 1000 600 1000 3 0 0 0 -1 -1 +P 900 800 600 800 1 0 0 +{ +T 700 850 5 8 1 1 0 0 1 +pinnumber=5 +T 700 850 5 8 0 1 0 0 1 +pinseq=5 +T 700 850 5 8 0 1 0 6 1 +pinlabel=I4 +T 700 850 5 8 0 1 0 8 1 +pintype=in +} +V 400 800 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 800 600 800 3 0 0 0 -1 -1 +P 900 600 600 600 1 0 0 +{ +T 700 650 5 8 1 1 0 0 1 +pinnumber=6 +T 700 650 5 8 0 1 0 0 1 +pinseq=6 +T 700 650 5 8 0 1 0 6 1 +pinlabel=I5 +T 700 650 5 8 0 1 0 8 1 +pintype=in +} +V 200 600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 600 600 600 3 0 0 0 -1 -1 +P 900 400 600 400 1 0 0 +{ +T 700 450 5 8 1 1 0 0 1 +pinnumber=7 +T 700 450 5 8 0 1 0 0 1 +pinseq=7 +T 700 450 5 8 0 1 0 6 1 +pinlabel=I6 +T 700 450 5 8 0 1 0 8 1 +pintype=in +} +V 400 400 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 400 600 400 3 0 0 0 -1 -1 +P 900 200 600 200 1 0 0 +{ +T 700 250 5 8 1 1 0 0 1 +pinnumber=8 +T 700 250 5 8 0 1 0 0 1 +pinseq=8 +T 700 250 5 8 0 1 0 6 1 +pinlabel=I7 +T 700 250 5 8 0 1 0 8 1 +pintype=in +} +V 200 200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 200 600 200 3 0 0 0 -1 -1 +T 0 2100 9 10 1 1 0 0 1 +device=MODJACK +T 0 2700 5 10 0 0 0 0 1 +footprint=RJ45 +T 0 2500 5 10 0 0 0 0 1 +description=8-position modular jack +T 0 1900 8 10 1 1 0 0 1 +refdes=J? +T 0 3100 5 10 0 0 0 0 1 +numslots=0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/nc-x.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,14 @@ +v 20040111 1 +P 0 100 300 100 1 0 0 +{ +T 100 0 5 10 0 1 0 0 1 +pinseq=1 +T 100 200 5 10 0 1 0 0 1 +pinnumber=1 +} +L 250 50 350 150 3 0 0 0 -1 -1 +L 250 150 350 50 3 0 0 0 -1 -1 +T 0 800 8 10 0 0 0 0 1 +device=none +T 0 600 8 10 0 0 0 0 1 +graphical=1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/resistornetwork-13.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,200 @@ +v 20040111 1 +P 0 200 300 200 1 0 0 +{ +T 100 250 5 8 1 1 0 0 1 +pinnumber=1 +T 100 250 5 8 0 0 0 0 1 +pinseq=1 +T 100 250 5 8 0 1 0 0 1 +pinlabel=1 +T 100 250 5 8 0 1 0 0 1 +pintype=pas +} +B 450 100 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1700 350 5 10 0 0 0 0 1 +device=RESISTOR_NETWORK +T 1400 5000 8 10 1 1 0 0 1 +refdes=RN? +L 300 200 450 200 3 0 0 0 -1 -1 +L 1050 200 1200 200 3 0 0 0 -1 -1 +B 450 500 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 600 450 600 3 0 0 0 -1 -1 +L 1050 600 1200 600 3 0 0 0 -1 -1 +P 0 600 300 600 1 0 0 +{ +T 100 650 5 8 1 1 0 0 1 +pinnumber=2 +T 100 650 5 8 0 0 0 0 1 +pinseq=2 +T 100 650 5 8 0 1 0 0 1 +pinlabel=2 +T 100 650 5 8 0 1 0 0 1 +pintype=pas +} +B 450 900 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 1000 450 1000 3 0 0 0 -1 -1 +L 1050 1000 1200 1000 3 0 0 0 -1 -1 +P 0 1000 300 1000 1 0 0 +{ +T 100 1050 5 8 1 1 0 0 1 +pinnumber=3 +T 100 1050 5 8 0 0 0 0 1 +pinseq=3 +T 100 1050 5 8 0 1 0 0 1 +pinlabel=3 +T 100 1050 5 8 0 1 0 0 1 +pintype=pas +} +B 450 1300 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 1400 450 1400 3 0 0 0 -1 -1 +L 1050 1400 1200 1400 3 0 0 0 -1 -1 +P 0 1400 300 1400 1 0 0 +{ +T 100 1450 5 8 1 1 0 0 1 +pinnumber=4 +T 100 1450 5 8 0 0 0 0 1 +pinseq=4 +T 100 1450 5 8 0 1 0 0 1 +pinlabel=4 +T 100 1450 5 8 0 1 0 0 1 +pintype=pas +} +B 450 1700 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 1800 450 1800 3 0 0 0 -1 -1 +L 1050 1800 1200 1800 3 0 0 0 -1 -1 +P 0 1800 300 1800 1 0 0 +{ +T 100 1850 5 8 1 1 0 0 1 +pinnumber=5 +T 100 1850 5 8 0 0 0 0 1 +pinseq=5 +T 100 1850 5 8 0 1 0 0 1 +pinlabel=5 +T 100 1850 5 8 0 1 0 0 1 +pintype=pas +} +B 450 2100 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 2200 450 2200 3 0 0 0 -1 -1 +L 1050 2200 1200 2200 3 0 0 0 -1 -1 +P 0 2200 300 2200 1 0 0 +{ +T 100 2250 5 8 1 1 0 0 1 +pinnumber=6 +T 100 2250 5 8 0 0 0 0 1 +pinseq=6 +T 100 2250 5 8 0 1 0 0 1 +pinlabel=6 +T 100 2250 5 8 0 1 0 0 1 +pintype=pas +} +B 450 2500 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 2600 450 2600 3 0 0 0 -1 -1 +L 1050 2600 1200 2600 3 0 0 0 -1 -1 +P 0 2600 300 2600 1 0 0 +{ +T 100 2650 5 8 1 1 0 0 1 +pinnumber=7 +T 100 2650 5 8 0 0 0 0 1 +pinseq=7 +T 100 2650 5 8 0 1 0 0 1 +pinlabel=7 +T 100 2650 5 8 0 1 0 0 1 +pintype=pas +} +B 450 2900 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 3000 450 3000 3 0 0 0 -1 -1 +L 1050 3000 1200 3000 3 0 0 0 -1 -1 +P 0 3000 300 3000 1 0 0 +{ +T 100 3050 5 8 1 1 0 0 1 +pinnumber=8 +T 100 3050 5 8 0 0 0 0 1 +pinseq=8 +T 100 3050 5 8 0 1 0 0 1 +pinlabel=8 +T 100 3050 5 8 0 1 0 0 1 +pintype=pas +} +B 450 3300 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 3400 450 3400 3 0 0 0 -1 -1 +L 1050 3400 1200 3400 3 0 0 0 -1 -1 +P 0 3400 300 3400 1 0 0 +{ +T 100 3450 5 8 1 1 0 0 1 +pinnumber=9 +T 100 3450 5 8 0 0 0 0 1 +pinseq=9 +T 100 3450 5 8 0 1 0 0 1 +pinlabel=9 +T 100 3450 5 8 0 1 0 0 1 +pintype=pas +} +B 450 3700 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 3800 450 3800 3 0 0 0 -1 -1 +L 1050 3800 1200 3800 3 0 0 0 -1 -1 +P 0 3800 300 3800 1 0 0 +{ +T 100 3850 5 8 1 1 0 0 1 +pinnumber=10 +T 100 3850 5 8 0 0 0 0 1 +pinseq=10 +T 100 3850 5 8 0 1 0 0 1 +pinlabel=10 +T 100 3850 5 8 0 1 0 0 1 +pintype=pas +} +B 450 4100 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 4200 450 4200 3 0 0 0 -1 -1 +L 1050 4200 1200 4200 3 0 0 0 -1 -1 +P 0 4200 300 4200 1 0 0 +{ +T 100 4250 5 8 1 1 0 0 1 +pinnumber=11 +T 100 4250 5 8 0 0 0 0 1 +pinseq=11 +T 100 4250 5 8 0 1 0 0 1 +pinlabel=11 +T 100 4250 5 8 0 1 0 0 1 +pintype=pas +} +B 450 4500 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 4600 450 4600 3 0 0 0 -1 -1 +L 1050 4600 1200 4600 3 0 0 0 -1 -1 +P 0 4600 300 4600 1 0 0 +{ +T 100 4650 5 8 1 1 0 0 1 +pinnumber=12 +T 100 4650 5 8 0 0 0 0 1 +pinseq=12 +T 100 4650 5 8 0 1 0 0 1 +pinlabel=12 +T 100 4650 5 8 0 1 0 0 1 +pintype=pas +} +B 450 4900 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 5000 450 5000 3 0 0 0 -1 -1 +L 1050 5000 1200 5000 3 0 0 0 -1 -1 +P 0 5000 300 5000 1 0 0 +{ +T 100 5050 5 8 1 1 0 0 1 +pinnumber=13 +T 100 5050 5 8 0 0 0 0 1 +pinseq=13 +T 100 5050 5 8 0 1 0 0 1 +pinlabel=13 +T 100 5050 5 8 0 1 0 0 1 +pintype=pas +} +L 1200 200 1200 5200 3 0 0 0 -1 -1 +B 300 0 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1200 5200 1200 5500 1 0 1 +{ +T 1300 5300 5 8 1 1 0 0 1 +pinnumber=14 +T 1300 5300 5 8 0 1 0 0 1 +pinseq=14 +T 1300 5300 5 8 0 1 0 0 1 +pinlabel=14 +T 1300 5300 5 8 0 1 0 0 1 +pintype=pas +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/resistorpack4-slotted.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,40 @@ +v 20031231 1 +P 900 100 750 100 1 0 0 +{ +T 800 150 5 8 0 1 0 0 1 +pinnumber=8 +T 800 150 5 8 0 0 0 0 1 +pinseq=2 +T 800 150 5 8 0 1 0 0 1 +pinlabel=2 +T 800 150 5 8 0 1 0 0 1 +pintype=pas +} +P 0 100 152 100 1 0 0 +{ +T 100 150 5 8 0 1 0 0 1 +pinnumber=1 +T 100 150 5 8 0 0 0 0 1 +pinseq=1 +T 100 150 5 8 0 1 0 0 1 +pinlabel=1 +T 100 150 5 8 0 1 0 0 1 +pintype=pas +} +B 150 0 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 350 5 10 0 0 0 0 1 +device=RESISTOR +T 400 350 5 10 0 0 0 0 1 +numslots=4 +T 400 350 5 10 0 0 0 0 1 +slotdef=1:1,8 +T 400 350 5 10 0 0 0 0 1 +slotdef=2:2,7 +T 400 350 5 10 0 0 0 0 1 +slotdef=3:3,6 +T 400 350 5 10 0 0 0 0 1 +slotdef=4:4,5 +T 400 350 5 10 0 0 0 0 1 +slot=1 +T 200 300 8 10 1 1 0 0 1 +refdes=RP?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/sidactor-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,33 @@ +v 20040111 1 +L 100 600 500 600 3 0 0 0 -1 -1 +T 0 1800 5 10 0 0 0 0 1 +device=SIDACTOR +L 100 900 500 900 3 0 0 0 -1 -1 +P 300 0 300 200 1 0 0 +{ +T 250 100 5 8 0 1 90 0 1 +pinnumber=1 +T 250 100 5 8 0 0 90 0 1 +pinseq=1 +T 250 100 5 8 0 1 90 0 1 +pinlabel=1 +T 250 100 5 8 0 1 90 0 1 +pintype=pas +} +P 300 1200 300 1000 1 0 0 +{ +T 250 1000 5 8 0 1 90 0 1 +pinnumber=2 +T 250 1000 5 8 0 0 90 0 1 +pinseq=2 +T 250 1000 5 8 0 1 90 0 1 +pinlabel=2 +T 250 1000 5 8 0 1 90 0 1 +pintype=pas +} +L 300 1000 300 900 3 0 0 0 -1 -1 +L 300 300 300 200 3 0 0 0 -1 -1 +T 600 600 8 10 1 1 0 0 1 +refdes=S? +L 100 300 500 300 3 0 0 0 -1 -1 +L 500 900 100 300 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/sidactor-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,50 @@ +v 20040111 1 +L 100 600 500 600 3 0 0 0 -1 -1 +T 0 1800 5 10 0 0 0 0 1 +device=SIDACTOR +L 100 900 500 900 3 0 0 0 -1 -1 +P 300 0 300 200 1 0 0 +{ +T 200 150 5 8 1 1 180 0 1 +pinnumber=3 +T 250 100 5 8 0 0 90 0 1 +pinseq=3 +T 250 100 5 8 0 1 90 0 1 +pinlabel=3 +T 250 100 5 8 0 1 90 0 1 +pintype=pas +} +L 300 300 300 200 3 0 0 0 -1 -1 +T 600 1800 8 10 1 1 0 0 1 +refdes=S? +L 100 300 500 300 3 0 0 0 -1 -1 +L 500 900 100 300 3 0 0 0 -1 -1 +L 100 1800 500 1800 3 0 0 0 -1 -1 +L 100 2100 500 2100 3 0 0 0 -1 -1 +P 300 2400 300 2200 1 0 0 +{ +T 200 2250 5 8 1 1 180 0 1 +pinnumber=1 +T 250 2200 5 8 0 0 90 0 1 +pinseq=1 +T 250 2200 5 8 0 1 90 0 1 +pinlabel=1 +T 250 2200 5 8 0 1 90 0 1 +pintype=pas +} +L 300 2200 300 2100 3 0 0 0 -1 -1 +L 100 1500 500 1500 3 0 0 0 -1 -1 +L 500 2100 100 1500 3 0 0 0 -1 -1 +L 300 1500 300 900 3 0 0 0 -1 -1 +L 300 1200 600 1200 3 0 0 0 -1 -1 +P 800 1200 600 1200 1 0 0 +{ +T 700 1250 5 8 1 1 0 0 1 +pinnumber=2 +T 700 1250 5 8 0 1 0 0 1 +pinseq=2 +T 700 1250 5 8 0 1 0 0 1 +pinlabel=2 +T 700 1250 5 8 0 1 0 0 1 +pintype=pas +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/sidactor-3.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,56 @@ +v 20040111 1 +L 100 600 500 600 3 0 0 0 -1 -1 +T 0 1800 5 10 0 0 0 0 1 +device=SIDACTOR +L 100 900 500 900 3 0 0 0 -1 -1 +P 300 0 300 200 1 0 0 +{ +T 200 150 5 8 1 1 180 0 1 +pinnumber=3 +T 250 100 5 8 0 0 90 0 1 +pinseq=3 +T 250 100 5 8 0 1 90 0 1 +pinlabel=3 +T 250 100 5 8 0 1 90 0 1 +pintype=pas +} +L 300 300 300 200 3 0 0 0 -1 -1 +T 1500 2250 8 10 1 1 0 6 1 +refdes=S? +L 100 300 500 300 3 0 0 0 -1 -1 +L 500 900 100 300 3 0 0 0 -1 -1 +L 100 1800 500 1800 3 0 0 0 -1 -1 +L 100 2100 500 2100 3 0 0 0 -1 -1 +P 300 2400 300 2200 1 0 0 +{ +T 200 2350 5 8 1 1 180 0 1 +pinnumber=1 +T 250 2200 5 8 0 0 90 0 1 +pinseq=1 +T 250 2200 5 8 0 1 90 0 1 +pinlabel=1 +T 250 2200 5 8 0 1 90 0 1 +pintype=pas +} +L 300 2200 300 2100 3 0 0 0 -1 -1 +L 100 1500 500 1500 3 0 0 0 -1 -1 +L 500 2100 100 1500 3 0 0 0 -1 -1 +L 300 1500 300 900 3 0 0 0 -1 -1 +P 1700 1200 1500 1200 1 0 0 +{ +T 1600 1250 5 8 1 1 0 0 1 +pinnumber=2 +T 1600 1250 5 8 0 1 0 0 1 +pinseq=2 +T 1600 1250 5 8 0 1 0 0 1 +pinlabel=2 +T 1600 1250 5 8 0 1 0 0 1 +pintype=pas +} +L 1100 1000 1100 1400 3 0 0 0 -1 -1 +L 800 1000 800 1400 3 0 0 0 -1 -1 +L 1400 1200 1500 1200 3 0 0 0 -1 -1 +L 1400 1000 1400 1400 3 0 0 0 -1 -1 +L 800 1400 1400 1000 3 0 0 0 -1 -1 +L 300 1200 800 1200 3 0 0 0 -1 -1 +B 0 200 1500 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/geda-symbols/trgpins.awk Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,3 @@ +(NF == 3) { + printf "%s\t%s\t\tline\tl\t\t%s\n", $3, $2, $1; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/amp.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,367 @@ +# -*- m4 -*- +# +# $Id: amp.inc,v 1.4 2010/12/05 05:39:40 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2003 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# +# Amp (www.amp.com) Specific Footprints + +# ------------------------------------------------------------------- +# the definition of a MICTOR connector +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: pad width (1/1000 mil) +# $6: pad length (1/1000 mil) +# $7: pad pitch (1/1000 mil) +# $8: pad seperation center to center for pads on opposite sides of +# the package (1/1000 mil) +# $9: define to make the pins get numbered starting with the highest pin +# instead of pin 1. Needed for certain brain damaged packages like +# the Mini-Circuits KK81 +# pin 1 will be upper left, pin N/2 will be lower left, +# pin N will be upper right as defined here +define(`COMMON_AMP_MICTOR_MIL', + ` + # number of pads + define(`NPADS', `$4') + + # number of segments of 38 pins each + define(`NSEG', eval(NPADS/38)) + + # pad width in 1/1000 mil + define(`PADWIDTH', `$5') + # pad length in 1/1000 mil + define(`PADLENGTH',`$6') + # pad pitch 1/1000 mil + define(`PITCH',`$7') + # seperation between pads on opposite sides 1/1000 mil + define(`PADSEP',`$8') + + # X coordinates for the right hand column of pads (mils) + define(`X1', eval( (PADSEP/2 + PADLENGTH - PADWIDTH/2)/1000)) + define(`X2', eval( (PADSEP/2 + PADWIDTH/2)/1000)) + + # silk screen width (mils) + define(`SILKW', `10') + define(`SILKSEP', `5') + + + # figure out if we have an even or odd number of pins per side + define(`TMP1', eval(NPADS/4)) + define(`TMP2', eval((4*TMP1 - NPADS) == 0)) + ifelse(TMP2, 1, `define(`EVEN',"yes")', `define(`EVEN',"no")') + + # silk bounding box is -XMAX,-YMAX, XMAX,YMAX (mils) + define(`XMAX', `200') + define(`YMAX', eval(250 + NSEG*250 + 125)) + + define(`REV', `$9') + + ifelse(REV,"reverse", + `define(`CURPIN', NPADS)' + , + `define(`CURPIN', `1')' + ) +Element(0x00 "$1" "$2" "$3" -20 -60 0 100 0x00) +( + define(`SEG', `1') + define(`YOFS', eval((1-NSEG)*25000/2)) + forloop(`i', 1, eval(NPADS / 2), + ` + ifelse(eval(i > SEG*19), 1, + `define(`SEG', incr(SEG)) + define(`YOFS', eval((1-NSEG)*25000/2 + (SEG-1)*25000))',) + ifelse(EVEN,"yes", + `Pad( -X1 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH + YOFS)/1000) + -X2 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)', + `Pad( -X1 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH + YOFS)/1000) + -X2 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)') + + ifelse(REV,"reverse", + `define(`CURPIN', decr(CURPIN)) + define(`CURPIN', decr(CURPIN))', + `define(`CURPIN', incr(CURPIN)) + define(`CURPIN', incr(CURPIN))' + ) + ') + ifelse(REV,"reverse", + `define(`CURPIN', `2')' + , + `define(`CURPIN', `NPADS')' + ) + + define(`SEG', `1') + define(`YOFS', eval((NSEG-1)*25000/2)) + forloop(`i', eval((NPADS / 2) + 1), NPADS, + ` + ifelse(eval(i - NPADS/2 > SEG*19), 1, + `define(`SEG', incr(SEG)) + define(`YOFS', eval((NSEG-1)*25000/2 - (SEG-1)*25000))',) + ifelse(EVEN,"yes", + `Pad( X1 eval( ((NPADS/4)*PITCH + PITCH/2 - (i-NPADS/2)*PITCH + YOFS)/1000) + X2 eval( ((NPADS/4)*PITCH + PITCH/2 - (i-NPADS/2)*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)', + `Pad( X1 eval( ((NPADS/4)*PITCH + PITCH - (i-NPADS/2)*PITCH + YOFS)/1000) + X2 eval( ((NPADS/4)*PITCH + PITCH - (i-NPADS/2)*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)') + ifelse(REV,"reverse", + `define(`CURPIN', incr(CURPIN)) + define(`CURPIN', incr(CURPIN))', + `define(`CURPIN', decr(CURPIN)) + define(`CURPIN', decr(CURPIN))' + ) + ') + + define(`GNDpad', `60') + define(`GNDdrl', `32') +# now add the center row of grounding pins + define(`CURPIN', incr(NPADS)) + define(`YOFS', eval(250-NSEG*250)) + forloop(`j', 1, NSEG, + `forloop(`i', -2, 2, + `Pin(0 eval(i*100 + YOFS) GNDpad GNDdrl "GND" "CURPIN" 0x01) + define(`CURPIN', incr(CURPIN))' + ) + define(`YOFS', eval(YOFS + 500))' + ) +# the latch pins + Pin(0 eval(-YOFS - 55) 80 53 "LATCH" "CURPIN" 0x01) + define(`CURPIN', incr(CURPIN)) + Pin(0 eval(YOFS + 55) 80 53 "LATCH" "CURPIN" 0x01) + define(`CURPIN', incr(CURPIN)) +# and the orientation pin + Pin(0 eval(-YOFS+50) 84 84 "ORIENT" "CURPIN" 0x09) + +# and finally the silk screen + ElementLine(-XMAX -YMAX -XMAX YMAX SILKW) + ElementLine(-XMAX YMAX XMAX YMAX SILKW) + ElementLine( XMAX YMAX XMAX -YMAX SILKW) + ElementLine(-XMAX -YMAX -25 -YMAX SILKW) + ElementLine( XMAX -YMAX 25 -YMAX SILKW) + + # punt on the arc on small parts as it can cover the pads + ifelse(eval((PADSEP-PADLENGTH)/1000 > 50), 1, `ElementArc(0 -YMAX 25 25 0 180 SILKW)', ) + + # Mark at the common centroid + Mark(0 0) +)') + +# dimensions are given in 1/100 mm. +# $5-$8 are pad width, length, pitch, and sep +define(`COMMON_AMP_MICTOR_MM', `COMMON_AMP_MICTOR_MIL(`$1',`$2',`$3',`$4', + eval($5*100000/254),eval($6*100000/254),eval($7*100000/254),eval($8*100000/254), `$9')') + + +define(`COMMON_AMP_MICTOR_767054', `COMMON_AMP_MICTOR_MIL(`$1',`$2',`$3',`$4',17000,50000,25000,278000)') + +# EXTRACT_BEGIN + +# +## Amp Mictor Connectors +# +define(`PKG_AMP_MICTOR_767054_1', `COMMON_AMP_MICTOR_767054(`$1',`$2',`$3',38)') +define(`PKG_AMP_MICTOR_767054_2', `COMMON_AMP_MICTOR_767054(`$1',`$2',`$3',76)') +define(`PKG_AMP_MICTOR_767054_3', `COMMON_AMP_MICTOR_767054(`$1',`$2',`$3',114)') +define(`PKG_AMP_MICTOR_767054_4', `COMMON_AMP_MICTOR_767054(`$1',`$2',`$3',152)') +define(`PKG_AMP_MICTOR_767054_5', `COMMON_AMP_MICTOR_767054(`$1',`$2',`$3',190)') +define(`PKG_AMP_MICTOR_767054_6', `COMMON_AMP_MICTOR_767054(`$1',`$2',`$3',228)') +define(`PKG_AMP_MICTOR_767054_7', `COMMON_AMP_MICTOR_767054(`$1',`$2',`$3',266)') + +# EXTRACT_END + +# ------------------------------------------------------------------- +# the definition of a MICTOR connector - Michael Sokolov's version +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +define(`COMMON_AMP_MICTOR_MS', + ` + # number of pads + define(`NPADS', `$4') + + # number of segments of 38 pins each + define(`NSEG', eval(NPADS/38)) + + # pad width in 1/1000 mil + define(`PADWIDTH', 17000) + # pad length in 1/1000 mil + define(`PADLENGTH',50000) + # pad pitch 1/1000 mil + define(`PITCH',25000) + # seperation between pads on opposite sides 1/1000 mil + define(`PADSEP',278000) + + # X coordinates for the right hand column of pads (mils) + define(`X1', eval( (PADSEP/2 + PADLENGTH - PADWIDTH/2)/1000)) + define(`X2', eval( (PADSEP/2 + PADWIDTH/2)/1000)) + + # silk screen width (mils) + define(`SILKW', `10') + + # figure out if we have an even or odd number of pins per side + define(`TMP1', eval(NPADS/4)) + define(`TMP2', eval((4*TMP1 - NPADS) == 0)) + ifelse(TMP2, 1, `define(`EVEN',"yes")', `define(`EVEN',"no")') + + # silk bounding box is -XMAX,-YMAX, XMAX,YMAX (mils) + define(`XMAX', `200') + define(`YMAX', eval(250 + NSEG*250 + 50)) + + define(`CURPIN', `1') +Element(0x00 "$1" "$2" "$3" -20 -60 0 100 0x00) +( + define(`SEG', `1') + define(`YOFS', eval((1-NSEG)*25000/2)) + forloop(`i', 1, eval(NPADS / 2), + ` + ifelse(eval(i > SEG*19), 1, + `define(`SEG', incr(SEG)) + define(`YOFS', eval((1-NSEG)*25000/2 + (SEG-1)*25000))',) + ifelse(EVEN,"yes", + `Pad( -X1 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH + YOFS)/1000) + -X2 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)', + `Pad( -X1 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH + YOFS)/1000) + -X2 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)') + define(`CURPIN', incr(CURPIN)) + ifelse(EVEN,"yes", + `Pad( X1 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH + YOFS)/1000) + X2 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)', + `Pad( X1 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH + YOFS)/1000) + X2 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH + YOFS)/1000) + eval(PADWIDTH/1000) "CURPIN" "CURPIN" 0x0)') + define(`CURPIN', incr(CURPIN)) + ') + + define(`GNDpad', `60') + define(`GNDdrl', `32') +# now add the center row of grounding pins + define(`YOFS', eval(250-NSEG*250)) + forloop(`j', 1, NSEG, + `forloop(`i', -2, 2, + `Pin(0 eval(i*100 + YOFS) GNDpad GNDdrl "GND" "CURPIN" 0x01) + define(`CURPIN', incr(CURPIN))' + ) + define(`YOFS', eval(YOFS + 500))' + ) +# the latch pins +# Pin(0 eval(-YOFS - 55) 80 53 "LATCH" "CURPIN" 0x01) +# define(`CURPIN', incr(CURPIN)) +# Pin(0 eval(YOFS + 55) 80 53 "LATCH" "CURPIN" 0x01) +# define(`CURPIN', incr(CURPIN)) +# and the orientation pin + Pin(0 eval(-YOFS+50) 84 84 "ORIENT" "CURPIN" 0x09) + +# and finally the silk screen + ElementLine(-XMAX -YMAX -XMAX YMAX SILKW) + ElementLine(-XMAX YMAX XMAX YMAX SILKW) + ElementLine( XMAX YMAX XMAX -YMAX SILKW) + ElementLine(-XMAX -YMAX -25 -YMAX SILKW) + ElementLine( XMAX -YMAX 25 -YMAX SILKW) + + # punt on the arc on small parts as it can cover the pads + ifelse(eval((PADSEP-PADLENGTH)/1000 > 50), 1, `ElementArc(0 -YMAX 25 25 0 180 SILKW)', ) + + # Mark at the common centroid + Mark(0 0) +)') + +define(`PKG_AMP_MICTOR38', `COMMON_AMP_MICTOR_MS(`$1',`$2',`$3',38)') +define(`PKG_AMP_MICTOR76', `COMMON_AMP_MICTOR_MS(`$1',`$2',`$3',76)') +define(`PKG_AMP_MICTOR114', `COMMON_AMP_MICTOR_MS(`$1',`$2',`$3',114)') +define(`PKG_AMP_MICTOR152', `COMMON_AMP_MICTOR_MS(`$1',`$2',`$3',152)') +define(`PKG_AMP_MICTOR190', `COMMON_AMP_MICTOR_MS(`$1',`$2',`$3',190)') +define(`PKG_AMP_MICTOR228', `COMMON_AMP_MICTOR_MS(`$1',`$2',`$3',228)') +define(`PKG_AMP_MICTOR266', `COMMON_AMP_MICTOR_MS(`$1',`$2',`$3',266)') + +# ------------------------------------------------------------------- +# AMP 0.8 mm Free Height (FH) connector system +# (used in Embedded Planet's RPX bus, for example) +# Footprint designed by Michael Sokolov based on AMP's recommended land pattern +# Pin "numbers" in this version are alphanumeric as used in the RPX bus: +# A1 through A60 on one side and B1 through B60 on the other side +# for the 120-pin version. In reference to the keying features on the +# mating faces, A is the "long" side and B is the "short" one. +# AMP's pin 1 is B1 in our nomenclature. +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins per side (60 for RPX bus) +define(`COMMON_AMP_RPX_PLUG', + ` +Element[0x00 "$1" "$2" "$3" 200000 100000 0 0 0 100 0x00] +( + # first calculate the drawing dimensions from the pin count + define(`dimA', eval(($4 - 1) * 8)) + define(`dimC', eval(dimA + 50)) + define(`dimB', eval(dimC + 16)) + # pad geometry + define(`padwidth', eval(500000/254)) + define(`youter', eval(3200000/254)) + define(`yinner', eval(1200000/254)) + define(`maskextra', 600) + # xpos variable keeps track of X position of pad-pair in .1mm units + define(`xpos', eval(-dimA/2)) + forloop(i, 1, $4, ` + define(`Xpos', eval(xpos*100000/254)) + Pad[Xpos eval(youter-padwidth/2) Xpos eval(yinner+padwidth/2) + padwidth 1000 eval(padwidth+maskextra) + "" "`A'i" ""] + Pad[Xpos eval(-youter+padwidth/2) Xpos eval(-yinner-padwidth/2) + padwidth 1000 eval(padwidth+maskextra) + "" "`B'i" ""] + define(`xpos', eval(xpos + 8)) + ') + define(`holeX', eval(dimC*100000/2/254)) + define(`holediam', eval(800000/254)) + Pin[-holeX 0 holediam 2000 holediam holediam "" "H1" "hole"] + define(`holediam', eval(1200000/254)) + Pin[holeX 0 holediam 2000 holediam holediam "" "H2" "hole"] + define(`silkW', 1000) + define(`silkX', eval(dimB*100000/2/254+silkW/2)) + define(`silkY', eval(3000000/254+silkW/2)) + ElementLine[-silkX -silkY silkX -silkY silkW] + ElementLine[-silkX silkY silkX silkY silkW] + ElementLine[-silkX -silkY -silkX silkY silkW] + ElementLine[ silkX -silkY silkX silkY silkW] + # silk angle-mark for orientation + define(`markX', eval(dimB*100000/2/254-3500)) + ElementLine[-silkX 0 -markX 0 silkW] + ElementLine[-markX 0 -markX -silkY silkW] +)') + +define(`PKG_AMP_RPX_40P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 20)') +define(`PKG_AMP_RPX_60P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 30)') +define(`PKG_AMP_RPX_80P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 40)') +define(`PKG_AMP_RPX_100P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 50)') +define(`PKG_AMP_RPX_120P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 60)') +define(`PKG_AMP_RPX_140P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 70)') +define(`PKG_AMP_RPX_160P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 80)') +define(`PKG_AMP_RPX_180P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3', 90)') +define(`PKG_AMP_RPX_200P', `COMMON_AMP_RPX_PLUG(`$1',`$2',`$3',100)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/amphenol.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,67 @@ +# -*- m4 -*- +# +# $Id: amphenol.inc,v 1.2 2007/02/26 03:52:25 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2003, 2004 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# Amphenol Connectors + + +# ARFX1229 SMA Connector +# 5.08 mm (200 mil) outer pin spacing +# 1.70 mm (67 mil, #51 drill) hole sizes + +define(`PKG_AMPHENOL_ARFX1229', + `define(`PAD_SIZE', `100') + define(`HOLE_SIZE', `67') + define(`CPAD_SIZE', `100') + define(`CHOLE_SIZE', `67') + define(`PAD_SPACE', `200') + define(`CENTER', eval(PAD_SPACE/2)) + define(`SILK', `70') + define(`XMIN', eval(-1*SILK)) + define(`XMAX', eval(PAD_SPACE+SILK)) + define(`YMIN', eval(-1*SILK)) + define(`YMAX', eval(PAD_SPACE+SILK)) +Element(0x00 "$1" "$2" "$3" eval(XMIN+20) eval(YMAX+20) 0 100 0x00) +( + + Pin(CENTER CENTER CPAD_SIZE CHOLE_SIZE "1" 0x01) + Pin(0 0 PAD_SIZE HOLE_SIZE "2" 0x01) + Pin(0 PAD_SPACE PAD_SIZE HOLE_SIZE "3" 0x01) + Pin(PAD_SPACE 0 PAD_SIZE HOLE_SIZE "4" 0x01) + Pin(PAD_SPACE PAD_SPACE PAD_SIZE HOLE_SIZE "5" 0x01) + + # silk screen + # ends + ElementLine(XMIN YMIN XMIN YMAX 10) + ElementLine(XMAX YMAX XMAX YMIN 10) + ElementLine(XMIN YMIN XMAX YMIN 10) + ElementLine(XMAX YMAX XMIN YMAX 10) + Mark(CENTER CENTER) +)') + +# XXX once we get some sort of annotation layer in PCB, the right +# angle connectors should have an annotation showing where the connector +# really goes to. Same for a keep out layer. +define(`PKG_AMPHENOL_ARFX1230',`PKG_AMPHENOL_ARFX1229(`$1', `$2', `$3')') +define(`PKG_AMPHENOL_ARFX1231',`PKG_AMPHENOL_ARFX1229(`$1', `$2', `$3')') +define(`PKG_AMPHENOL_ARFX1232',`PKG_AMPHENOL_ARFX1229(`$1', `$2', `$3')') +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/bga.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,35 @@ +# BGA packages +# A. G. Major, 2000 + +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins along outer edge +# $5: number of rows +# +define(`PKG_BGA', + `define(`XBLOCK', `$4') + define(`YBLOCK', `$5') + define(`PITCH', `50') + define(`DIAMETER', `25') + define(`NUMPINS', eval(4*(XBLOCK-4)*YBLOCK)) +Element(0x00 "$1" "$2" "$3" 100 0 0 100 0x00) +( + forloop(`i', 0, eval(XBLOCK-1), + `forloop(`j', 0, eval(YBLOCK-1), + `PAD(eval(i*PITCH), eval(j*PITCH), eval(i*PITCH), eval(j*PITCH), DIAMETER, 1)' + `PAD(eval((XBLOCK+YBLOCK-j-1)*PITCH), eval(i*PITCH), eval((XBLOCK+YBLOCK-j-1)*PITCH), eval(i*PITCH), DIAMETER, 1)' + `PAD(eval((XBLOCK+YBLOCK-i-1)*PITCH), eval((XBLOCK+YBLOCK-j-1)*PITCH), eval((XBLOCK+YBLOCK-i-1)*PITCH), eval((XBLOCK+YBLOCK-j-1)*PITCH), DIAMETER, 1)' + `PAD(eval(j*PITCH), eval((XBLOCK+YBLOCK-i-1)*PITCH), eval(j*PITCH), eval((XBLOCK+YBLOCK-i-1)*PITCH), DIAMETER, 1)' + )' + ) + ElementLine(eval(-PITCH/2) eval(-1*PITCH) eval((XBLOCK+YBLOCK)*PITCH) eval(-1*PITCH) 10) + ElementLine(eval((XBLOCK+YBLOCK)*PITCH) eval(-1*PITCH) eval((XBLOCK+YBLOCK)*PITCH) eval((XBLOCK+YBLOCK)*PITCH) 10) + ElementLine(eval(-1*PITCH) eval((XBLOCK+YBLOCK)*PITCH) eval((XBLOCK+YBLOCK)*PITCH) eval((XBLOCK+YBLOCK)*PITCH) 10) + ElementLine(eval(-1*PITCH) eval(-PITCH/2) eval(-1*PITCH) eval((XBLOCK+YBLOCK)*PITCH) 10) + ElementLine(eval(-PITCH/2) eval(-PITCH) eval(-PITCH/2) eval(-PITCH/2) 10) + ElementLine(eval(-PITCH) eval(-PITCH/2) eval(-PITCH/2) eval(-PITCH/2) 10) + Mark(eval((YBLOCK+1)*PITCH) eval((YBLOCK+1)*PITCH)) +)') + +# -------------------------------------------------------------------
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/bourns.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,149 @@ +# -*- m4 -*- +# +# $Id: bourns.inc,v 1.2 2007/02/26 03:52:26 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2003, 2005 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# +# Bourns Specific Footprints + + +# Surface mount trim pots, such as the 3224 series. +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin 1,3 width (1/100 mm) width is in the direction parallel to the +# $5: pin 1,3 length (1/100 mm) line which intersects pins 1 and 3 +# $6: pin 2 width (1/100 mm) +# $7: pin 2 length (1/100 mm) +# $8: spacing from pad center to pad center between 2 and 1,3 (1/100 mm) +# $9: spacing from pad center to pad center between 1 and 3 (1/100 mm) +# $A: package width (1/100 mm) + +define(`PKG_BOURNS_GENERIC_POT', + ` + # pin 1,3 width, length (1/100 mm) + define(`W13', `$4') + define(`L13', `$5') + + # pin 2 width, length (1/100 mm) + define(`W2', `$6') + define(`L2', `$7') + + # spacing from pad center to pad center between 2 and 1,3 (1/100 mm) + define(`S12', `$8') + # spacing from pad center to pad center between 1 and 3 (1/100 mm) + define(`S13', `$9') + + # package width (1/100 mm) + define(`WIDTH', `$A') + + # silkscreen width (mils) + define(`SILKW', `10') + + # how much space to leave around the part before the + # silk screen (mils) + define(`SILKS', `8') + # lower right corner for silk screen (mil) + ifelse(eval(L2 > L13), 1 + define(`SILKX', eval((S12+L2)*50/254 + SILKS + SILKW/2)), + define(`SILKX', eval((S12+L13)*50/254 + SILKS + SILKW/2)) + ) + define(`SILKY', eval((WIDTH/2)*100/254 + SILKS + SILKW/2)) + + # refdes text size (mil) + define(`TEXTSIZE', 100) + # x,y coordinates for refdes label (mil) + define(`TEXTX', -SILKX) + define(`TEXTY', eval(-SILKY - 10 - TEXTSIZE/2)) + +Element(0x00 "$1" "$2" "$3" TEXTX TEXTY 0 TEXTSIZE 0x00) +( + +# pin 1 +ifelse(0, eval(W13>L13), + # Pads which have the perpendicular pad dimension less + # than or equal to the parallel pad dimension + Pad(eval( (S12 - L13 + W13)*50/254) eval( S13*50/254) + eval( (S12 + L13 - W13)*50/254) eval( S13*50/254) eval(W13*100/254) "1" 0x100) + , + # Pads which have the perpendicular pad dimension greater + # than or equal to the parallel pad dimension + Pad(eval( (S12 + L13)*50/254) eval((-S13 - W13 + L13)*50/254) + eval( (S12 + L13)*50/254) eval((-S13 + W13 - L13)*50/254) eval(L13*100/254) "1" 0x100) + ) + +# pin 2 +ifelse(0, eval(W2>L2), + # Pads which have the perpendicular pad dimension less + # than or equal to the parallel pad dimension + Pad(eval( (-S12 - L2 + W2)*50/254) 0 + eval( (-S12 + L2 - W2)*50/254) 0 eval(W2*100/254) "2" 0x100) + , + # Pads which have the Y (width) pad dimension greater + # than or equal to the X (length) pad dimension + Pad(eval( -S12*50/254) eval((- W2 + L2)*50/254) + eval( -S12*50/254) eval(( W2 - L2)*50/254) eval(L2*100/254) "2" 0x100) + ) + +# pin 3 +ifelse(0, eval(W13>L13), + # Pads which have the perpendicular pad dimension less + # than or equal to the parallel pad dimension + Pad(eval( (S12 - L13 + W13)*50/254) eval(-S13*50/254) + eval( (S12 + L13 - W13)*50/254) eval(-S13*50/254) eval(W13*100/254) "3" 0x100) + , + # Pads which have the perpendicular pad dimension greater + # than or equal to the parallel pad dimension + Pad(eval( (S12 + L13)*50/254) eval((-S13 - W13 + L13)*50/254) + eval( (S12 + L13)*50/254) eval((-S13 + W13 - L13)*50/254) eval(L13*100/254) "3" 0x100) + ) + +# Silk screen around package +ElementLine( SILKX SILKY SILKX -SILKY SILKW) +ElementLine( SILKX -SILKY -SILKX -SILKY SILKW) +ElementLine(-SILKX -SILKY -SILKX SILKY SILKW) +ElementLine(-SILKX SILKY SILKX SILKY SILKW) + +# Mark at the center of the part +Mark(0 0) +)') + +# ------------------------------------------------------------------- + +# EXTRACT_BEGIN + + +# +## Bourns 3224 Series SMT Trim Pot +# + +define(`PKG_BOURNS_3224G', `PKG_BOURNS_GENERIC_POT(`$1',`$2',`$3', + `127', `127', `200', `127', `520', `230', `480')') +define(`PKG_BOURNS_3224J', `PKG_BOURNS_GENERIC_POT(`$1',`$2',`$3', + `130', `200', `200', `200', `400', `230', `480')') +define(`PKG_BOURNS_3224W', `PKG_BOURNS_GENERIC_POT(`$1',`$2',`$3', + `130', `160', `200', `160', `290', `254', `480')') +define(`PKG_BOURNS_3224X', `PKG_BOURNS_GENERIC_POT(`$1',`$2',`$3', + `132', `190', `200', `190', `510', `254', `480')') + +# EXTRACT_END +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/bre.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,57 @@ +# -*- m4 -*- +# $Id: bre.inc,v 1.1 2007/08/25 16:59:17 msokolov Exp $ +# +# Bottom lead rectangular components + +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: X total size of component +# $5: Y total size of component +# $6: distance between the pins +# +# Basic building block macro takes new PCB units (.01 mil), +# wrapper macros are provided for mils and metric. + +define(`PKG_BOTTOMRECT_BASIC', + `define(`halfX', eval($4 / 2)) + define(`halfY', eval($5 / 2)) + define(`halfpinX', eval($6 / 2)) + define(`silkW', 1000) + define(`silkX', eval(halfX + silkW/2)) + define(`silkY', eval(halfY + silkW/2)) + # how much to grow the pads by for soldermask + define(`maskGrow', 300) + # clearance from planes + define(`clearance', 1000) + # drill and copper annulus for the pins, taken from PKG_LED + define(`drill', 4300) + define(`annulus', 6500) + # some math for the Pin syntax + define(`pinclear', eval(clearance*2)) + define(`pinmask', eval(annulus + maskGrow*2)) +Element[0x00 "`$1'" "`$2'" "`$3'" 0 0 -halfX eval(halfY + silkW*2) 0 100 0x00] +( + # outline + ElementLine[-silkX -silkY -silkX silkY silkW] + ElementLine[-silkX silkY silkX silkY silkW] + ElementLine[ silkX silkY silkX -silkY silkW] + ElementLine[ silkX -silkY -silkX -silkY silkW] + # pins + Pin[-halfpinX 0 annulus pinclear pinmask drill "1" "1" 0x0] + Pin[ halfpinX 0 annulus pinclear pinmask drill "2" "2" 0x0] +)') + +define(`PKG_BOTTOMRECT_MIL', `PKG_BOTTOMRECT_BASIC(`$1',`$2',`$3', + eval($4 * 100), eval($5 * 100), eval($6 * 100))') + +# the actual units for the following are .1 mm +define(`PKG_BOTTOMRECT_MM', `PKG_BOTTOMRECT_BASIC(`$1',`$2',`$3', + eval($4*100000/254), eval($5*100000/254), eval($6*100000/254))') + +# polyester film capacitors +define(`PKG_PFC185_74_150', `PKG_BOTTOMRECT_MM(`$1',`$2',`$3', 185, 74, 150)') + +# Raychem telecom PTC resistors +define(`PKG_TR600_150', `PKG_BOTTOMRECT_MIL(`$1',`$2',`$3', 354, 180, 197)') +define(`PKG_TR600_160', `PKG_BOTTOMRECT_MIL(`$1',`$2',`$3', 630, 236, 197)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/btb.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,84 @@ +# -*- m4 -*- +# $Id: btb.inc,v 1.1 2011/06/18 19:36:29 msokolov Exp $ +# +# Board-to-board connectors + +# Hirose DF40 series +# used by LogicPD for their TI ARM SOMs and development kits +# +# Only the header/plug version has been created so far; the motivating +# application is making a board that would mate with LogicPD's AM3517 +# development kit baseboard. +# +# The connector itself is not polarized and has no officially-defined +# pin numbering convention; the pin numbering used in this footprint +# is that used by LogicPD. +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: contacts per side (50 for 100 contacts total as used by LPD) +define(`COMMON_DF40C_HDR', + ` +Element[0x00 "$1" "$2" "$3" 200000 100000 0 0 0 100 0x00] +( + # X position preliminary computations (.01mm units) + define(`dimB', eval(($4 - 1) * 40)) + define(`dimA', eval(dimB + 192)) + # pad geometry + define(`padwidth', eval(230000/254)) + define(`fatpadwidth', eval(350000/254)) + define(`youter', eval(3370000/2/254)) + define(`yinner', eval(2050000/2/254)) + define(`maskextra', 600) + # xpos variable keeps track of X position of pad-pair in .01mm units + define(`xpos', eval(dimB/2)) + define(`CURPIN', 1) + forloop(i, 1, $4, ` + define(`Xpos', eval(xpos*10000/254)) + Pad[Xpos eval(youter-padwidth/2) Xpos eval(yinner+padwidth/2) + padwidth 1000 eval(padwidth+maskextra) + "" "CURPIN" ""] + define(`CURPIN', eval(CURPIN + 1)) + Pad[Xpos eval(-youter+padwidth/2) Xpos eval(-yinner-padwidth/2) + padwidth 1000 eval(padwidth+maskextra) + "" "CURPIN" ""] + define(`CURPIN', eval(CURPIN + 1)) + define(`xpos', eval(xpos - 40)) + ') + # 4 extra mechanical-only pins + define(`Xpos', eval((dimB*5 + 475) * 1000 / 254)) + Pad[Xpos eval(youter-fatpadwidth/2) Xpos eval(yinner+fatpadwidth/2) + fatpadwidth 1000 eval(fatpadwidth+maskextra) + "" "M1" ""] + Pad[Xpos eval(-youter+fatpadwidth/2) Xpos eval(-yinner-fatpadwidth/2) + fatpadwidth 1000 eval(fatpadwidth+maskextra) + "" "M2" ""] + Pad[-Xpos eval(youter-fatpadwidth/2) -Xpos eval(yinner+fatpadwidth/2) + fatpadwidth 1000 eval(fatpadwidth+maskextra) + "" "M3" ""] + Pad[-Xpos eval(-youter+fatpadwidth/2) -Xpos eval(-yinner-fatpadwidth/2) + fatpadwidth 1000 eval(fatpadwidth+maskextra) + "" "M4" ""] + # silk outline + define(`silkW', 1000) + define(`silkX', eval(dimA*10000/2/254+silkW/2)) + define(`silkY', eval(3370000/2/254+300+silkW/2)) + ElementLine[-silkX -silkY silkX -silkY silkW] + ElementLine[-silkX silkY silkX silkY silkW] + ElementLine[-silkX -silkY -silkX silkY silkW] + ElementLine[ silkX -silkY silkX silkY silkW] +)') + +define(`PKG_DF40C_10DP', `COMMON_DF40C_HDR(`$1',`$2',`$3', 5)') +define(`PKG_DF40C_20DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',10)') +define(`PKG_DF40C_24DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',12)') +define(`PKG_DF40C_30DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',15)') +define(`PKG_DF40C_40DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',20)') +define(`PKG_DF40C_44DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',22)') +define(`PKG_DF40C_50DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',25)') +define(`PKG_DF40C_60DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',30)') +define(`PKG_DF40C_70DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',35)') +define(`PKG_DF40C_80DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',40)') +define(`PKG_DF40C_90DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',45)') +define(`PKG_DF40C_100DP', `COMMON_DF40C_HDR(`$1',`$2',`$3',50)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/common.m4 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,128 @@ +divert(-1) +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: common.m4,v 1.9 2012/11/07 19:02:52 msokolov Exp $ +# +# common defines for packages +# +# ------------------------------------------------------------------- +# create a single object +# $1: mask name +# $2: 'value' of the new object +# $3: package of the circuit +# +define(`CreateObject', + `ifdef(`PinList_$1', `DefinePinList(PinList_$1)')' + `PKG_$3(`Description_$1', ,``$2'', Param1_$1, Param2_$1)' +) + +# this one is used to show the correct value for the footprint attribute +# in a gschem (www.geda.seul.org) schematic. See QueryLibrary.sh +define(`QueryObject', + `ifdef(`PinList_$1', `DefinePinList(PinList_$1)')' +`$3 ifdef(`Param1_$1', `Param1_$1') ifdef(`Param2_$1', `Param2_$1')' +) + +# ------------------------------------------------------------------- +# define for-loops like the manual tells us +# +define(`forloop', + `define(`$1', `$2')_forloop(`$1', `$2', `$3', `$4')') +define(`_forloop', + `$4`'ifelse($1, `$3', , + `define(`$1', incr($1))_forloop(`$1', `$2', `$3', `$4')')') + +# version with step control added by Michael Spacefalcon +define(`forloop2', + `define(`$1', `$2')_forloop2(`$1', `$2', `$3', `$4', `$5')') +define(`_forloop2', + `$5`'ifelse($1, `$3', , + `define(`$1', eval($1 + $4))_forloop2(`$1', `$2', `$3', `$4', `$5')')') + +# ------------------------------------------------------------------- +# the following definitions evaluate the list of pin-names +# missing names will be defined as 'P_#' +# +# the first two arguments are skipped +# +define(`PIN', `Pin($1 $2 $3 $4 ifdef(`P_$5', "P_$5", "$5") ifelse($5, 1, 0x101, 0x01))') +define(`PAD', `Pad($1 $2 $3 $4 $5 ifdef(`P_$6', "P_$6", "$6") ifelse($6, 1, 0x00, 0x100))') + +define(`EDGECONN', `Pad($1 $2 $3 $4 $5 ifdef(`P_$6', "P_$6", "$6") "$6" $7)') + +# This stuff won't work with dmr m4 +#define(`DEFPIN', `define(`count', incr(count))' `define(`P_'count, $1)') +#define(`DefinePinList', `ifelse($#, 1, , +# `pushdef(`count')' +# `define(`count', 0)' +# `_DEFPINLIST($@)' +# `popdef(`count')')') +#define(`_DEFPINLIST', `ifelse($#, 0, , $#, 1, `DEFPIN(`$1')', +# `DEFPIN(`$1')'` +# _DEFPINLIST(shift($@))')') +# +#define(`args',` +# ifelse($#, 0, , $#, 1,`define(`arg'cnt,`$1')', +# `define(`arg'cnt,`$1') define(`cnt',incr(cnt)) args(shift($@))')') + +include(amp.inc) +include(amphenol.inc) +include(bga.inc) +include(bourns.inc) +include(bre.inc) +include(btb.inc) +include(connector.inc) +include(cts.inc) +include(dil.inc) +include(dpr.inc) +include(geda.inc) +include(hirose.inc) +include(johnstech.inc) +include(midcom.inc) +include(minicircuits.inc) +include(misc.inc) +include(panasonic.inc) +# pci.inc uses stuff that won't work with dmr m4 +#include(pci.inc) +include(plcc.inc) +include(qfn.inc) +include(qfp.inc) +include(qfp2.inc) +include(qfpdj.inc) +include(resistor_adjust.inc) +include(rules.inc) +include(smt.inc) +include(smtosc.inc) +include(to.inc) +include(zif.inc) + +# if any of these files exist, then include them. +# this makes it a bit easier to configure pcb without +# mucking with app-defaults every time you launch it +sinclude(site-config.inc) +sinclude(user-config.inc) +sinclude(proj-config.inc) + +divert(0)dnl
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/connector.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,801 @@ +*# -*- m4 -*- +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: connector.inc,v 1.5 2009/12/26 22:53:39 msokolov Exp $ +# +# connector packages + +# ------------------------------------------------------------------- +# the definition of a single connector +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of rows +# $5: number of columns +# +define(`PKG_CONNECTOR', + `define(`MAXY', eval(`$4' * 100)) + define(`MAXX', eval(`$5' * 100)) +Element(0x00 "$1" "$2" "$3" eval(MAXX + 60) 0 3 100 0x00) +( + forloop(`row', 1, $4, `forloop(`col', 1, $5, + `PIN(eval(col * 100 -50), eval(row * 100 -50), 60, 38, eval((row-1)*$5+col)) + ') ') + ElementLine(0 0 0 MAXY 20) + ElementLine(0 MAXY MAXX MAXY 20) + ElementLine(MAXX MAXY MAXX 0 20) + ElementLine(MAXX 0 0 0 20) + ElementLine(0 100 100 100 10) + ElementLine(100 100 100 0 10) + Mark(50 50) +)') + +# ------------------------------------------------------------------- +# the definition of a 2 column header connector with DIP +# pin numbering. Use PKG_CONNECTOR for ribbon cable numbering +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of rows +# +define(`PKG_CONNECTOR_DIL', + `define(`MAXY', eval(`$4' * 100)) + define(`MAXX', `200') +Element(0x00 "$1" "$2" "$3" eval(MAXX + 60) 0 3 100 0x00) +( + forloop(`row', 1, eval(`$4'), + `PIN(50, eval(row * 100 -50), 60, 38, eval(row)) + ') + forloop(`row', 1, eval(`$4'), + `PIN(150, eval(($4 + 1 - row) * 100 -50), 60, 38, eval($4 + row)) + ') + ElementLine(0 0 0 MAXY 20) + ElementLine(0 MAXY MAXX MAXY 20) + ElementLine(MAXX MAXY MAXX 0 20) + ElementLine(MAXX 0 0 0 20) + ElementLine(0 100 100 100 10) + ElementLine(100 100 100 0 10) + Mark(50 50) +)') + + + +# --------------------------------------------------------------- +# base definition (housing) for connector DIN 41.612 +# 11/95 Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +# female package added 05/96 also by Volker Bosch +# +# derived from above for 48 - Pin Connectors from the same series +# Holm Tiffe +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: requested rows a,b,c +# +define(`PKG_DIN41_612MALE_SMALL', + `define(`XPOS', `eval(300 + 100 * i)') + define(`MINY', 300) +Element(0x00 "$1" "$2" "$3" 520 550 0 200 0x00) +( + # Reihe a + ifelse(index(`$4', `a'), `-1', , + forloop(`i', 1, 16, `PIN(eval(2000 - 100 *i), 300, 60, 30, i) + ')) + + # Reihe b + ifelse(index(`$4', `b'), `-1', , `define(`MINY', 200)' + forloop(`i', 1, 16, `PIN(eval(2000 - 100 *i), 200, 60, 30, eval(16 + i)) + ')) + + # Reihe c + ifelse(index(`$4', `c'), `-1', , `define(`MINY', 100)' + forloop(`i', 1, 16, `PIN(eval(2000 - 100 *i), 100, 60, 30, eval(32 + i)) + ')) + # Rueckseite Kontaktstifte + forloop(`i', 1, 16, `ElementLine(XPOS MINY XPOS 375 40) + ') + + # Befestigungsbohrung + Pin( 200 400 120 80 "M1" 0x01) + Pin(2100 400 120 80 "M2" 0x01) + + # Begrenzung M1 + ElementLine( 100 300 320 300 20) + ElementLine( 320 300 320 395 20) + ElementLine( 320 395 320 620 10) + ElementLine( 320 620 200 620 10) + ElementLine( 200 620 100 620 20) + ElementLine( 100 620 100 300 20) + + # Begrenzung M2 + ElementLine(1980 300 2200 300 20) + ElementLine(2200 300 2200 620 20) + ElementLine(2200 620 2100 620 20) + ElementLine(2100 620 1980 620 10) + ElementLine(1980 620 1980 395 10) + ElementLine(1980 395 1980 300 20) + + # Kante Pins + ElementLine( 320 395 1980 395 20) + + # Kanten Stifte + ElementLine( 200 620 200 800 20) + ElementLine( 200 800 2100 800 20) + ElementLine(2100 800 2100 620 20) + + Mark(1900 300) +)') + +define(`PKG_DIN41_612FEMALE_SMALL', + `define(`MAXX', 420) + define(`MAXX1', `eval(MAXX -170)') + define(`MAXX2', `eval(MAXX -40)') +Element(0x00 "$1" "$2" "$3" 50 100 3 200 0x00) +( + # Reihe a + ifelse(index(`$4', `a'), `-1', , + forloop(`i', 1, 16, `PIN(200, eval(300 + 100 *i), 60, 30, i) + ')) + + # Reihe b + ifelse(index(`$4', `b'), `-1', , + forloop(`i', 1, 16, `PIN(300, eval(300 + 100 *i), 60, 30, eval(16 + i)) + ')) + + # Reihe c + ifelse(index(`$4', `c'), `-1', , `define(`MAXX', 520)' + forloop(`i', 1, 16, `PIN(400, eval(300 + 100 *i), 60, 30, eval(32 + i)) + ')) + + # Befestigungsbohrung + Pin(290 180 120 80 "M1" 0x01) + Pin(290 2120 120 80 "M2" 0x01) + + # Aeussere Begrenzung + ElementLine( 80 80 MAXX 80 20) + ElementLine(MAXX 80 MAXX 2220 20) + ElementLine(MAXX 2220 80 2220 20) + ElementLine( 80 2220 80 80 20) + + # Innere Begrenzung + ElementLine(120 320 MAXX1 320 10) + ElementLine(MAXX1 320 MAXX1 360 10) + ElementLine(MAXX1 360 MAXX2 360 10) + ElementLine(MAXX2 360 MAXX2 1940 10) + ElementLine(MAXX2 1940 MAXX1 1940 10) + ElementLine(MAXX1 1940 MAXX1 1980 10) + ElementLine(MAXX1 1980 120 1980 10) + ElementLine(120 1980 120 320 10) + + # Markierung: Pin 1a + Mark(200 400) +)') + + +# --------------------------------------------------------------- +# base definition (housing) for connector DIN 41.612 +# 11/95 Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +# female package added 05/96 also by Volker Bosch +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: requested rows a,b,c +# +define(`PKG_DIN41_612MALE', + `define(`XPOS', `eval(300 + 100 * i)') + define(`MINY', 300) +Element(0x00 "$1" "$2" "$3" 520 550 0 200 0x00) +( + # Reihe a + ifelse(index(`$4', `a'), `-1', , + forloop(`i', 1, 32, `PIN(eval(3600 - 100 *i), 300, 60, 30, i) + ')) + + # Reihe b + ifelse(index(`$4', `b'), `-1', , `define(`MINY', 200)' + forloop(`i', 1, 32, `PIN(eval(3600 - 100 *i), 200, 60, 30, eval(32 + i)) + ')) + + # Reihe c + ifelse(index(`$4', `c'), `-1', , `define(`MINY', 100)' + forloop(`i', 1, 32, `PIN(eval(3600 - 100 *i), 100, 60, 30, eval(64 + i)) + ')) + # Rueckseite Kontaktstifte + forloop(`i', 1, 32, `ElementLine(XPOS MINY XPOS 375 40) + ') + + # Befestigungsbohrung + Pin( 200 400 120 80 "M1" 0x01) + Pin(3700 400 120 80 "M2" 0x01) + + # Begrenzung M1 + ElementLine( 100 300 320 300 20) + ElementLine( 320 300 320 395 20) + ElementLine( 320 395 320 620 10) + ElementLine( 320 620 200 620 10) + ElementLine( 200 620 100 620 20) + ElementLine( 100 620 100 300 20) + + # Begrenzung M2 + ElementLine(3580 300 3800 300 20) + ElementLine(3800 300 3800 620 20) + ElementLine(3800 620 3700 620 20) + ElementLine(3700 620 3580 620 10) + ElementLine(3580 620 3580 395 10) + ElementLine(3580 395 3580 300 20) + + # Kante Pins + ElementLine( 320 395 3580 395 20) + + # Kanten Stifte + ElementLine( 200 620 200 800 20) + ElementLine( 200 800 3700 800 20) + ElementLine(3700 800 3700 620 20) + + Mark(3500 300) +)') + +define(`PKG_DIN41_612FEMALE', + `define(`MAXX', 420) + define(`MAXX1', `eval(MAXX -170)') + define(`MAXX2', `eval(MAXX -40)') +Element(0x00 "$1" "$2" "$3" 50 100 3 200 0x00) +( + # Reihe a + ifelse(index(`$4', `a'), `-1', , + forloop(`i', 1, 32, `PIN(200, eval(300 + 100 *i), 60, 30, i) + ')) + + # Reihe b + ifelse(index(`$4', `b'), `-1', , + forloop(`i', 1, 32, `PIN(300, eval(300 + 100 *i), 60, 30, eval(32 + i)) + ')) + + # Reihe c + ifelse(index(`$4', `c'), `-1', , `define(`MAXX', 520)' + forloop(`i', 1, 32, `PIN(400, eval(300 + 100 *i), 60, 30, eval(64 + i)) + ')) + + # Befestigungsbohrung + Pin(290 180 120 80 "M1" 0x01) + Pin(290 3720 120 80 "M2" 0x01) + + # Aeussere Begrenzung + ElementLine( 80 80 MAXX 80 20) + ElementLine(MAXX 80 MAXX 3820 20) + ElementLine(MAXX 3820 80 3820 20) + ElementLine( 80 3820 80 80 20) + + # Innere Begrenzung + ElementLine(120 320 MAXX1 320 10) + ElementLine(MAXX1 320 MAXX1 360 10) + ElementLine(MAXX1 360 MAXX2 360 10) + ElementLine(MAXX2 360 MAXX2 3540 10) + ElementLine(MAXX2 3540 MAXX1 3540 10) + ElementLine(MAXX1 3540 MAXX1 3580 10) + ElementLine(MAXX1 3580 120 3580 10) + ElementLine(120 3580 120 320 10) + + # Markierung: Pin 1a + Mark(200 400) +)') + +# --------------------------------------------------------------- +# base definition (housing) for connector DIN 41.651 laying and standing +# 05/96 Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +# +# Changed hole size from 20 mils to 28 mils; 07/00 LRDoolittle@lbl.gov +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# +define(`PKG_DIN41_651LAY', + `define(`MAXY', eval($4/2 *100 +400)) + define(`CENTERY', eval($4/2 *50 +425)) +Element(0x00 "$1" "$2" "$3" 400 250 3 200 0x00) +( + forloop(`i', 1, eval($4 / 2), + `PIN(100, eval(100*i +400), 60, 28, eval(2*i-1)) + PIN(200, eval(100*i +400), 60, 28, eval(2*i)) + ') + + # Befestigungsbohrung + Pin(180 270 100 80 "M1" 0x01) + Pin(180 eval(MAXY+230) 100 80 "M2" 0x01) + + # aeusserer Rahmen + ElementLine(80 70 335 70 20) + ElementLine(335 70 770 200 20) + ElementLine(770 200 770 300 20) + ElementLine(770 300 610 390 20) + ElementLine(610 390 610 eval(MAXY+150) 20) + ElementLine(610 eval(MAXY+150) 770 eval(MAXY+200) 20) + ElementLine(770 eval(MAXY+200) 770 eval(MAXY+300) 20) + ElementLine(770 eval(MAXY+300) 335 eval(MAXY+430) 20) + ElementLine(335 eval(MAXY+430) 80 eval(MAXY+430) 20) + ElementLine( 80 eval(MAXY+430) 80 70 20) + + # Codieraussparung + ElementLine(610 eval(CENTERY -50) 435 eval(CENTERY -50) 5) + ElementLine(435 eval(CENTERY -50) 435 eval(CENTERY +100) 5) + ElementLine(435 eval(CENTERY +100) 610 eval(CENTERY +100) 5) + + # Markierung Pin 1 + ElementLine(610 450 500 500 5) + ElementLine(500 500 610 550 5) + + # Plazierungsmarkierung == Pin 1 + Mark(100 500) +)') + +define(`PKG_DIN41_651STAND', + `define(`MAXY', eval($4/2 *100 +400)) + define(`CENTERY', eval($4/2 *50 +425)) +Element(0x00 "$1" "$2" "$3" 50 100 3 200 0x00) +( + forloop(`i', 1, eval($4 / 2), + `PIN(200, eval(100*i +400), 60, 28, eval(2*i-1)) + PIN(300, eval(100*i +400), 60, 28, eval(2*i)) + ') + # aeusserer Rahmen + ElementLine(90 70 410 70 20) + ElementLine(410 70 410 eval(MAXY +430) 20) + ElementLine(410 eval(MAXY +430) 90 eval(MAXY +430) 20) + ElementLine(90 eval(MAXY +430) 90 70 20) + + # innerer Rahmen mit Codieraussparung + ElementLine(110 350 390 350 5) + ElementLine(390 350 390 eval(MAXY +150) 5) + ElementLine(390 eval(MAXY +150) 110 eval(MAXY +150) 5) + ElementLine(110 eval(MAXY +150) 110 eval(CENTERY +100) 5) + ElementLine(110 eval(CENTERY +100) 90 eval(CENTERY +100) 5) + ElementLine(90 eval(CENTERY -50) 110 eval(CENTERY -50) 5) + ElementLine(110 eval(CENTERY -50) 110 350 5) + + # Markierung Pin 1 + ElementLine(110 390 150 350 5) + + # Auswurfhebel oben + ElementLine(200 70 200 350 5) + ElementLine(300 70 300 350 5) + + # Auswurfhebel unten + ElementLine(200 eval(MAXY+150) 200 eval(MAXY+430) 5) + ElementLine(300 eval(MAXY+150) 300 eval(MAXY+430) 5) + + # Plazierungsmarkierung == Pin 1 + Mark(200 500) +)') + +# --------------------------------------------------------------- +# base definition (housing) for SUB-D connectors, laying +# 11/95 Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +# female package added 05/96 also by Volker Bosch +# Pins reordered, 12/99 Larry Doolittle <LRDoolittle@lbl.gov> + +# Connector dimensions changed! No, these stupid things don't +# line up neatly on a 50 mil grid. Now corresponds to AMP's +# Application Specification 114-40013 03-APR-97 Rev B, for +# AMPLIMITE[TM] HD-20 Series 454 and 545. +# Also pulled silkscreen lines away from pins by NOSMUDGE. +# 12/99 Larry Doolittle <LRDoolittle@lbl.gov> +# +# Parameterized silkscreen in terms of PANEL_DISTANCE, the distance +# from the drilling holes to the intended edge of the board. +# According to the drawing listed above, that should be 398 or 489 +# plus some unknown flange thickness. For the part I have in my hand +# (AMP 747846-4), it's about 365 mils. The original version of this +# macro had it hard coded at 460. I also reduced size of pads and holes +# to 60/35. The drawing listed above recommends 47 mil holes, the part +# in my hand has 28 mil pins. +# +# Status: Female tested, works great, 07-Jan-2000. +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins +# +# base is upper drilling hole +# +define(`PKG_SUBD_LAY_BASE', + `define(`BASEX', 1000) + define(`BASEY', 1000) + define(`PY1', eval(BASEY +270)) + define(`PY2', eval(PY1 +($4-1)/2*108)) + define(`OFFSET', eval(($4+1)/2)) + define(`PANEL_DISTANCE', 365) +Element(0x00 "$1" "$2" "$3" eval(BASEX-0) eval(PY2-0) 1 150 0x00) +( + # Gehaeuse (schmaler Kasten incl. Bohrungen) + define(`X1', eval(BASEX-PANEL_DISTANCE)) + define(`Y1', eval(PY1-390)) + define(`X2', eval(BASEX-PANEL_DISTANCE+30)) + define(`Y2', eval(PY2+390)) + ElementLine(X1 Y1 X2 Y1 10) + ElementLine(X2 Y1 X2 Y2 10) + ElementLine(X2 Y2 X1 Y2 10) + ElementLine(X1 Y2 X1 Y1 10) + ElementLine(X1 eval(Y1+60) X2 eval(Y1+60) 10) + ElementLine(X1 eval(Y1+180) X2 eval(Y1+180) 10) + ElementLine(X1 eval(Y2-60) X2 eval(Y2-60) 10) + ElementLine(X1 eval(Y2-180) X2 eval(Y2-180) 10) + + # Gehaeuse (aeusserer Kasten) + # This part of the connector normally hangs off the circuit board, + # so it is confusing to actually mark it on the silkscreen + # define(`X1', `eval(BASEX-PANEL_DISTANCE-260)') + # define(`Y1', `eval(PY1-100)') + # define(`X2', `eval(BASEX-PANEL_DISTANCE)') + # define(`Y2', `eval(PY2+100)') + # ElementLine(X1 Y1 X2 Y1 20) + # ElementLine(X2 Y1 X2 Y2 10) + # ElementLine(X2 Y2 X1 Y2 20) + # ElementLine(X1 Y2 X1 Y1 20) + + # Gehaeuse (innerer Kasten) + define(`X1', eval(BASEX-PANEL_DISTANCE+30)) + define(`Y1', eval(PY1-160)) + define(`X2', eval(BASEX-230)) + define(`Y2', eval(PY2+160)) + ElementLine(X1 Y1 X2 Y1 20) + ElementLine(X2 Y1 X2 Y2 20) + ElementLine(X2 Y2 X1 Y2 20) + ElementLine(X1 Y2 X1 Y1 10) + + # Pins + SUBD_SUBFUNCTION + + # Befestigungsbohrung + Pin(BASEX BASEY 250 125 "C1" 0x01) + Pin(BASEX eval(PY2+270) 250 125 "C2" 0x01) + +)') + +define(`PKG_SUBD_MALE_LAY', + `define(`SUBD_SUBFUNCTION', + ` + define(`NOSMUDGE', 40) + # First row + forloop(`i', 1, eval($4/2), + `define(`Y', eval(PY1 +(i-1)*108)) + PIN(eval(BASEX+56), Y, 60, 35, i) + ElementLine(eval(BASEX+56-NOSMUDGE) Y X2 Y 20) + ') + + # Last pin in first row + PIN(eval(BASEX+56), PY2, 60, 35, OFFSET) + ElementLine(eval(BASEX+56-NOSMUDGE) PY2 X2 PY2 20) + + # Second row + forloop(`i', 1, eval($4/2), + `define(`Y', eval(PY1 +(i-1)*108+54)) + PIN(eval(BASEX-56), Y, 60, 35, eval(i+OFFSET)) + ElementLine(eval(BASEX-56-NOSMUDGE) Y X2 Y 20) + ') + # Plazierungsmarkierung == PIN 1 + Mark(eval(BASEX +50) PY1) + ')' + `PKG_SUBD_LAY_BASE(`$1', `$2', `$3', `$4')' +) + +define(`PKG_SUBD_FEMALE_LAY', + `define(`SUBD_SUBFUNCTION', + ` + define(`NOSMUDGE', 40) + # Pin 1 + PIN(eval(BASEX+56), PY2, 60, 35, 1) + ElementLine(eval(BASEX+56-NOSMUDGE) PY2 X2 PY2 20) + + # Plazierungsmarkierung == PIN 1 + # Changed PY1 to PY2 13-Dec-1999 LRD + Mark(eval(BASEX +56) PY2) + + # Remainder of the first row + forloop(`i', 1, eval($4/2), + `define(`Y', eval(PY1 +($4/2-i)*108)) + PIN(eval(BASEX+56), Y, 60, 35, eval($4/2+i+2-OFFSET)) + ElementLine(eval(BASEX+56-NOSMUDGE) Y X2 Y 20) + ') + + # Second row + forloop(`i', 1, eval($4/2), + `define(`Y', eval(PY1 +($4/2-i)*108+54)) + PIN(eval(BASEX-56), Y, 60, 35, eval($4/2+i+1)) + ElementLine(eval(BASEX-56-NOSMUDGE) Y X2 Y 20) + ') + ')' + `PKG_SUBD_LAY_BASE(`$1', `$2', `$3', `$4')' +) + +# --------------------------------------------------------------- +# definition for a right angle BNC connector, +# such as Amphenol 31-5640-1010 or OUPIIN 8928 +# 12/99 Larry Doolittle <LRDoolittle@lbl.gov> +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins +# +# base is one of the pegs +# +define(`PKG_BNC_LAY', + `define(`BASEX', 200) + define(`BASEY', -200) +Element(0x00 "$1" "$2" "$3" BASEX eval(BASEY+200) 3 100 0x00) +( + define(`X1', eval(BASEX-260)) + define(`Y1', eval(BASEY-90)) + define(`X2', eval(BASEX+290)) + define(`Y2', eval(BASEY+490)) + ElementLine(X1 Y1 X2 Y1 10) + ElementLine(X2 Y1 X2 Y2 10) + ElementLine(X2 Y2 X1 Y2 10) + ElementLine(X1 Y2 X1 Y1 10) + PIN(eval(BASEX-200), eval(BASEY+200), 60, 35, 1) + PIN(eval(BASEX-200), eval(BASEY+100), 60, 35, 2) + PIN(eval(BASEX), eval(BASEY), 100, 81, m1) + PIN(eval(BASEX), eval(BASEY+400), 100, 81, m2) +)') + + +# --------------------------------------------------------------- +# definition for MTA-100 header, +# such as AMP 640456-x +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins +# +# 0.100" pin pitch +# 0.038" drill diameter +# 0.060" pad diameter +# Available with 2 through 15 pins +# +define(`PKG_MTA_100', +` + define(`PITCH', `100') + define(`NPINS', eval($4)) + define(`SILKW', `10') + define(`SILKXOFS', `75') + define(`SILKYOFS', `115') + define(`SILKX1', `-SILKXOFS') + define(`SILKX2', eval((NPINS-1)*PITCH + SILKXOFS)) + define(`SILKY1', `-SILKYOFS') + define(`SILKY2', `SILKYOFS') + define(`SILKY3', eval(SILKYOFS+2*SILKW)) + +Element(0x00 "$1" "$2" "$3" 0 140 0 150 0x00) +( + forloop(`i', 1, `$4', + `PIN(eval((i-1)*100), 0, 60, 38, `i') + ') + define(`X1',-78) + define(`X2', eval(`$4'*100-78)) + ElementLine(SILKX1 SILKY1 SILKX2 SILKY1 SILKW) + ElementLine(SILKX2 SILKY1 SILKX2 SILKY3 SILKW) + ElementLine(SILKX2 SILKY2 SILKX1 SILKY2 SILKW) + ElementLine(SILKX1 SILKY3 SILKX1 SILKY1 SILKW) + + ElementLine(SILKX2 SILKY3 SILKX1 SILKY3 SILKW) + + Mark(0 0) +)') + +# --------------------------------------------------------------- +# definition for MTA-156 header, +# such as AMP 640445-x +# 12/99 Larry Doolittle <LRDoolittle@lbl.gov> +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins +# +# base is pin 1 (although I don't claim to know which end is +# conventionally pin 1) +# 0.156 pin pitch +# 0.070 holes +# 0.078 end clearance +# 0.180 and 0.120 side clearance +# Available with 2 through 24 pins +# +define(`PKG_MTA_156', + ` +Element(0x00 "$1" "$2" "$3" 0 140 0 150 0x00) +( + forloop(`i', 1, `$4', + `PIN(eval((i-1)*156), 0, 100, 70, `i') + ') + define(`X1',-78) + define(`X2', eval(`$4'*156-78)) + ElementLine(X1 120 X2 120 10) + ElementLine(X2 120 X2 -180 10) + ElementLine(X2 -180 X1 -180 10) + ElementLine(X2 -80 X1 -80 10) + ElementLine(X1 -180 X1 120 10) +)') + +# --------------------------------------------------------------- +# definition for a vertical SMA connector, +# 6/00 Larry Doolittle <LRDoolittle@lbl.gov> +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins +# +# base is the center pin +# +define(`PKG_SMA_VERT', + `define(`BASEX', 0) + define(`BASEY', 0) +Element(0x00 "$1" "$2" "$3" BASEX eval(BASEY+150) 3 100 0x00) +( + define(`X1', eval(BASEX-160)) + define(`Y1', eval(BASEY-160)) + define(`X2', eval(BASEX+160)) + define(`Y2', eval(BASEY+160)) + ElementLine(X1 Y1 X2 Y1 10) + ElementLine(X2 Y1 X2 Y2 10) + ElementLine(X2 Y2 X1 Y2 10) + ElementLine(X1 Y2 X1 Y1 10) + PIN( BASEX , BASEY , 80, 30, 1) + PIN(eval(BASEX-100), eval(BASEY+100), 80, 30, 2) + PIN(eval(BASEX-100), eval(BASEY-100), 80, 30, 3) + PIN(eval(BASEX+100), eval(BASEY+100), 80, 30, 4) + PIN(eval(BASEX+100), eval(BASEY-100), 80, 30, 5) +)') + +# --------------------------------------------------------------- +# definition for a Molex high density connector, 53467/53645 +# Board-to-Board 0.635mm (0.25") Ptich Plug - SMT Dual Row, Vertical Stacking +# Reference: http://www.molex.com/product/micro/53467.html +# 4/01 Larry Doolittle <LRDoolittle@lbl.gov> +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins +# +# base is on the symmetry line, between pins 1 and 2 +# +define(`PKG_MOLEX_025', + `define(`PINPAIRS',eval($4/2)) +Element(0x00 "$1" "$2" "$3" 0 0 3 100 0x00) +( + forloop(`i', 1, PINPAIRS, + `define(`Y', eval(25*(i-1)) )' + `PAD( 54, Y, 111, Y, 14, eval(i*2-1))' + `PAD(-111, Y, -54, Y, 14, eval(i*2))' + ) + define(`ENDY',eval(25*(PINPAIRS-1))) + + # Keying is done with two sizes of alignment pins: 35 and 28 mils + Pin(0 -50 50 35 "M1" 0x01) + Pin(0 eval(ENDY+50) 43 28 "M2" 0x01) + + # ends of mounting pads are 71 and 169 mils from end pad centers + PAD(0, -110, 0, -130, 79, M3) + PAD(0, eval(ENDY+110), 0, eval(ENDY+130), 79, M4) + + define(`BOXY',eval(ENDY+150)) + ElementLine(-100 -150 50 -150 10) + ElementLine( 50 -150 100 -100 10) + ElementLine( 100 -100 100 BOXY 10) + ElementLine( 100 BOXY -100 BOXY 10) + ElementLine(-100 BOXY -100 -150 10) + + # Support for aggregate parts built from this base, like + # the nanoEngine below. + ifdef(`MOLEX_EXTRA', `MOLEX_EXTRA', ) +)') + +# --------------------------------------------------------------- +# definition for a Bright Star nanoEngine, StrongARM single board computer +# Reference: http://www.brightstar.com/arm/nanoman.pdf +# 4/01 Larry Doolittle <LRDoolittle@lbl.gov> +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +# base borrowed from the Molex connector +# +define(`PKG_NANOENGINE', + `define(`MOLEX_EXTRA', ` + ElementLine(-175 -215 -175 2185 15) + ElementLine(-175 2185 1225 2185 15) + ElementLine(1225 2185 1225 -215 15) + ElementLine(1225 -215 -175 -215 15) + Pin(525 -115 125 70 "M5" 0x01) + Pin(525 2085 125 70 "M6" 0x01) + ')' + `PKG_MOLEX_025($1, $2, $3, 160)' +) + +# ------------------------------------------------------------------- +# the definition of a through hole test point +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: drill diameter (mils) +# $5: pad diameter (mils) +# $6: silk diameter (mils) +# +define(`PKG_TP', + ` + define(`DRILL', `$4') + define(`PADDIA', `$5') + define(`SILK', eval($6/2)) + define(`SILKW', `10') +Element(0x00 "$1" "$2" "$3" -20 eval(-SILK - 60) 0 100 0x00) +( + Pin( 0 0 PADDIA DRILL "1" "1" 0x0) + ElementArc(0 0 SILK SILK 0 360 SILKW) + + # Mark at the common centroid + Mark(0 0) +)') + +define(`PKG_TP_38_60_90', `PKG_TP(`$1', `$2', `$3', 38, 60, 90)'); + +# Parameterized RJ45 modular jack footprint +# +# The parameterized part is the distance from the mark at pin 1 +# to the intended edge of the PCB, which combined with the length +# dimension of the populated part will determine how much of the connector +# protrudes off the board. +# We parameterize the footprint by abusing the value argument to the macro; +# with uEDA use the pcbvalue= attribute in the MCL. +# +# Based on the non-M4 RJ45 footprint by Levente Kovacs, modified +# to have the silk outline terminate in a butt end which is to serve as an +# end-stop in the placement, to be run into the edge of the PCB. +# That's the parameterized part. + +define(`PKG_RJ45_parameterized',` +Element["" "`$1'" "`$2'" "`$3'" 0 0 -2500 0 0 100 ""] +( + Pin[10000 35000 6000 2000 6000 2800 "" "8" "edge2"] + Pin[0 30000 6000 2000 6000 2800 "" "7" "edge2"] + Pin[10000 15000 6000 2000 6000 2800 "" "4" "edge2"] + Pin[0 10000 6000 2000 6000 2800 "" "3" "edge2"] + Pin[0 20000 6000 2000 6000 2800 "" "5" "edge2"] + Pin[0 0 6000 2000 6000 2800 "" "1" "square,edge2"] + Pin[10000 5000 6000 2000 6000 2800 "" "2" "edge2"] + Pin[10000 25000 6000 2000 6000 2800 "" "6" "edge2"] + Pin[-25000 -5000 12800 2000 12800 12800 "" "H1" "hole,edge2"] + Pin[-25000 40000 12800 2000 12800 12800 "" "H2" "hole,edge2"] + ElementLine [-eval($3 * 100) 49500 15000 49500 1000] + ElementLine [15000 49500 15000 -14500 1000] + ElementLine [-eval($3 * 100) -14500 15000 -14500 1000] +)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/cts.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,91 @@ +# -*- m4 -*- +# +# $Id: cts.inc,v 1.1 2007/02/19 05:28:27 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2004 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# +# CTS (http://www.ctscorp.com) Specific Footprints +# +# for the 742/3/4/5/6 resistors see +# http://www.ctscorp.com/components/Datasheets/CTSChipArrayDs.pdf + +# EXTRACT_BEGIN + +# COMMON_SMT_DIL_MM +# $4: number of pins +# $5: pad width (1/100 mm) +# $6: pad length (1/100 mm) +# $7: pad pitch (1/100 mm) +# $8: pad seperation for pads on opposite sides of +# the package (1/100 mm) +# $9: define to make the pins get numbered starting with the highest pin +# instead of pin 1. Needed for certain brain damaged packages like +# the Mini-Circuits KK81 + +# +## CTS 742C Series Chip Resistor Array +# + +define(`PKG_CTS_742C_04', `COMMON_SMT_DIL_MM(`$1',`$2',`$3' ,4,50,90,80,90)') +define(`PKG_CTS_742C_08', `COMMON_SMT_DIL_MM(`$1',`$2',`$3', 8,50,90,80,90)') +define(`PKG_CTS_742C_16', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',16,50,90,80,90)') + +# +## CTS 742C Series Chip Resistor Array +# + +define(`PKG_CTS_742X_08', `COMMON_SMT_DIL_MM(`$1',`$2',`$3', 8,50,90,80,90)') + +# +## CTS 743C Series Chip Resistor Array +# + +define(`PKG_CTS_743C_04', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',4,32000,47000,50000,28000)') +define(`PKG_CTS_743C_08', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',8,32000,47000,50000,28000)') + +# +## CTS 744C Series Chip Resistor Array +# + +define(`PKG_CTS_744C_04', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',4,32000,51000,50000,67000)') +define(`PKG_CTS_744C_08', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',8,32000,51000,50000,67000)') + +# +## CTS 745C Series Chip Resistor Array +# + +define(`PKG_CTS_745C_10', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',10,32000,51000,50000,67000)') + +# +# +## CTS 745X Series Chip Resistor Array +# + +define(`PKG_CTS_745X_10', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',10,32000,51000,50000,67000)') + +# +## CTS 746X Series Chip Resistor Array +# + +define(`PKG_CTS_746X_10', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',10,14000,32000,25000,28000)') + +# EXTRACT_END +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/dil.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,125 @@ +# -*- m4 -*- +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: dil.inc,v 1.2 2007/02/26 03:52:30 msokolov Exp $ +# +# DIL packages + +# ------------------------------------------------------------------- +# the definition of a dual-inline package N and similar types +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: package size (300, 600, 900 + 100 for socket space) +# $6: pin spacing +# $7: pad size +# $8: drill size +# +define(`PKG_DIL', + ` +# retain backwards compatibility to older versions of PKG_DIL +# which did not have $6,$7,$8 args + + ifelse("`$6'","", + `define(`PINSPACE', `100')' + , + `define(`PINSPACE', eval(`$6'))' + ) + ifelse("`$7'","", + `define(`PADSIZE', `60')' + , + `define(`PADSIZE', `$7')' + ) + ifelse("`$8'","", + `define(`DRILLSIZE', `28')' + , + `define(`DRILLSIZE', `$8')' + ) + define(`MAXY', eval(`$4' / 2 * PINSPACE)) + define(`MAXX', eval(`$5' + 100)) + define(`CENTERX', eval(MAXX / 2)) +Element(0x00 "$1" "$2" "$3" eval(CENTERX + 20) 100 3 100 0x00) +( + forloop(`i', 1, eval($4 / 2), + `PIN(50, eval((2*i-1) * PINSPACE/2), + eval(PADSIZE), eval(DRILLSIZE), i) + ') + forloop(`i', 1, eval($4 / 2), + `PIN(eval(MAXX -50), eval(MAXY - (2*i-1) * PINSPACE/2), + eval(PADSIZE), eval(DRILLSIZE), eval(i + $4/2)) + ') + ElementLine(0 0 0 MAXY 10) + ElementLine(0 MAXY MAXX MAXY 10) + ElementLine(MAXX MAXY MAXX 0 10) + ElementLine(0 0 eval(CENTERX - 50) 0 10) + ElementLine(eval(CENTERX + 50) 0 MAXX 0 10) + ElementArc(CENTERX 0 50 50 0 180 10) + Mark(50 50) +)') +define(`PKG_J', `PKG_DIL(`$1', `$2', `$3', `$4', `$5', 100, 60, 28)') +define(`PKG_JD', `PKG_DIL(`$1', `$2', `$3', `$4', `$5', 100, 60, 28)') +define(`PKG_JG', `PKG_DIL(`$1', `$2', `$3', `$4', `$5', 100, 60, 28)') +define(`PKG_N', `PKG_DIL(`$1', `$2', `$3', `$4', `$5', 100, 60, 28)') +define(`PKG_NT', `PKG_DIL(`$1', `$2', `$3', `$4', `$5', 100, 60, 28)') +define(`PKG_P', `PKG_DIL(`$1', `$2', `$3', `$4', `$5', 100, 60, 28)') +#shrink DIP +define(`PKG_NS', `PKG_DIL(`$1', `$2', `$3', `$4', `$5', 70, 55, 28)') + +# ------------------------------------------------------------------- +# the definition of a dual-inline package D and DW +# never used by circuits, just a short-cut for others +# width D==244, DW==419 +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: width +# +define(`COMMON_D_DW', + `define(`MAXY', eval(`$4' / 2 * 50)) + define(`MAXX', `$5') + define(`XLOW', `50') + define(`XHIGH', eval(MAXX - 50)) + define(`CENTERX', eval(MAXX / 2)) +Element(0x00 "$1" "$2" "$3" eval(CENTERX + 20) 50 3 100 0x00) +( + forloop(`i', 1, eval($4 / 2), + `PAD(0, eval(i * 50 -25), XLOW, eval(i * 50 -25), 20, i) + ') + forloop(`i', 1, eval($4 / 2), + `PAD(XHIGH, eval(MAXY - i * 50 +25), MAXX, eval(MAXY - i * 50 +25), 20, eval(i + $4/2)) + ') + ElementLine(XLOW 0 XLOW MAXY 10) + ElementLine(XLOW MAXY XHIGH MAXY 10) + ElementLine(XHIGH MAXY XHIGH 0 10) + ElementLine(XLOW 0 eval(CENTERX - 25) 0 10) + ElementLine(eval(CENTERX + 25) 0 XHIGH 0 10) + ElementArc(CENTERX 0 25 25 0 180 10) + Mark(25 25) +)') + +define(`PKG_D', `COMMON_D_DW(`$1', `$2', `$3', `$4', 244)') +define(`PKG_DW', `COMMON_D_DW(`$1', `$2', `$3', `$4', 419)') +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/dpr.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,99 @@ +# -*- m4 -*- +# $Id: dpr.inc,v 1.1 2007/03/11 02:36:19 msokolov Exp $ +# +# SMT dual position configuration resistors + +# based on COMMON_SMT_2PAD_MIL from smt.inc +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: length of component in mil +# $5: width of component in mil, also width of pad +# $6: percent scale factor for silk letters A & B +# $7: x offset from the centre of a pad to the UL corner of the following letter +# $8: y coordinate of the top of the letters (0 = centre of the footprint) +# +define(`PKG_DPR', + `define(`sizX', eval($4 * 100)) + define(`sizY', eval($5 * 100)) + define(`metalX', eval((sizX * 20) / 100)) + define(`addFRAME', eval(sizY / 5)) + define(`addTIN', eval(sizY / 5)) + define(`padX', eval(metalX + 2*addTIN)) + define(`padY', eval(sizY + 2*addTIN)) + define(`centerX', eval(sizX - metalX)) + define(`width', eval(centerX + padX/2 + addFRAME)) + define(`height', eval(sizY/2 + addFRAME + addTIN)) + define(`silkW', ifelse(eval(sizY >= 5000), 1, 1000, eval(sizY/5))) + # how much to grow the pads by for soldermask + define(`maskGrow', 300) + # clearance from planes + define(`clearance', 1000) +Element[0x00 "`$1'" "`$2'" "`$3'" 0 0 eval(width + 2000) 0 3 100 0x00] +( + # outline + ElementLine[-width -height -width height silkW] + ElementLine[-width height width height silkW] + ElementLine[width height width -height silkW] + ElementLine[width -height -width -height silkW] + + # pads + ifelse(eval(padX > padY), 1, + `Pad[eval((-2*centerX - padX + padY)/2) 0 + eval((-2*centerX + padX - padY)/2) 0 + padY eval(2*clearance) eval(padY + 2*maskGrow) "1" "1" 0x100] + Pad[eval((- padX + padY)/2) 0 + eval(( padX - padY)/2) 0 + padY eval(2*clearance) eval(padY + 2*maskGrow) "2" "2" 0x100] + Pad[eval(( 2*centerX - padX + padY)/2) 0 + eval(( 2*centerX + padX - padY)/2) 0 + padY eval(2*clearance) eval(padY + 2*maskGrow) "3" "3" 0x100] + ', + `Pad[-centerX eval((-padY+padX)/2) + -centerX eval((padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "1" "1" 0x100] + Pad[0 eval((-padY+padX)/2) 0 eval((padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "2" "2" 0x100] + Pad[centerX eval((-padY+padX)/2) + centerX eval((padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "3" "3" 0x100] + ') + + # silk letters A & B + define(`letterscale', $6) + define(`letterx', eval($7 * 100 - centerX)) + define(`lettery', eval($8 * 100)) + define(`letterW', 800) + DPR_letterA + define(`letterx', eval($7 * 100)) + DPR_letterB +)') + +# helper macros for the silk letters A & B +define(`DPR_ltrx',`eval(($1 * letterscale) + letterx)') +define(`DPR_ltry',`eval(($1 * letterscale) + lettery)') + +define(`DPR_letterA',` + ElementLine[DPR_ltrx(0) DPR_ltry(5) DPR_ltrx(0) DPR_ltry(40) letterW] + ElementLine[DPR_ltrx(0) DPR_ltry(5) DPR_ltrx(5) DPR_ltry(0) letterW] + ElementLine[DPR_ltrx(5) DPR_ltry(0) DPR_ltrx(20) DPR_ltry(0) letterW] + ElementLine[DPR_ltrx(20) DPR_ltry(0) DPR_ltrx(25) DPR_ltry(5) letterW] + ElementLine[DPR_ltrx(25) DPR_ltry(5) DPR_ltrx(25) DPR_ltry(40) letterW] + ElementLine[DPR_ltrx(0) DPR_ltry(20) DPR_ltrx(25) DPR_ltry(20) letterW] +') + +define(`DPR_letterB',` + ElementLine[DPR_ltrx(0) DPR_ltry(40) DPR_ltrx(20) DPR_ltry(40) letterW] + ElementLine[DPR_ltrx(20) DPR_ltry(40) DPR_ltrx(25) DPR_ltry(35) letterW] + ElementLine[DPR_ltrx(25) DPR_ltry(25) DPR_ltrx(25) DPR_ltry(35) letterW] + ElementLine[DPR_ltrx(20) DPR_ltry(20) DPR_ltrx(25) DPR_ltry(25) letterW] + ElementLine[DPR_ltrx(5) DPR_ltry(20) DPR_ltrx(20) DPR_ltry(20) letterW] + ElementLine[DPR_ltrx(5) DPR_ltry(0) DPR_ltrx(5) DPR_ltry(40) letterW] + ElementLine[DPR_ltrx(0) DPR_ltry(0) DPR_ltrx(20) DPR_ltry(0) letterW] + ElementLine[DPR_ltrx(20) DPR_ltry(0) DPR_ltrx(25) DPR_ltry(5) letterW] + ElementLine[DPR_ltrx(25) DPR_ltry(5) DPR_ltrx(25) DPR_ltry(15) letterW] + ElementLine[DPR_ltrx(20) DPR_ltry(20) DPR_ltrx(25) DPR_ltry(15) letterW] +') + +define(`PKG_DPR0805', `PKG_DPR(`$1',`$2',`$3', 80, 50, 80, 22, -16)'); +define(`PKG_DPR1206', `PKG_DPR(`$1',`$2',`$3', 120, 60, 100, 36, -20)');
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/geda.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,1105 @@ +# -*- m4 -*- +# $Id: geda.inc,v 1.6 2009/12/26 22:53:42 msokolov Exp $ +# +# gEDA compatible footprint names +# +# the real component definitions are in the *.inc files +# +# revisions: +# Oct 10 2002 - Egil Kvaleberg <egil@kvaleberg.no> +# Initial version +# + +# +## Dual in-line package, narrow (300 mil) +# DIP6 .. DIP64, DIP24N, DIP28N +# +define(`PKG_DIP6', `PKG_N(`$1', `$2', `$3', 6, 300)'); +define(`PKG_DIP8', `PKG_N(`$1', `$2', `$3', 8, 300)'); +define(`PKG_DIP14', `PKG_N(`$1', `$2', `$3', 14, 300)'); +define(`PKG_DIP16', `PKG_N(`$1', `$2', `$3', 16, 300)'); +define(`PKG_DIP18', `PKG_N(`$1', `$2', `$3', 18, 300)'); +define(`PKG_DIP20', `PKG_N(`$1', `$2', `$3', 20, 300)'); +define(`PKG_DIP22', `PKG_N(`$1', `$2', `$3', 22, 300)'); +define(`PKG_DIP24N', `PKG_N(`$1', `$2', `$3', 24, 300)'); +define(`PKG_DIP28N', `PKG_N(`$1', `$2', `$3', 28, 300)'); +## Dual in-line package, medium wide (400 mil) +define(`PKG_DIP8M', `PKG_N(`$1', `$2', `$3', 8, 400)'); +define(`PKG_DIP14M', `PKG_N(`$1', `$2', `$3', 14, 400)'); +define(`PKG_DIP16M', `PKG_N(`$1', `$2', `$3', 16, 400)'); +define(`PKG_DIP18M', `PKG_N(`$1', `$2', `$3', 18, 400)'); +define(`PKG_DIP20M', `PKG_N(`$1', `$2', `$3', 20, 400)'); +define(`PKG_DIP22M', `PKG_N(`$1', `$2', `$3', 22, 400)'); +define(`PKG_DIP24M', `PKG_N(`$1', `$2', `$3', 24, 400)'); +define(`PKG_DIP28M', `PKG_N(`$1', `$2', `$3', 28, 400)'); +## Dual in-line package, wide (600 mil) +define(`PKG_DIP24', `PKG_N(`$1', `$2', `$3', 24, 600)'); +define(`PKG_DIP28', `PKG_N(`$1', `$2', `$3', 28, 600)'); +define(`PKG_DIP32', `PKG_N(`$1', `$2', `$3', 32, 600)'); +define(`PKG_DIP36', `PKG_N(`$1', `$2', `$3', 36, 600)'); +define(`PKG_DIP40', `PKG_N(`$1', `$2', `$3', 40, 600)'); +define(`PKG_DIP42', `PKG_N(`$1', `$2', `$3', 42, 600)'); +define(`PKG_DIP44', `PKG_N(`$1', `$2', `$3', 44, 600)'); +define(`PKG_DIP48', `PKG_N(`$1', `$2', `$3', 48, 600)'); +## Dual in-line package, wide (900 mil) +define(`PKG_DIP64', `PKG_N(`$1', `$2', `$3', 64, 900)'); + +# +## Shrink dual in-line package, wide (400 mil) +# +define(`PKG_SDIP18', `PKG_NS(`$1', `$2', `$3', 18, 300)'); +define(`PKG_SDIP22', `PKG_NS(`$1', `$2', `$3', 22, 300)'); +define(`PKG_SDIP24', `PKG_NS(`$1', `$2', `$3', 24, 300)'); +# +## Shrink dual in-line package, wide (400 mil) +define(`PKG_SDIP30', `PKG_NS(`$1', `$2', `$3', 30, 400)'); +define(`PKG_SDIP32', `PKG_NS(`$1', `$2', `$3', 32, 400)'); +# +## Shrink dual in-line package, wide (600 mil) +define(`PKG_SDIP42', `PKG_NS(`$1', `$2', `$3', 42, 600)'); + +# +## Single in line package +# SIP1 .. SIP13 +# +define(`PKG_SIP1', `PKG_CSIL(`$1', `$2', `$3', 1)'); +define(`PKG_SIP2', `PKG_CSIL(`$1', `$2', `$3', 2)'); +define(`PKG_SIP3', `PKG_CSIL(`$1', `$2', `$3', 3)'); +define(`PKG_SIP4', `PKG_CSIL(`$1', `$2', `$3', 4)'); +define(`PKG_SIP5', `PKG_CSIL(`$1', `$2', `$3', 5)'); +define(`PKG_SIP6', `PKG_CSIL(`$1', `$2', `$3', 6)'); +define(`PKG_SIP7', `PKG_CSIL(`$1', `$2', `$3', 7)'); +define(`PKG_SIP8', `PKG_CSIL(`$1', `$2', `$3', 8)'); +define(`PKG_SIP9', `PKG_CSIL(`$1', `$2', `$3', 9)'); +define(`PKG_SIP10', `PKG_CSIL(`$1', `$2', `$3', 10)'); +define(`PKG_SIP11', `PKG_CSIL(`$1', `$2', `$3', 11)'); +define(`PKG_SIP12', `PKG_CSIL(`$1', `$2', `$3', 12)'); +define(`PKG_SIP13', `PKG_CSIL(`$1', `$2', `$3', 13)'); + +# +## Ultra (Micro?) Small outline package +# +# pins, width (1/100mil), pitch (1/100 mil) +define(`PKG_US8', `PKG_US( `$1', `$2', `$3', 8)'); +define(`PKG_US14', `PKG_US( `$1', `$2', `$3', 14)'); +define(`PKG_US16', `PKG_US( `$1', `$2', `$3', 16)'); + +# +## Small outline package, narrow (150mil) +# aka SOP8, aka S8 +# +# COMMON_SMT_DIL_{MIL,MM} +# $4: number of pins +# $5: pad width (1/1000 mil or 1/100 mm) +# $6: pad length (1/1000 mil or 1/100 mm) +# $7: pad pitch (1/1000 mil 1/100 mm) +# $8: pad seperation for pads on opposite sides of +# the package (1/1000 mil or 1/100 mm) +# $9: define to make the pins get numbered starting with the highest pin +# instead of pin 1. Needed for certain brain damaged packages like +# the Mini-Circuits KK81 + +# dimensions from http://landpatterns.ipc.org/ +define(`PKG_SO8', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 8, 20000, 85000, 50000, 120000)') +define(`PKG_SO14', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 14, 20000, 85000, 50000, 120000)') +define(`PKG_SO16', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 16, 20000, 85000, 50000, 120000)') +define(`PKG_SO18N', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 18, 20000, 85000, 50000, 120000)') +define(`PKG_SO20N', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 20, 20000, 85000, 50000, 120000)') + +## Small outline package, medium (200mil) +# aka 8S2 +define(`PKG_SO8M', `PKG_SO( `$1', `$2', `$3', 8, 330, 5000)'); +define(`PKG_SO18M', `PKG_SO( `$1', `$2', `$3', 18, 330, 5000)'); +define(`PKG_SO20M', `PKG_SO( `$1', `$2', `$3', 20, 330, 5000)'); +define(`PKG_SO22M', `PKG_SO( `$1', `$2', `$3', 22, 330, 5000)'); +define(`PKG_SO24M', `PKG_SO( `$1', `$2', `$3', 24, 330, 5000)'); + +## Small outline package, wide (300mil) +# dimensions from http://landpatterns.ipc.org/ +define(`PKG_SO8W', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 8, 20000, 80000, 50000, 280000)') +define(`PKG_SO14W', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 14, 20000, 80000, 50000, 280000)') +define(`PKG_SO16W', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 16, 20000, 80000, 50000, 280000)') +define(`PKG_SO18W', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 18, 20000, 80000, 50000, 280000)') +define(`PKG_SO20W', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 20, 20000, 80000, 50000, 280000)') +define(`PKG_SO24W', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 24, 20000, 80000, 50000, 280000)') +define(`PKG_SO28', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 28, 20000, 80000, 50000, 280000)') +define(`PKG_SO32', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3', 32, 20000, 80000, 50000, 280000)') + +## Small outline package, wider (325mil) +define(`PKG_SO28W', `PKG_SO( `$1', `$2', `$3', 28, 474, 5000)'); + +## Small outline package, wider (450mil) +define(`PKG_SO32W', `PKG_SO( `$1', `$2', `$3', 32, 567, 5000)'); + +## Small outline package, wide (525mil) +define(`PKG_SO44', `PKG_SO( `$1', `$2', `$3', 44, 634, 5000)'); + + + +# NOTE: There is also SOJ20,28,32,40,42 +# 0.300" size, 28,32 pin (MO-088, MO-077 respectively) +# 0.400" size, 28,32,36 pin (MO-061) +# +# +# from http://landpatterns.ipc.org/ +# 14-28 pin 0.300" - pitch = 1.27 mm, pad is 0.6 x 2.2, gap is 5 +# 14-28 pin 0.350" - pitch = 1.27 mm, pad is 0.6 x 2.2, gap is 6.2 +# 14-28 pin 0.400" - pitch = 1.27 mm, pad is 0.6 x 2.2, gap is 7.4 +# 14-28 pin 0.450" - pitch = 1.27 mm, pad is 0.6 x 2.2, gap is 8.8 +# +# Cypress (www.cypress.com) has 20, 24, 28, 32 in the 0.3" and +# 28, 32, 36, 44 in the 0.4" + +## Small outline J-leaded package (300 mil) +define(`PKG_SOJ14_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',14,23622,86614,50000,196850)'); +define(`PKG_SOJ16_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',16,23622,86614,50000,196850)'); +define(`PKG_SOJ18_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',18,23622,86614,50000,196850)'); +define(`PKG_SOJ20_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',20,23622,86614,50000,196850)'); +define(`PKG_SOJ22_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',22,23622,86614,50000,196850)'); +define(`PKG_SOJ24_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',24,23622,86614,50000,196850)'); +define(`PKG_SOJ26_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',26,23622,86614,50000,196850)'); +define(`PKG_SOJ28_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',28,23622,86614,50000,196850)'); +define(`PKG_SOJ30_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',30,23622,86614,50000,196850)'); +define(`PKG_SOJ32_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',32,23622,86614,50000,196850)'); +define(`PKG_SOJ34_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',34,23622,86614,50000,196850)'); +define(`PKG_SOJ36_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',36,23622,86614,50000,196850)'); +define(`PKG_SOJ38_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',38,23622,86614,50000,196850)'); +define(`PKG_SOJ40_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',40,23622,86614,50000,196850)'); +define(`PKG_SOJ42_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',42,23622,86614,50000,196850)'); +define(`PKG_SOJ44_300', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',44,23622,86614,50000,196850)'); + +## Small outline J-leaded package (350 mil) +define(`PKG_SOJ14_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',14,23622,86614,50000,244094)'); +define(`PKG_SOJ16_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',16,23622,86614,50000,244094)'); +define(`PKG_SOJ18_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',18,23622,86614,50000,244094)'); +define(`PKG_SOJ20_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',20,23622,86614,50000,244094)'); +define(`PKG_SOJ22_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',22,23622,86614,50000,244094)'); +define(`PKG_SOJ24_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',24,23622,86614,50000,244094)'); +define(`PKG_SOJ26_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',26,23622,86614,50000,244094)'); +define(`PKG_SOJ28_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',28,23622,86614,50000,244094)'); +define(`PKG_SOJ30_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',30,23622,86614,50000,244094)'); +define(`PKG_SOJ32_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',32,23622,86614,50000,244094)'); +define(`PKG_SOJ34_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',34,23622,86614,50000,244094)'); +define(`PKG_SOJ36_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',36,23622,86614,50000,244094)'); +define(`PKG_SOJ38_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',38,23622,86614,50000,244094)'); +define(`PKG_SOJ40_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',40,23622,86614,50000,244094)'); +define(`PKG_SOJ42_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',42,23622,86614,50000,244094)'); +define(`PKG_SOJ44_350', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',44,23622,86614,50000,244094)'); + +## Small outline J-leaded package (400 mil) +define(`PKG_SOJ14_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',14,23622,86614,50000,291339)'); +define(`PKG_SOJ16_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',16,23622,86614,50000,291339)'); +define(`PKG_SOJ18_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',18,23622,86614,50000,291339)'); +define(`PKG_SOJ20_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',20,23622,86614,50000,291339)'); +define(`PKG_SOJ22_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',22,23622,86614,50000,291339)'); +define(`PKG_SOJ24_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',24,23622,86614,50000,291339)'); +define(`PKG_SOJ26_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',26,23622,86614,50000,291339)'); +define(`PKG_SOJ28_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',28,23622,86614,50000,291339)'); +define(`PKG_SOJ30_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',30,23622,86614,50000,291339)'); +define(`PKG_SOJ32_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',32,23622,86614,50000,291339)'); +define(`PKG_SOJ34_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',34,23622,86614,50000,291339)'); +define(`PKG_SOJ36_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',36,23622,86614,50000,291339)'); +define(`PKG_SOJ38_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',38,23622,86614,50000,291339)'); +define(`PKG_SOJ40_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',40,23622,86614,50000,291339)'); +define(`PKG_SOJ42_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',42,23622,86614,50000,291339)'); +define(`PKG_SOJ44_400', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',44,23622,86614,50000,291339)'); + +## Small outline J-leaded package (450 mil) +define(`PKG_SOJ14_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',14,23622,86614,50000,346457)'); +define(`PKG_SOJ16_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',16,23622,86614,50000,346457)'); +define(`PKG_SOJ18_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',18,23622,86614,50000,346457)'); +define(`PKG_SOJ20_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',20,23622,86614,50000,346457)'); +define(`PKG_SOJ22_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',22,23622,86614,50000,346457)'); +define(`PKG_SOJ24_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',24,23622,86614,50000,346457)'); +define(`PKG_SOJ26_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',26,23622,86614,50000,346457)'); +define(`PKG_SOJ28_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',28,23622,86614,50000,346457)'); +define(`PKG_SOJ30_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',30,23622,86614,50000,346457)'); +define(`PKG_SOJ32_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',32,23622,86614,50000,346457)'); +define(`PKG_SOJ34_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',34,23622,86614,50000,346457)'); +define(`PKG_SOJ36_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',36,23622,86614,50000,346457)'); +define(`PKG_SOJ38_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',38,23622,86614,50000,346457)'); +define(`PKG_SOJ40_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',40,23622,86614,50000,346457)'); +define(`PKG_SOJ42_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',42,23622,86614,50000,346457)'); +define(`PKG_SOJ44_450', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',44,23622,86614,50000,346457)'); + + +# +# NOTE: +# Shrink small outline SSOP is a full confusion of +# pitch 25.00 mil, 0.65mm, 0.8mm +# widths 244, 260, 311, 323 etc +# there are really too many variants, the ones listed here are +# fairly industry standard +# +## Shrink small outline package, .65mm, narrow +define(`PKG_SSOP8', `PKG_SSO( `$1', `$2', `$3', 8, 323, 2559)'); +define(`PKG_SSOP14', `PKG_SSO( `$1', `$2', `$3', 14, 323, 2559)'); +define(`PKG_SSOP16', `PKG_SSO( `$1', `$2', `$3', 16, 244, 2559)'); +define(`PKG_SSOP20', `PKG_SSO( `$1', `$2', `$3', 20, 260, 2559)'); +define(`PKG_SSOP24', `PKG_SSO( `$1', `$2', `$3', 24, 323, 2559)'); +define(`PKG_SSOP28', `PKG_SSO( `$1', `$2', `$3', 28, 323, 2559)'); + +# +## Shrink small outline package, .65mm, wide +#define(`PKG_SSOP16W', `PKG_SSO( `$1', `$2', `$3', 16, 420, 2559)'); +#define(`PKG_SSOP20W', `PKG_SSO( `$1', `$2', `$3', 20, 420, 2559)'); +#define(`PKG_SSOP28W', `PKG_SSO( `$1', `$2', `$3', 28, 420, 2559)'); +#define(`PKG_SSOP30W', `PKG_SSO( `$1', `$2', `$3', 30, 420, 2559)'); +#define(`PKG_SSOP32W', `PKG_SSO( `$1', `$2', `$3', 32, 420, 2559)'); +#define(`PKG_SSOP36W', `PKG_SSO( `$1', `$2', `$3', 36, 420, 2559)'); + +# +## Shrink small outline package, 25mil, wide +define(`PKG_SSOP48W', `PKG_SSO( `$1', `$2', `$3', 48, 420, 2500)'); +define(`PKG_SSOP56W', `PKG_SSO( `$1', `$2', `$3', 56, 420, 2500)'); + +# +## Shrink small outline package, .80mm, wider +define(`PKG_SSOP64W', `PKG_SSO( `$1', `$2', `$3', 64, 545, 3150)'); + +## Shrink small outline package, .65mm, narrow +# BUG:(`PKG_MSOP8', `PKG_SSO( `$1', `$2', `$3', 8, 323, 2559)'); +# +## Mini small outline package, .65mm +define(`PKG_MSOP8', `PKG_SSO( `$1', `$2', `$3', 8, 199, 2559)'); +## Mini small outline package, .5mm +define(`PKG_MSOP10', `PKG_TSOP( `$1', `$2', `$3', 8, 199, 1969)'); + +## Quarter size small outline package +define(`PKG_QSOP16', `PKG_SSO( `$1', `$2', `$3', 16, 244, 2500)'); +define(`PKG_QSOP20', `PKG_SSO( `$1', `$2', `$3', 20, 244, 2500)'); +define(`PKG_QSOP24', `PKG_SSO( `$1', `$2', `$3', 24, 244, 2500)'); +define(`PKG_QSOP28', `PKG_SSO( `$1', `$2', `$3', 28, 244, 2500)'); + +# +## Thin small outline package +# BUG: TSOP in 26(x2),28(x2),32,44(x2),48,50(x2),54,66,70(x2),86 +# +define(`PKG_TSOP28', `PKG_TSOP( `$1', `$2', `$3', 28, 535, 2165)'); +define(`PKG_TSOP32A', `PKG_TSOP( `$1', `$2', `$3', 32, 795, 2000)'); +define(`PKG_TSOP32B', `PKG_TSOP( `$1', `$2', `$3', 32, 559, 2000)'); + +## Thin shrink small outline package +# BUG: TSSOP 14, 20, 28 are all 4.4mm +define(`PKG_TSSOP8', `PKG_TSSOP( `$1', `$2', `$3', 8, 260, 2600)'); + +define(`PKG_TSSOP48', `PKG_TSOP( `$1', `$2', `$3', 48, 319, 2000)'); +define(`PKG_TSSOP56', `PKG_TSOP( `$1', `$2', `$3', 56, 319, 2000)'); +define(`PKG_TSSOP64', `PKG_TSOP( `$1', `$2', `$3', 64, 319, 2000)'); + +# +## Plastic leadless chip carrier +# PLCC44 .. PLCC84 +# +# BUG: similar: +# QFJ 18,20,22,28,32,44,68,84 +# +define(`PKG_PLCC20', `PKG_PLCC(`$1', `$2', `$3', 20, 150)'); +define(`PKG_PLCC28', `PKG_PLCC(`$1', `$2', `$3', 28, 150)'); +define(`PKG_PLCC32', `PKG_PLCC(`$1', `$2', `$3', 32, 150)'); +define(`PKG_PLCC44', `PKG_PLCC(`$1', `$2', `$3', 44, 150)'); +define(`PKG_PLCC52', `PKG_PLCC(`$1', `$2', `$3', 52, 150)'); +define(`PKG_PLCC68', `PKG_PLCC(`$1', `$2', `$3', 68, 150)'); +define(`PKG_PLCC84', `PKG_PLCC(`$1', `$2', `$3', 84, 150)'); + +# +## Plastic leadless chip carrier with pin socket +# PLCC44X .. PLCC84X +# +define(`PKG_PLCC20X', `PKG_PLCC_SOCKET(`$1', `$2', `$3', 20, 150)'); +define(`PKG_PLCC28X', `PKG_PLCC_SOCKET(`$1', `$2', `$3', 28, 150)'); +define(`PKG_PLCC32X', `PKG_PLCC_SOCKET(`$1', `$2', `$3', 32, 150)'); +define(`PKG_PLCC44X', `PKG_PLCC_SOCKET(`$1', `$2', `$3', 44, 150)'); +define(`PKG_PLCC52X', `PKG_PLCC_SOCKET(`$1', `$2', `$3', 52, 150)'); +define(`PKG_PLCC68X', `PKG_PLCC_SOCKET(`$1', `$2', `$3', 68, 150)'); +define(`PKG_PLCC84X', `PKG_PLCC_SOCKET(`$1', `$2', `$3', 84, 150)'); + +## Square Quad Flat Nolead (QFN) package +# + +# 4x4 mm +define(`PKG_QFN12_4', `PKG_QFN_80(`$1',`$2',`$3', `12', `4', `0')') +define(`PKG_TQFN12_4', `PKG_QFN_80(`$1',`$2',`$3', `12', `4', `0')') +define(`PKG_QFN12_4_EP', `PKG_QFN_80(`$1',`$2',`$3', `12', `4', `210')') +define(`PKG_TQFN12_4_EP', `PKG_QFN_80(`$1',`$2',`$3', `12', `4', `210')') + +define(`PKG_QFN16_4', `PKG_QFN_65(`$1',`$2',`$3', `16', `4', `0')') +define(`PKG_TQFN16_4', `PKG_QFN_65(`$1',`$2',`$3', `16', `4', `0')') +define(`PKG_QFN16_4_EP', `PKG_QFN_65(`$1',`$2',`$3', `16', `4', `210')') +define(`PKG_TQFN16_4_EP', `PKG_QFN_65(`$1',`$2',`$3', `16', `4', `210')') + +define(`PKG_QFN20_4', `PKG_QFN_50(`$1',`$2',`$3', `20', `4', `0')') +define(`PKG_TQFN20_4', `PKG_QFN_50(`$1',`$2',`$3', `20', `4', `0')') +define(`PKG_QFN20_4_EP', `PKG_QFN_50(`$1',`$2',`$3', `20', `4', `210')') +define(`PKG_TQFN20_4_EP', `PKG_QFN_50(`$1',`$2',`$3', `20', `4', `210')') + +define(`PKG_QFN24_4', `PKG_QFN_50S(`$1',`$2',`$3', `24', `4', `0')') +define(`PKG_TQFN24_4', `PKG_QFN_50S(`$1',`$2',`$3', `24', `4', `0')') +define(`PKG_QFN24_4_EP', `PKG_QFN_50S(`$1',`$2',`$3', `24', `4', `210')') +define(`PKG_TQFN24_4_EP', `PKG_QFN_50S(`$1',`$2',`$3', `24', `4', `260')') + +# 5x5 mm +define(`PKG_QFN16_5', `PKG_QFN_80(`$1',`$2',`$3', `16', `5', `0')') +define(`PKG_TQFN16_5', `PKG_QFN_80(`$1',`$2',`$3', `16', `5', `0')') +define(`PKG_QFN16_5_EP', `PKG_QFN_80(`$1',`$2',`$3', `16', `5', `310')') +define(`PKG_TQFN16_5_EP', `PKG_QFN_80(`$1',`$2',`$3', `16', `5', `310')') + +define(`PKG_QFN20_5', `PKG_QFN_65(`$1',`$2',`$3', `20', `5', `0')') +define(`PKG_TQFN20_5', `PKG_QFN_65(`$1',`$2',`$3', `20', `5', `0')') +define(`PKG_QFN20_5_EP', `PKG_QFN_65(`$1',`$2',`$3', `20', `5', `310')') +define(`PKG_TQFN20_5_EP', `PKG_QFN_65(`$1',`$2',`$3', `20', `5', `310')') + +define(`PKG_QFN28_5', `PKG_QFN_50(`$1',`$2',`$3', `28', `5', `0')') +define(`PKG_TQFN28_5', `PKG_QFN_50(`$1',`$2',`$3', `28', `5', `0')') +define(`PKG_QFN28_5_EP', `PKG_QFN_50(`$1',`$2',`$3', `28', `5', `310')') +define(`PKG_TQFN28_5_EP', `PKG_QFN_50(`$1',`$2',`$3', `28', `5', `325')') + +define(`PKG_QFN32_5', `PKG_QFN_50S(`$1',`$2',`$3', `32', `5', `0')') +define(`PKG_TQFN32_5', `PKG_QFN_50S(`$1',`$2',`$3', `32', `5', `0')') +define(`PKG_QFN32_5_EP', `PKG_QFN_50S(`$1',`$2',`$3', `32', `5', `310')') +define(`PKG_TQFN32_5_EP', `PKG_QFN_50S(`$1',`$2',`$3', `32', `5', `310')') + +# 6x6 mm +define(`PKG_QFN36_6', `PKG_QFN_50(`$1',`$2',`$3', `36', `6', `0')') +define(`PKG_TQFN36_6', `PKG_QFN_50(`$1',`$2',`$3', `36', `6', `0')') +define(`PKG_QFN36_6_EP', `PKG_QFN_50(`$1',`$2',`$3', `36', `6', `370')') +define(`PKG_TQFN36_6_EP', `PKG_QFN_50(`$1',`$2',`$3', `36', `6', `370')') + +define(`PKG_QFN40_6', `PKG_QFN_50S(`$1',`$2',`$3', `40', `6', `0')') +define(`PKG_TQFN40_6', `PKG_QFN_50S(`$1',`$2',`$3', `40', `6', `0')') +define(`PKG_QFN40_6_EP', `PKG_QFN_50S(`$1',`$2',`$3', `40', `6', `410')') +define(`PKG_TQFN40_6_EP', `PKG_QFN_50S(`$1',`$2',`$3', `40', `6', `410')') + +# 7x7 mm +define(`PKG_QFN32_7', `PKG_QFN_65(`$1',`$2',`$3', `32', `7', `0')') +define(`PKG_TQFN32_7', `PKG_QFN_65(`$1',`$2',`$3', `32', `7', `0')') +define(`PKG_QFN32_7_EP', `PKG_QFN_65(`$1',`$2',`$3', `32', `7', `470')') +define(`PKG_TQFN32_7_EP', `PKG_QFN_65(`$1',`$2',`$3', `32', `7', `470')') + +define(`PKG_QFN44_7', `PKG_QFN_50(`$1',`$2',`$3', `44', `7', `0')') +define(`PKG_TQFN44_7', `PKG_QFN_50(`$1',`$2',`$3', `44', `7', `0')') +define(`PKG_QFN44_7_EP', `PKG_QFN_50(`$1',`$2',`$3', `44', `7', `470')') +define(`PKG_TQFN44_7_EP', `PKG_QFN_50(`$1',`$2',`$3', `44', `7', `470')') + +define(`PKG_QFN48_7', `PKG_QFN_50S(`$1',`$2',`$3', `48', `7', `0')') +define(`PKG_TQFN48_7', `PKG_QFN_50S(`$1',`$2',`$3', `48', `7', `0')') +define(`PKG_QFN48_7_EP', `PKG_QFN_50S(`$1',`$2',`$3', `48', `7', `560')') +define(`PKG_TQFN48_7_EP', `PKG_QFN_50S(`$1',`$2',`$3', `48', `7', `560')') + +# 8x8 mm +define(`PKG_QFN56_8', `PKG_QFN_50S(`$1',`$2',`$3', `56', `8', `0')') +define(`PKG_TQFN56_8', `PKG_QFN_50S(`$1',`$2',`$3', `56', `8', `0')') +define(`PKG_QFN56_8_EP', `PKG_QFN_50S(`$1',`$2',`$3', `56', `8', `665')') +define(`PKG_TQFN56_8_EP', `PKG_QFN_50S(`$1',`$2',`$3', `56', `8', `665')') + +# 10x10 mm +define(`PKG_QFN68_10', `PKG_QFN_50(`$1',`$2',`$3', `68', `10', `0')') +define(`PKG_TQFN68_10', `PKG_QFN_50(`$1',`$2',`$3', `68', `10', `0')') +define(`PKG_QFN68_10_EP', `PKG_QFN_50(`$1',`$2',`$3', `68', `10', `770')') +define(`PKG_TQFN68_10_EP', `PKG_QFN_50(`$1',`$2',`$3', `68', `10', `770')') + +# +## Square Quad-side flat pack +# QFP 32,44,56,64,80,100,128,160,208,240,272,304 +# LQFP 144,176,208 +# TQFP 44,48,64,80,120 + +define(`PKG_LQFP24_4', `PKG_LQFP_50(`$1',`$2',`$3', `24', `4')'); +define(`PKG_LQFP32_5', `PKG_LQFP_50(`$1',`$2',`$3', `32', `5')'); +define(`PKG_LQFP32_7', `PKG_LQFP_80(`$1',`$2',`$3', `32', `7')'); +define(`PKG_LQFP44_10', `PKG_LQFP_80(`$1',`$2',`$3', `44',`10')'); +define(`PKG_LQFP48_7', `PKG_LQFP_50(`$1',`$2',`$3', `48', `7')'); +define(`PKG_LQFP48_12', `PKG_LQFP_80(`$1',`$2',`$3', `48',`12')'); +define(`PKG_LQFP52_10', `PKG_LQFP_65(`$1',`$2',`$3', `52',`10')'); +define(`PKG_LQFP64_7', `PKG_LQFP_40(`$1',`$2',`$3', `64', `7')'); +define(`PKG_LQFP64_10', `PKG_LQFP_50(`$1',`$2',`$3', `64',`10')'); +define(`PKG_LQFP64_14', `PKG_LQFP_80(`$1',`$2',`$3', `64',`14')'); +define(`PKG_LQFP72_10', `PKG_LQFP_50(`$1',`$2',`$3', `72',`10')'); +define(`PKG_LQFP80_12', `PKG_LQFP_50(`$1',`$2',`$3', `80',`12')'); +define(`PKG_LQFP80_14', `PKG_LQFP_65(`$1',`$2',`$3', `80',`14')'); +define(`PKG_LQFP100_10', `PKG_LQFP_40(`$1',`$2',`$3',`100',`10')'); +define(`PKG_LQFP100_14', `PKG_LQFP_50(`$1',`$2',`$3',`100',`14')'); +define(`PKG_LQFP112_20', `PKG_LQFP_65(`$1',`$2',`$3',`112',`20')'); +define(`PKG_LQFP120_16', `PKG_LQFP_50(`$1',`$2',`$3',`120',`16')'); +define(`PKG_LQFP128_14', `PKG_LQFP_40(`$1',`$2',`$3',`128',`14')'); +define(`PKG_LQFP144_20', `PKG_LQFP_50(`$1',`$2',`$3',`144',`20')'); +define(`PKG_LQFP160_24', `PKG_LQFP_50(`$1',`$2',`$3',`160',`24')'); +define(`PKG_LQFP176_24', `PKG_LQFP_50(`$1',`$2',`$3',`176',`24')'); + +define(`PKG_QFP32_7', `PKG_QFP_80(`$1',`$2',`$3', `32', `7')'); +define(`PKG_QFP44_10', `PKG_QFP_80(`$1',`$2',`$3', `44',`10')'); +define(`PKG_QFP52_10', `PKG_QFP_65(`$1',`$2',`$3', `52',`10')'); +define(`PKG_QFP64_14', `PKG_QFP_80(`$1',`$2',`$3', `64',`14')'); +define(`PKG_QFP80_14', `PKG_QFP_65(`$1',`$2',`$3', `80',`14')'); +define(`PKG_QFP100_14', `PKG_QFP_50(`$1',`$2',`$3',`100',`14')'); +define(`PKG_QFP120_28', `PKG_QFP_80(`$1',`$2',`$3',`120',`28')'); +define(`PKG_QFP128_28', `PKG_QFP_80(`$1',`$2',`$3',`128',`28')'); +define(`PKG_QFP144_28', `PKG_QFP_65(`$1',`$2',`$3',`144',`28')'); +define(`PKG_QFP160_28', `PKG_QFP_65(`$1',`$2',`$3',`160',`28')'); +define(`PKG_QFP208_28', `PKG_QFP_50(`$1',`$2',`$3',`208',`28')'); +define(`PKG_QFP160_28', `PKG_QFP_65(`$1',`$2',`$3',`160',`28')'); +define(`PKG_QFP240_32', `PKG_QFP_50(`$1',`$2',`$3',`240',`32')'); +define(`PKG_QFP304_40', `PKG_QFP_50(`$1',`$2',`$3',`304',`40')'); + +define(`PKG_TQFP32_7', `PKG_QFP_80(`$1',`$2',`$3', `32', `7')'); +define(`PKG_TQFP44_10', `PKG_QFP_80(`$1',`$2',`$3', `44',`10')'); +define(`PKG_TQFP52_10', `PKG_QFP_65(`$1',`$2',`$3', `52',`10')'); +define(`PKG_TQFP64_14', `PKG_QFP_80(`$1',`$2',`$3', `64',`14')'); +define(`PKG_TQFP80_14', `PKG_QFP_65(`$1',`$2',`$3', `80',`14')'); +define(`PKG_TQFP100_14', `PKG_QFP_50(`$1',`$2',`$3',`100',`14')'); +define(`PKG_TQFP120_28', `PKG_QFP_80(`$1',`$2',`$3',`120',`28')'); +define(`PKG_TQFP128_28', `PKG_QFP_80(`$1',`$2',`$3',`128',`28')'); +define(`PKG_TQFP144_28', `PKG_QFP_65(`$1',`$2',`$3',`144',`28')'); +define(`PKG_TQFP160_28', `PKG_QFP_65(`$1',`$2',`$3',`160',`28')'); +define(`PKG_TQFP208_28', `PKG_QFP_50(`$1',`$2',`$3',`208',`28')'); +define(`PKG_TQFP160_28', `PKG_QFP_65(`$1',`$2',`$3',`160',`28')'); +define(`PKG_TQFP240_32', `PKG_QFP_50(`$1',`$2',`$3',`240',`32')'); +define(`PKG_TQFP304_40', `PKG_QFP_50(`$1',`$2',`$3',`304',`40')'); + +# +## Rectangular Quad-side flat pack + +define(`PKG_QFP64_R', `PKG_QFP_100(`$1',`$2',`$3', `64',`0')'); +define(`PKG_QFP80_R', `PKG_QFP_80L(`$1',`$2',`$3', `80',`0')'); +define(`PKG_QFP100_R', `PKG_QFP_65L(`$1',`$2',`$3',`100',`0')'); +define(`PKG_QFP128_R', `PKG_QFP_50L(`$1',`$2',`$3',`128',`0')'); +define(`PKG_LQFP128_R', `PKG_LQFP_50(`$1',`$2',`$3',`128',`0')'); + +## Zig-zag in-line package +# ZIP20 .. ZIP40 +# +define(`PKG_ZIP9', `PKG_SD(`$1', `$2', `$3', 9)'); +define(`PKG_ZIP12', `PKG_SD(`$1', `$2', `$3', 12)'); +define(`PKG_ZIP16', `PKG_SD(`$1', `$2', `$3', 16)'); +define(`PKG_ZIP18', `PKG_SD(`$1', `$2', `$3', 18)'); +define(`PKG_ZIP20', `PKG_SD(`$1', `$2', `$3', 20)'); +define(`PKG_ZIP24', `PKG_SD(`$1', `$2', `$3', 24)'); +define(`PKG_ZIP28', `PKG_SD(`$1', `$2', `$3', 28)'); +define(`PKG_ZIP40', `PKG_SD(`$1', `$2', `$3', 40)'); + +# +## Axial non-polar component (typically resistor or capacitor), +# 300 through 1000 mil between pins +# AXN300 .. AXN1000 +# +define(`PKG_ACY300', `PKG_AXIAL_LAY(`$1', `$2', `$3', 300)'); +define(`PKG_ACY400', `PKG_AXIAL_LAY(`$1', `$2', `$3', 400)'); +define(`PKG_ACY500', `PKG_AXIAL_LAY(`$1', `$2', `$3', 500)'); +define(`PKG_ACY600', `PKG_AXIAL_LAY(`$1', `$2', `$3', 600)'); +define(`PKG_ACY800', `PKG_AXIAL_LAY(`$1', `$2', `$3', 800)'); +define(`PKG_ACY1000', `PKG_AXIAL_LAY(`$1', `$2', `$3', 1000)'); + + +## Axial polar component (typically capacitor), +# 300 through 1000 mil between pins +# +define(`PKG_ACY300P', `PKG_AXIAL_LAY_POLAR(`$1', `$2', `$3', 300)') +define(`PKG_ACY400P', `PKG_AXIAL_LAY_POLAR(`$1', `$2', `$3', 400)') +define(`PKG_ACY500P', `PKG_AXIAL_LAY_POLAR(`$1', `$2', `$3', 500)') +define(`PKG_ACY600P', `PKG_AXIAL_LAY_POLAR(`$1', `$2', `$3', 600)') +define(`PKG_ACY800P', `PKG_AXIAL_LAY_POLAR(`$1', `$2', `$3', 800)') +define(`PKG_ACY1000P', `PKG_AXIAL_LAY_POLAR(`$1', `$2', `$3', 1000)') + +# +## Axial diode (pin 1 is cathode) +# ALF300 .. ALF1000 +# +# +define(`PKG_ALF300', `PKG_DIODE_LAY(`$1', `$2', `$3', 300)'); +define(`PKG_ALF400', `PKG_DIODE_LAY(`$1', `$2', `$3', 400)'); +define(`PKG_ALF500', `PKG_DIODE_LAY(`$1', `$2', `$3', 500)'); +define(`PKG_ALF600', `PKG_DIODE_LAY(`$1', `$2', `$3', 600)'); +define(`PKG_ALF800', `PKG_DIODE_LAY(`$1', `$2', `$3', 800)'); +define(`PKG_ALF1000',`PKG_DIODE_LAY(`$1', `$2', `$3', 1000)'); + +# +## Bottom lead non-polar circular component (typically capacitor) +# pin spacing 100 mil and up +# RCY100 .. RCY1000 +# +define(`PKG_RCY100', `PKG_RADIAL_CAN(`$1', `$2', `$3', 200)'); +define(`PKG_RCY200', `PKG_RADIAL_CAN(`$1', `$2', `$3', 400)'); +define(`PKG_RCY300', `PKG_RADIAL_CAN(`$1', `$2', `$3', 600)'); +define(`PKG_RCY400', `PKG_RADIAL_CAN(`$1', `$2', `$3', 800)'); +define(`PKG_RCY500', `PKG_RADIAL_CAN(`$1', `$2', `$3', 1000)'); +define(`PKG_RCY600', `PKG_RADIAL_CAN(`$1', `$2', `$3', 1200)'); +define(`PKG_RCY800', `PKG_RADIAL_CAN(`$1', `$2', `$3', 1600)'); +define(`PKG_RCY1000', `PKG_RADIAL_CAN(`$1', `$2', `$3', 2000)'); + + +## Bottom lead polar circular component (typically capacitor) +# pin spacing 100 mil and up +# +define(`PKG_RCY100P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 200)'); +define(`PKG_RCY200P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 400)'); +define(`PKG_RCY300P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 600)'); +define(`PKG_RCY400P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 800)'); +define(`PKG_RCY500P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 1000)'); +define(`PKG_RCY600P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 1200)'); +define(`PKG_RCY800P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 1600)'); +define(`PKG_RCY1000P', `PKG_RADIAL_CAN_POLAR(`$1', `$2', `$3', 2000)'); + + +# +## Bottom lead rectangular non-polar component (typically capacitor) +# pin spacing 100 mil and up +# BRE100 .. BRE1200 +# +define(`PKG_BRE100', `PKG_RECTANGULAR2N(`$1', `$2', `$3', 200, 100)'); +define(`PKG_BRE200', `PKG_RECTANGULAR2N(`$1', `$2', `$3', 400, 100)'); +define(`PKG_BRE300', `PKG_RECTANGULAR2N(`$1', `$2', `$3', 600, 150)'); +define(`PKG_BRE400', `PKG_RECTANGULAR2( `$1', `$2', `$3', 600, 200)'); +define(`PKG_BRE500', `PKG_RECTANGULAR2( `$1', `$2', `$3', 750, 250)'); +define(`PKG_BRE600', `PKG_RECTANGULAR2( `$1', `$2', `$3', 1200, 300)'); +define(`PKG_BRE700', `PKG_RECTANGULAR2( `$1', `$2', `$3', 1050, 350)'); +define(`PKG_BRE800', `PKG_RECTANGULAR2( `$1', `$2', `$3', 1200, 400)'); +define(`PKG_BRE900', `PKG_RECTANGULAR2( `$1', `$2', `$3', 1350, 450)'); +define(`PKG_BRE1000', `PKG_RECTANGULAR2( `$1', `$2', `$3', 1500, 500)'); +define(`PKG_BRE1100', `PKG_RECTANGULAR2( `$1', `$2', `$3', 1650, 550)'); +define(`PKG_BRE1200', `PKG_RECTANGULAR2( `$1', `$2', `$3', 1800, 600)'); + +# +## Crystal +# HC49 +# +define(`PKG_HC49', `PKG_CRYSTAL(`$1', `$2', `$3', 300)'); + +# +## Crystal oscillator +# pins are NC, GND, CLK, VCC +# OSC14 +# +define(`PKG_OSC14', `PKG_OSC(`$1', `$2', `$3')'); + +# +## LED, size in mm (pin 1 is +, 2 is -) +# LED3, LED5 +# +define(`PKG_LED3', `PKG_LED(`$1', `$2', `$3', 118)'); +define(`PKG_LED5', `PKG_LED(`$1', `$2', `$3', 236)'); + +# +## Transistor +# TO3_90 +# TO3_45 +# TO126LAY +# TO126W for wide +# TO126S for standing +# TO126SW for both +# TO220 +# TO220W for wide +# TO220S for standing +# TO220SW for both +# +# as is TO3_90 +# as is TO3_45 +# as is TO5 +# as is TO92 +define(`PKG_TO126', `PKG_TO126LAY( `$1', `$2', `$3')'); +define(`PKG_TO126S', `PKG_TO126LAY_WIDE( `$1', `$2', `$3')'); +define(`PKG_TO126W', `PKG_TO126STAND( `$1', `$2', `$3')'); +define(`PKG_TO126SW',`PKG_TO126STAND_WIDE(`$1', `$2', `$3')'); +define(`PKG_TO220', `PKG_TO220LAY( `$1', `$2', `$3')'); +define(`PKG_TO220W', `PKG_TO220LAY_WIDE( `$1', `$2', `$3')'); +define(`PKG_TO220S', `PKG_TO220STAND( `$1', `$2', `$3')'); +define(`PKG_TO220SW',`PKG_TO220STAND_WIDE(`$1', `$2', `$3')'); + +## diode in TO220 +# +define(`PKG_TO220ACS', `PKG_TO220ACSTAND(`$1', `$2', `$3')'); +define(`PKG_TO218', `GENERIC_PL_POWER(`$1', `$2', `$3', 3, 219, 615, 200, 120,100, 60, 0)'); +# aka TOP3 +define(`PKG_TO247', `GENERIC_PL_POWER(`$1', `$2', `$3', 3, 219, 630, 210, 130,100, 60, 0)'); +# diode in TO247/TOP3 +define(`PKG_TO247_2', `GENERIC_PL_POWER(`$1', `$2', `$3', 2, 438, 630, 210, 130,100, 60, 0)'); +# aka TOP3BIG +define(`PKG_TO264', `GENERIC_PL_POWER(`$1', `$2', `$3', 3, 219, 800, 210, 130,100, 60, 0)'); +# aka IPAK +define(`PKG_TO251', `GENERIC_PL_POWER(`$1', `$2', `$3', 3, 90, 265, 100, 50, 70, 40, 0)'); + +define(`PKG_TO220ACSTAND', `GENERIC_PL_POWER(`$1', `$2', `$3', 2, 200, 400, 180, 100, 80, 40, 0)') + +# the definitions of PKG_TO220STAND PKG_TO220STAND-WIDE can be replaced by following lines: +#define(`PKG_TO220STAND', `GENERIC_PL_POWER(`$1', `$2', `$3', 3, 100, 400, 180, 100, 80, 40, 0)') +#define(`PKG_TO220STAND-WIDE', `GENERIC_PL_POWER(`$1', `$2', `$3', 3, 100, 400, 180, 200, 80, 40,-100)') + +# +## Power IC, as in MULTIWATT15 +# +# See the following: +# PENTAWATT: http://www.st.com/stonline/books/pdf/docs/9262.pdf +# HEPTAWATT: http://www.st.com/stonline/books/pdf/docs/5430.pdf +# MULTIWATT8: http://www.st.com/stonline/books/pdf/docs/5437.pdf +# MULTIWATT11: http://www.st.com/stonline/books/pdf/docs/5433.pdf +# MULTIWATT15: http://www.st.com/stonline/books/pdf/docs/5439.pdf + +# GENERIC_PL_POWER +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin count +# $5: pin spacing +# $6: body length (dimension parallel to rows of pins) +# $7: body width (dimension perpendicular to rows of pins) +# $8: pin/tab spacing +# $9: pad size +# $10: drill size +# $11: pin row spacing + +define(`PKG_PENTAWATT', `GENERIC_PL_POWER(`$1', `$2', `$3', 5, 67, 409, 189, 177, 90, 60, 157)' ); +define(`PKG_HEPTAWATT', `GENERIC_PL_POWER(`$1', `$2', `$3', 7, 50, 409, 189, 110, 90, 60, 200)' ); +define(`PKG_MULTIWATT8', `GENERIC_PL_POWER(`$1', `$2', `$3', 8, 100, 800, 200, 115, 90, 60, 0)' ); +define(`PKG_MULTIWATT11', `GENERIC_PL_POWER(`$1', `$2', `$3', 11, 67, 800, 200, 180, 90, 60, 200)' ); +define(`PKG_MULTIWATT15', `GENERIC_PL_POWER(`$1', `$2', `$3', 15, 50, 800, 200, 180, 90, 60, 200)' ); + +# +## Jumper, i.e. single row headers +# +define(`PKG_JUMPER1', `PKG_CONNECTOR(`$1', `$2', `$3', 1, 1)'); +define(`PKG_JUMPER2', `PKG_CONNECTOR(`$1', `$2', `$3', 2, 1)'); +define(`PKG_JUMPER3', `PKG_CONNECTOR(`$1', `$2', `$3', 3, 1)'); +define(`PKG_JUMPER4', `PKG_CONNECTOR(`$1', `$2', `$3', 4, 1)'); +define(`PKG_JUMPER5', `PKG_CONNECTOR(`$1', `$2', `$3', 5, 1)'); +define(`PKG_JUMPER6', `PKG_CONNECTOR(`$1', `$2', `$3', 6, 1)'); +define(`PKG_JUMPER7', `PKG_CONNECTOR(`$1', `$2', `$3', 7, 1)'); +define(`PKG_JUMPER8', `PKG_CONNECTOR(`$1', `$2', `$3', 8, 1)'); +define(`PKG_JUMPER9', `PKG_CONNECTOR(`$1', `$2', `$3', 9, 1)'); +define(`PKG_JUMPER10', `PKG_CONNECTOR(`$1', `$2', `$3', 10, 1)'); +define(`PKG_JUMPER11', `PKG_CONNECTOR(`$1', `$2', `$3', 11, 1)'); +define(`PKG_JUMPER12', `PKG_CONNECTOR(`$1', `$2', `$3', 12, 1)'); +define(`PKG_JUMPER14', `PKG_CONNECTOR(`$1', `$2', `$3', 14, 1)'); +define(`PKG_JUMPER16', `PKG_CONNECTOR(`$1', `$2', `$3', 16, 1)'); +define(`PKG_JUMPER18', `PKG_CONNECTOR(`$1', `$2', `$3', 18, 1)'); +define(`PKG_JUMPER20', `PKG_CONNECTOR(`$1', `$2', `$3', 20, 1)'); + +# +## MTA Connector, (0.100 inch pitch) +# +define(`PKG_MTA100_2', `PKG_MTA_100(`$1', `$2', `$3', 2)'); +define(`PKG_MTA100_3', `PKG_MTA_100(`$1', `$2', `$3', 3)'); +define(`PKG_MTA100_4', `PKG_MTA_100(`$1', `$2', `$3', 4)'); +define(`PKG_MTA100_5', `PKG_MTA_100(`$1', `$2', `$3', 5)'); +define(`PKG_MTA100_6', `PKG_MTA_100(`$1', `$2', `$3', 6)'); +define(`PKG_MTA100_7', `PKG_MTA_100(`$1', `$2', `$3', 7)'); +define(`PKG_MTA100_8', `PKG_MTA_100(`$1', `$2', `$3', 8)'); +define(`PKG_MTA100_9', `PKG_MTA_100(`$1', `$2', `$3', 9)'); +define(`PKG_MTA100_10', `PKG_MTA_100(`$1', `$2', `$3', 10)'); +define(`PKG_MTA100_11', `PKG_MTA_100(`$1', `$2', `$3', 11)'); +define(`PKG_MTA100_12', `PKG_MTA_100(`$1', `$2', `$3', 12)'); +define(`PKG_MTA100_13', `PKG_MTA_100(`$1', `$2', `$3', 13)'); +define(`PKG_MTA100_14', `PKG_MTA_100(`$1', `$2', `$3', 14)'); +define(`PKG_MTA100_15', `PKG_MTA_100(`$1', `$2', `$3', 15)'); + +# +## Header connector, DIP pin numbering +# Corresponding to gEDA symbols header2-1 .. header64-1 +# +define(`PKG_HEADER2_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 1)'); +define(`PKG_HEADER4_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 2)'); +define(`PKG_HEADER6_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 3)'); +define(`PKG_HEADER8_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 4)'); +define(`PKG_HEADER10_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 5)'); +define(`PKG_HEADER12_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 6)'); +define(`PKG_HEADER14_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 7)'); +define(`PKG_HEADER16_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 8)'); +define(`PKG_HEADER18_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 9)'); +define(`PKG_HEADER20_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 10)'); +define(`PKG_HEADER22_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 11)'); +define(`PKG_HEADER26_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 13)'); +define(`PKG_HEADER30_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 15)'); +define(`PKG_HEADER34_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 17)'); +define(`PKG_HEADER40_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 20)'); +define(`PKG_HEADER50_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 25)'); +define(`PKG_HEADER64_1', `PKG_CONNECTOR_DIL(`$1', `$2', `$3', 32)'); + +# +## Header connector, ribbon cable numbering +# corresponding to gEDA symbols header2-2 .. header64-2 +# +define(`PKG_HEADER2_2', `PKG_CONNECTOR(`$1', `$2', `$3', 1, 2)'); +define(`PKG_HEADER4_2', `PKG_CONNECTOR(`$1', `$2', `$3', 2, 2)'); +define(`PKG_HEADER6_2', `PKG_CONNECTOR(`$1', `$2', `$3', 3, 2)'); +define(`PKG_HEADER8_2', `PKG_CONNECTOR(`$1', `$2', `$3', 4, 2)'); +define(`PKG_HEADER10_2', `PKG_CONNECTOR(`$1', `$2', `$3', 5, 2)'); +define(`PKG_HEADER12_2', `PKG_CONNECTOR(`$1', `$2', `$3', 6, 2)'); +define(`PKG_HEADER14_2', `PKG_CONNECTOR(`$1', `$2', `$3', 7, 2)'); +define(`PKG_HEADER16_2', `PKG_CONNECTOR(`$1', `$2', `$3', 8, 2)'); +define(`PKG_HEADER18_2', `PKG_CONNECTOR(`$1', `$2', `$3', 9, 2)'); +define(`PKG_HEADER20_2', `PKG_CONNECTOR(`$1', `$2', `$3', 10, 2)'); +define(`PKG_HEADER22_2', `PKG_CONNECTOR(`$1', `$2', `$3', 11, 2)'); +define(`PKG_HEADER26_2', `PKG_CONNECTOR(`$1', `$2', `$3', 13, 2)'); +define(`PKG_HEADER30_2', `PKG_CONNECTOR(`$1', `$2', `$3', 15, 2)'); +define(`PKG_HEADER34_2', `PKG_CONNECTOR(`$1', `$2', `$3', 17, 2)'); +define(`PKG_HEADER40_2', `PKG_CONNECTOR(`$1', `$2', `$3', 20, 2)'); +define(`PKG_HEADER50_2', `PKG_CONNECTOR(`$1', `$2', `$3', 25, 2)'); +define(`PKG_HEADER60_2', `PKG_CONNECTOR(`$1', `$2', `$3', 30, 2)'); +define(`PKG_HEADER64_2', `PKG_CONNECTOR(`$1', `$2', `$3', 32, 2)'); + +# +## Header connector with latches +# +define(`PKG_DIN41651_10', `PKG_DIN41_651LAY( `$1', `$2', `$3', 10)'); +define(`PKG_DIN41651_14', `PKG_DIN41_651LAY( `$1', `$2', `$3', 14)'); +define(`PKG_DIN41651_16', `PKG_DIN41_651LAY( `$1', `$2', `$3', 16)'); +define(`PKG_DIN41651_20', `PKG_DIN41_651LAY( `$1', `$2', `$3', 10)'); +define(`PKG_DIN41651_26', `PKG_DIN41_651LAY( `$1', `$2', `$3', 26)'); +define(`PKG_DIN41651_34', `PKG_DIN41_651LAY( `$1', `$2', `$3', 34)'); +define(`PKG_DIN41651_40', `PKG_DIN41_651LAY( `$1', `$2', `$3', 40)'); +define(`PKG_DIN41651_50', `PKG_DIN41_651LAY( `$1', `$2', `$3', 50)'); +define(`PKG_DIN41651_60', `PKG_DIN41_651LAY( `$1', `$2', `$3', 60)'); +define(`PKG_DIN41651_64', `PKG_DIN41_651LAY( `$1', `$2', `$3', 64)'); + +define(`PKG_DIN41651_10S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 10)'); +define(`PKG_DIN41651_14S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 14)'); +define(`PKG_DIN41651_16S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 16)'); +define(`PKG_DIN41651_20S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 10)'); +define(`PKG_DIN41651_26S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 26)'); +define(`PKG_DIN41651_34S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 34)'); +define(`PKG_DIN41651_40S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 40)'); +define(`PKG_DIN41651_50S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 50)'); +define(`PKG_DIN41651_60S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 60)'); +define(`PKG_DIN41651_64S', `PKG_DIN41_651STAND(`$1', `$2', `$3', 64)'); + +# +## DSUB connector, female/male +# DE9F .. DC37F +# DE9M .. DC37M +# +define(`PKG_DE9F', `PKG_SUBD_FEMALE_LAY(`$1', `$2', `$3', 9)'); +define(`PKG_DA15F', `PKG_SUBD_FEMALE_LAY(`$1', `$2', `$3', 15)'); +define(`PKG_DB25F', `PKG_SUBD_FEMALE_LAY(`$1', `$2', `$3', 25)'); +define(`PKG_DC37F', `PKG_SUBD_FEMALE_LAY(`$1', `$2', `$3', 37)'); +define(`PKG_DE9M', `PKG_SUBD_MALE_LAY( `$1', `$2', `$3', 9)'); +define(`PKG_DA15M', `PKG_SUBD_MALE_LAY( `$1', `$2', `$3', 15)'); +define(`PKG_DB25M', `PKG_SUBD_MALE_LAY( `$1', `$2', `$3', 25)'); +define(`PKG_DC37M', `PKG_SUBD_MALE_LAY( `$1', `$2', `$3', 37)'); + +# backward compatibility for the uneducated +define(`PKG_DB9F', `PKG_SUBD_FEMALE_LAY(`$1', `$2', `$3', 9)'); +define(`PKG_DB15F', `PKG_SUBD_FEMALE_LAY(`$1', `$2', `$3', 15)'); +define(`PKG_DB37F', `PKG_SUBD_FEMALE_LAY(`$1', `$2', `$3', 37)'); +define(`PKG_DB9M', `PKG_SUBD_MALE_LAY( `$1', `$2', `$3', 9)'); +define(`PKG_DB15M', `PKG_SUBD_MALE_LAY( `$1', `$2', `$3', 15)'); +define(`PKG_DB37M', `PKG_SUBD_MALE_LAY( `$1', `$2', `$3', 37)'); + +# +## DIN connector, 96 pin housing +# DIN41612C96F ... +# +define(`PKG_DIN41612C96F', `PKG_DIN41_612FEMALE(`$1', `$2', `$3', `abc')'); +define(`PKG_DIN41612C96M', `PKG_DIN41_612MALE( `$1', `$2', `$3', `abc')'); +define(`PKG_DIN41612C64F', `PKG_DIN41_612FEMALE(`$1', `$2', `$3', `ac')'); +define(`PKG_DIN41612C64M', `PKG_DIN41_612MALE( `$1', `$2', `$3', `ac')'); + +define(`PKG_DIN41612C96FS', `PKG_DIN41_612FEMALE_SMALL(`$1', `$2', `$3', `abc')'); +define(`PKG_DIN41612C96MS', `PKG_DIN41_612MALE_SMALL( `$1', `$2', `$3', `abc')'); +define(`PKG_DIN41612C64FS', `PKG_DIN41_612FEMALE_SMALL(`$1', `$2', `$3', `ac')'); +define(`PKG_DIN41612C64MS', `PKG_DIN41_612MALE_SMALL( `$1', `$2', `$3', `ac')'); + +# +## Standard SMT resistor, capacitor etc +# 0201 .. 2706 +# +define(`PKG_old0201', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 20, 10)'); +define(`PKG_old0402', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 40, 20)'); +define(`PKG_old0603', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 60, 30)'); +define(`PKG_old0805', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 80, 50)'); +define(`PKG_old1008', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 100, 80)'); +define(`PKG_old1206', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 120, 60)'); +define(`PKG_old1210', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 120, 100)'); +define(`PKG_old1806', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 180, 60)'); +define(`PKG_old1812', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 180, 120)'); +define(`PKG_old1825', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 180, 250)'); +define(`PKG_2706', `PKG_SMT_2PAD_MIL( `$1', `$2', `$3', 270, 60)'); + +# The following are recommendations from IPC-7351 +# The naming convention, like 'CAPC0603L' follows the IPC standard. At the end +# of each size is a package named like '0603', '1206' which is more or less a compromise part based +# on the nominal IPC footprints for that package size. Any additions to this section +# should follow the IPC naming convention and size. +# +# The base macro accepts the numbers directly (after multiplying by 100) from the IPC +# standard so they are fairly simple to add. + +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pad X (size of pad in direction perpendicular to axis of part) [1/100 mm] +# $5: pad Y (size of pad in direction parallel to axis of part) [1/100 mm] +# $6: pad center to center spacing [1/100 mm] +# $7: courtyard size in direction parallel to axis of part [1/100 mm] (V1) +# $8: courtyard size in direction perpendicular to axis of part [1/100 mm] (V2) +# $9: length of silk screen line [1/100 mm] (R1) +# $10: spacing of silk screen line [1/100 mm] (R2) + +# 01005 +# See for example Murata GRM02 series. +# package X is 0.2 mm +/- 0.02 mm +# package Y is 0.07 to 0.14 mm +# package inner pad edge to pad edge is 0.13 min +# package outer pad edge to outer pad edge is 0.4 mm +/- 0.02 mm +# package height is 0.2mm +/- 0.02 mm + +# From page 10 of IPC-7351, Feb 2005, +# Zmax = length of pattern = Lmin (overall length of the component) + 2*Jt + sqrt(Cl^2 + F^2 + P^2) +# Gmin = Distance between lands of the pattern = Smax (distance between terminals) - 2*Jh - sqrt(Cs^2 + F^2 + P^2) +# Xmax = Width of pattern = Wmin (width of lead) + 2*Js + sqrt(Cw^2 + F^2 + P^2) +# +# C = component tolerance = *max - *min +# F = PCB tolerance - used 0.05 +# P = placement tolerance - used 0.05 +# +# X = Xmax = 0.18/0.18/0.23 round to get 0.20/0.20/0.25 +# Y = 0.5 * (Zmax - Gmin) +# center to center = 0.5 * (Zmax + Gmin) +# +# +# Jt = 0.00/0.10/0.20 +# Jh = -0.05/-0.05/-0.05 +# Js = 0.00/0.00/0.05 +# Round to nearest 0.05 +# Courtyard excess 0.10/0.15/0.20 +# +# +# Note that rounding to 0.05 mm produces a roundoff error of up to +/- 1 mil. This can be significant +# when we're talking about gaps on the order of 6 mils. So for this really tiny part, round to 0.01 mm +define(`PKG_CAPC0402L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 26, 15, 31, 56, 28, 0, 0)'); +define(`PKG_CAPC0402N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 26, 25, 41, 81, 33, 0, 0)'); +define(`PKG_CAPC0402M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 36, 35, 51, 106, 38, 0, 0)'); + +define(`PKG_INDC0402L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 26, 15, 31, 56, 28, 0, 0)'); +define(`PKG_INDC0402N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 26, 25, 41, 81, 33, 0, 0)'); +define(`PKG_INDC0402M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 36, 35, 51, 106, 38, 0, 0)'); + +define(`PKG_RESC0402L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 26, 15, 31, 56, 28, 0, 0)'); +define(`PKG_RESC0402N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 26, 25, 41, 81, 33, 0, 0)'); +define(`PKG_RESC0402M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 36, 35, 51, 106, 38, 0, 0)'); + +define(`PKG_01005', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 26, 25, 41, 81, 33, 0, 0)'); + +# 0201 +define(`PKG_CAPC0603L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 30, 30, 50, 100, 60, 0, 0)'); +define(`PKG_CAPC0603N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 40, 40, 60, 130, 80, 0, 0)'); +define(`PKG_CAPC0603M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 50, 50, 80, 160, 90, 0, 0)'); + +define(`PKG_RESC0603L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 30, 30, 50, 100, 60, 0, 0)'); +define(`PKG_RESC0603N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 40, 40, 60, 130, 80, 0, 0)'); +define(`PKG_RESC0603M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 50, 50, 80, 160, 90, 0, 0)'); + +define(`PKG_0201', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 40, 40, 60, 130, 80, 0, 0)'); + +# 0402 (C,L = 0.6 mm high, R = 0.4 mm high) +define(`PKG_CAPC1005L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 55, 40, 90, 150, 80, 0, 0)'); +define(`PKG_CAPC1005N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 65, 50, 90, 170, 100, 0, 0)'); +define(`PKG_CAPC1005M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 75, 60, 100, 200, 120, 0, 0)'); + +define(`PKG_INDC1005L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 60, 50, 80, 150, 90, 0, 0)'); +define(`PKG_INDC1005N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 70, 50, 80, 170, 100, 0, 0)'); +define(`PKG_INDC1005M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 80, 70, 100, 200, 120, 0, 0)'); + +define(`PKG_RESC1005L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 55, 35, 90, 150, 80, 0, 0)'); +define(`PKG_RESC1005N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 65, 45, 100, 170, 100, 0, 0)'); +define(`PKG_RESC1005M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 75, 55, 110, 200, 120, 0, 0)'); + +define(`PKG_new0402', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 70, 50, 80, 170, 100, 0, 0)'); +define(`PKG_0402', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 70, 50, 90, 170, 100, 400)'); + +# 0603 (C = 0.85 mm high, L = 0.95 mm high, R = 0.60 mm high) +define(`PKG_CAPC1608L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 90, 65, 120, 200, 120, 0, 0)'); +define(`PKG_CAPC1608N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 100, 75, 130, 230, 130, 0, 0)'); +define(`PKG_CAPC1608M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 110, 85, 140, 270, 150, 0, 0)'); + +define(`PKG_INDC1608L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 90, 65, 120, 200, 120, 0, 0)'); +define(`PKG_INDC1608N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 100, 75, 130, 230, 130, 0, 0)'); +define(`PKG_INDC1608M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 110, 85, 140, 270, 150, 0, 0)'); + +define(`PKG_RESC1608L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 90, 50, 120, 200, 120, 0, 90)'); +define(`PKG_RESC1608N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 100, 60, 140, 230, 130, 0, 0)'); +define(`PKG_RESC1608M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 110, 70, 150, 270, 150, 10, 110)'); + +define(`PKG_new0603', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 100, 75, 130, 230, 130, 0, 0)'); +define(`PKG_0603', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 100, 75, 130, 230, 130, 600)'); + +# 0805 (C = 1.1 mm high, L = 1.2 mm high, R = 0.65 mm high) +define(`PKG_CAPC2012L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 140, 110, 160, 280, 170, 0, 0)'); +define(`PKG_CAPC2012N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 150, 130, 180, 350, 200, 0, 0)'); +define(`PKG_CAPC2012M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 160, 150, 200, 440, 260, 0, 0)'); + +define(`PKG_INDC2012L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 140, 110, 160, 280, 170, 0, 0)'); +define(`PKG_INDC2012N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 150, 130, 180, 350, 200, 0, 0)'); +define(`PKG_INDC2012M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 160, 150, 200, 440, 260, 0, 0)'); + +define(`PKG_RESC2012L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 130, 100, 160, 280, 160, 20, 130)'); +define(`PKG_RESC2012N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 140, 120, 180, 350, 190, 20, 140)'); +define(`PKG_RESC2012M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 150, 140, 200, 440, 250, 20, 150)'); + +define(`PKG_new0805', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 150, 130, 180, 350, 200, 20, 140)'); +define(`PKG_0805', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 150, 130, 180, 350, 200, 1000)'); + +# 1008 (L = 2.2 mm high) +define(`PKG_INDC2520L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 220, 90, 240, 340, 250, 80, 220)'); +define(`PKG_INDC2520N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 230, 110, 260, 410, 280, 70, 230)'); +define(`PKG_INDC2520M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 240, 130, 280, 500, 340, 80, 240)'); + +define(`PKG_new1008', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 230, 110, 260, 410, 280, 70, 230)'); +define(`PKG_1008', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 230, 110, 260, 410, 280, 1000)'); + +# 1206 (C = 1.35 mm high, L = 1.9 mm high, R = 0.71 mm high) +define(`PKG_CAPC3216L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 170, 110, 280, 400, 200, 90, 170)'); +define(`PKG_CAPC3216N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 180, 130, 300, 470, 230, 100, 180)'); +define(`PKG_CAPC3216M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 190, 150, 320, 560, 290, 100, 190)'); + +define(`PKG_INDC3216L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 180, 100, 300, 420, 210, 120, 180)'); +define(`PKG_INDC3216N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 190, 120, 320, 490, 240, 120, 190)'); +define(`PKG_INDC3216M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 200, 140, 340, 580, 300, 130, 200)'); + +define(`PKG_RESC3216L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 170, 110, 280, 400, 200, 90, 170)'); +define(`PKG_RESC3216N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 180, 130, 300, 470, 230, 100, 180)'); +define(`PKG_RESC3216M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 190, 150, 320, 560, 290, 100, 190)'); + +define(`PKG_new1206', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 190, 130, 300, 490, 240, 120, 190)'); +define(`PKG_1206', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 190, 130, 300, 490, 240, 1000)'); + +# 1210 (C = 1.35 mm high, L = 1.35 mm high, R = 0.71 mm high) +define(`PKG_CAPC3225L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 260, 110, 280, 400, 290, 90, 260)'); +define(`PKG_CAPC3225N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 270, 130, 300, 470, 320, 100, 270)'); +define(`PKG_CAPC3225M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 280, 150, 320, 560, 380, 100, 280)'); + +define(`PKG_INDC3225L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 260, 110, 280, 400, 290, 90, 260)'); +define(`PKG_INDC3225N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 270, 130, 300, 470, 320, 100, 270)'); +define(`PKG_INDC3225M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 280, 150, 320, 560, 380, 100, 280)'); + +define(`PKG_RESC3225L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 260, 110, 280, 400, 290, 90, 260)'); +define(`PKG_RESC3225N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 270, 130, 300, 470, 320, 100, 270)'); +define(`PKG_RESC3225M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 280, 150, 320, 560, 380, 100, 280)'); + +define(`PKG_new1210', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 270, 130, 300, 470, 320, 100, 270)'); +define(`PKG_1210', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 270, 130, 300, 470, 320, 1000)'); + +# 1806 (L = 1.9 mm high) + +define(`PKG_INDC4509L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 110, 130, 400, 540, 150, 200, 110)'); +define(`PKG_INDC4509N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 120, 150, 420, 610, 170, 190, 120)'); +define(`PKG_INDC4509M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 130, 170, 440, 700, 230, 200, 130)'); + +define(`PKG_new1806', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 120, 150, 420, 610, 170, 190, 120)'); +define(`PKG_1806', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 120, 150, 420, 610, 170, 1000)'); + +# 1812 (C = 1.35 mm high, L = 1.75 mm high, R = 1.1 mm high) +define(`PKG_CAPC4532L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 330, 140, 380, 540, 370, 160, 330)'); +define(`PKG_CAPC4532N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 340, 160, 400, 610, 390, 160, 340)'); +define(`PKG_CAPC4532M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 350, 180, 420, 700, 450, 160, 350)'); + +define(`PKG_INDC4532L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 330, 140, 380, 540, 370, 160, 330)'); +define(`PKG_INDC4532N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 340, 160, 400, 610, 390, 160, 340)'); +define(`PKG_INDC4532M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 350, 180, 420, 700, 450, 160, 350)'); + +define(`PKG_RESC4532L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 330, 140, 380, 540, 370, 160, 330)'); +define(`PKG_RESC4532N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 340, 160, 400, 610, 390, 160, 340)'); +define(`PKG_RESC4532M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 350, 180, 420, 700, 450, 160, 350)'); + +define(`PKG_new1812', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 340, 160, 400, 610, 390, 160, 340)'); +define(`PKG_1812', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 340, 160, 400, 610, 390, 1000)'); + +# 1825 (C = 1.1 mm high, R = 1.35 mm high) +define(`PKG_CAPC4564L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 670, 140, 380, 540, 700, 160, 670)'); +define(`PKG_CAPC4564N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 680, 160, 400, 610, 730, 160, 680)'); +define(`PKG_CAPC4564M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 690, 180, 420, 700, 790, 160, 690)'); + +define(`PKG_RESC4564L', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 670, 140, 380, 540, 700, 160, 670)'); +define(`PKG_RESC4564N', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 680, 160, 400, 610, 730, 160, 680)'); +define(`PKG_RESC4564M', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 690, 180, 420, 700, 790, 160, 690)'); + +define(`PKG_new1825', `PKG_SMT_2PAD_MM100( `$1', `$2', `$3', 680, 160, 400, 610, 730, 160, 680)'); +define(`PKG_1825', `PKG_SMT_2PAD_MS( `$1', `$2', `$3', 680, 160, 400, 610, 730, 1000)'); + + + +# +## 3-Pin SMT EMI Filter based on standard SMT sizes +# See www.murata.com for example +# +define(`PKG_EMI0603', `COMMON_SMT_3PAD_MIL( `$1', `$2', `$3', 24, 24, 63, 47, 16, 10, 10)'); +define(`PKG_EMI0805', `COMMON_SMT_3PAD_MIL( `$1', `$2', `$3', 32, 24, 79, 75, 24, 10, 10)'); +define(`PKG_EMI1206', `COMMON_SMT_3PAD_MIL( `$1', `$2', `$3', 32, 28, 126, 79, 39, 10, 10)'); +define(`PKG_EMI1806', `COMMON_SMT_3PAD_MIL( `$1', `$2', `$3', 39, 39, 177, 102, 59, 10, 10)'); + +# +## Tantalum SMT capacitor (pin 1 is +) +# pin 1 is marked (and is presumably +), pin 2 is minus +# EIA3216 .. EIA7343 +# +define(`PKG_EIA3216', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 32, 16)'); +define(`PKG_EIA3528', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 35, 28)'); +define(`PKG_EIA6032', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 60, 32)'); +define(`PKG_EIA7343', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 73, 43)'); + +define(`PKG_TANT_A', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 32, 16)'); +define(`PKG_TANT_B', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 35, 28)'); +define(`PKG_TANT_C', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 60, 32)'); +define(`PKG_TANT_D', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 73, 43)'); + +# +## Surface mount electrolytic capacitor, number is dia in mm +define(`PKG_SME3', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 33, 33)'); +define(`PKG_SME4', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 43, 43)'); +define(`PKG_SME5', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 53, 53)'); +define(`PKG_SME6', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 66, 66)'); +define(`PKG_SME8', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 84, 84)'); +define(`PKG_SME10', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3',104,104)'); + +# +## SMT diode (pin 1 is cathode) +# (pin 2 is anode) +# SOD110 .. +# +# SOD23D is a SOT23 housing with pin numbers that match diodes +# it can also be used for transistors that used this numbering +# dimensions of `PKG_SMT_DIODE( `$1', `$2', `$3', len=mm/10, wid=mm/10)'); #JG +# dimensions of `PKG_SM/EIT_2PAD_EIA( `$1', `$2', `$3', len=mm/10, wid=mm/10)'); #JG +# +define(`PKG_SOD80', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 37, 16)'); +define(`PKG_SOD87', `PKG_SMT_2PAD_EIA( `$1', `$2', `$3', 37, 21)'); +define(`PKG_SOD106A', `PKG_SMT_DIODE( `$1', `$2', `$3', 55, 25)'); +define(`PKG_SOD110', `PKG_SMT_DIODE( `$1', `$2', `$3', 21, 14)'); +# BUG: pads are only 0.65 mm wide: +define(`PKG_SOD123', `PKG_SMT_DIODE( `$1', `$2', `$3', 40, 15)'); +# BUG: pads are only 0.60 mm wide: +define(`PKG_SOD323', `PKG_SMT_DIODE( `$1', `$2', `$3', 27, 13)'); +define(`PKG_DO214', `PKG_SMT_DIODE( `$1', `$2', `$3', 77, 33)'); #JG +define(`PKG_DO214AB', `PKG_SMT_DIODE( `$1', `$2', `$3', 79, 34)'); #JG +define(`PKG_SOT23D', `PKG_SMT_TRANSISTOR2( `$1', `$2', `$3', 20, 21)'); +define(`PKG_SOT323D', `PKG_SMT_TRANSISTOR2( `$1', `$2', `$3', 13, 18)'); + +# +## SMT transistor, 3 pins +define(`PKG_SOT23', `PKG_SMT_TRANSISTOR3( `$1', `$2', `$3', 20, 21)'); +define(`PKG_SOT323', `PKG_SMT_TRANSISTOR3( `$1', `$2', `$3', 13, 18)'); +define(`PKG_SC90', `PKG_SMT_TRANSISTOR3( `$1', `$2', `$3', 10, 15)'); +define(`PKG_SC70_3', `PKG_SMT_TRANSISTOR3( `$1', `$2', `$3', 13, 18)'); + +## SMT transistor, 4 pins +define(`PKG_SOT89', `PKG_SMT_TRANSISTOR4X(`$1', `$2', `$3', 31, 31)'); +define(`PKG_SOT143', `PKG_SMT_TRANSISTOR4( `$1', `$2', `$3', 19, 21)'); +define(`PKG_SOT223', `PKG_SMT_TRANSISTOR4X(`$1', `$2', `$3', 46, 62)'); +define(`PKG_SC70_4', `PKG_SMT_TRANSISTOR4( `$1', `$2', `$3', 13, 18)'); + +## SMT transistor, 5 pins +# aka SOT23-5 +define(`PKG_SOT25', `PKG_SMT_TRANSISTOR5( `$1', `$2', `$3', 20, 21)'); +define(`PKG_SOT325', `PKG_SMT_TRANSISTOR5( `$1', `$2', `$3', 13, 18)'); +define(`PKG_SC70_5', `PKG_SMT_TRANSISTOR5A(`$1', `$2', `$3', 13, 18)'); + +## SMT transistor, 6 pins +# aka SOT23-6 +define(`PKG_SOT26', `PKG_SMT_TRANSISTOR6( `$1', `$2', `$3', 20, 21)'); +define(`PKG_SOT326', `PKG_SMT_TRANSISTOR6( `$1', `$2', `$3', 13, 18)'); +define(`PKG_SC70_6', `PKG_SMT_TRANSISTOR6( `$1', `$2', `$3', 13, 18)'); + +## Pressure transducer +define(`PKG_MPAK', `COMMON_SMT_TRANSISTORX_MIL(`$1', `$2', `$3', 150, 437, 20, `12345')'); + +# +## Virtual component, no footprint +# +define(`PKG_DUMMY');
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/hirose.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,77 @@ +# -*- m4 -*- +# $Id: hirose.inc,v 1.1 2011/07/30 04:29:51 msokolov Exp $ +# +# Fancy connectors from Hirose + +# Hirose DF19 series +# board-to-cable / board-to-FPC +# commonly used for LCD panels and other LVDS applications +# +# The receptacle is the only gender intended for PCB mounting +# in this series; the mating plug is part of cable assemblies. +# Cable assemblies may be plain wire, FPC or micro-coax, but the choice +# of cable type does not affect the PCB-mounted receptacle type. +# +# The PCB-mounted receptacle is available in several different versions: +# top-board horizontal mounting (right angle, cable parallel to board), +# offset mounting (same thing, but requires a special cutout in the PCB), +# or top-board vertical mounting (cable perpendicular to board). +# These versions require different footprints; the only footprint +# that has been created so far is for the top-board horizontal mounting +# version. +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of contacts +define(`DF19RCPT_HOR_TOP', + ` +Element[0x00 "$1" "$2" "$3" 200000 100000 0 0 0 100 0x00] +( + # We put the mark at the bottom of the keepout directly under pin 1 + # the intermediate calculations are in .01mm units + define(`left_gnd_nearedge', 185) + define(`left_gnd_centre', eval(left_gnd_nearedge + 55)) + define(`left_gnd_faredge', eval(left_gnd_nearedge + 110)) + define(`right_gnd_nearedge', eval(($4 - 1) * 100 + 165)) + define(`right_gnd_centre', eval(right_gnd_nearedge + 55)) + define(`right_gnd_faredge', eval(right_gnd_nearedge + 110)) + # pad geometry + define(`padwidth', eval(550000/254)) + define(`gndpadwidth', eval(1100000/254)) + define(`youter', eval(6000000/254)) + define(`yinner', eval(5000000/254)) + define(`gndtop', eval(2500000/254)) + define(`maskextra', 600) + # draw the pads first + forloop(i, 1, $4, ` + define(`Xpos', eval((i-1) * 1000000 / 254)) + Pad[Xpos -eval(youter-padwidth/2) Xpos -eval(yinner+padwidth/2) + padwidth 1000 eval(padwidth+maskextra) + "" "i" ""] + ') + # ground/mechanical pads + define(`Xpos', -eval(left_gnd_centre * 10000 / 254)) + Pad[Xpos -eval(gndtop-gndpadwidth/2) Xpos -eval(gndpadwidth/2) + gndpadwidth 1000 eval(gndpadwidth+maskextra) + "GND" "eval($4 + 1)" ""] + define(`Xpos', eval(right_gnd_centre * 10000 / 254)) + Pad[Xpos -eval(gndtop-gndpadwidth/2) Xpos -eval(gndpadwidth/2) + gndpadwidth 1000 eval(gndpadwidth+maskextra) + "GND" "eval($4 + 2)" ""] + # silk outline + define(`silkW', 1000) + define(`silktop', eval(4700000/254)) + define(`silkext', 1100) + define(`silkleft', eval(left_gnd_faredge * 10000 / 254 + silkext)) + define(`silkright', eval(right_gnd_faredge * 10000 / 254 + silkext)) + ElementLine[-silkleft -silktop silkright -silktop silkW] + ElementLine[-silkleft silkext silkright silkext silkW] + ElementLine[-silkleft -silktop -silkleft silkext silkW] + ElementLine[silkright -silktop silkright silkext silkW] +)') + +define(`PKG_DF19RCPT_8H', `DF19RCPT_HOR_TOP(`$1',`$2',`$3', 8)') +define(`PKG_DF19RCPT_14H', `DF19RCPT_HOR_TOP(`$1',`$2',`$3',14)') +define(`PKG_DF19RCPT_20H', `DF19RCPT_HOR_TOP(`$1',`$2',`$3',20)') +define(`PKG_DF19RCPT_30H', `DF19RCPT_HOR_TOP(`$1',`$2',`$3',30)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/johnstech.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,326 @@ +# -*- m4 -*- +# $Id: johnstech.inc,v 1.2 2007/02/26 03:52:34 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2003 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# +# Johnstech Evaluation Socket for QFN packages +# Johnstech Socket Part Numbers 724810 through 724839 +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size (mm) +# $6: pad pitch (1/100 mm) +# $7: PCB pad width (1/100 mm) +# $8: Package pad length (1/100 mm) +# $9: Exposed paddle size, 0 for no exposed paddle (1/100 mm) + +define(`PKG_GENERIC_JOHNSTECH7248_QFN', + ` + # number of pins on left/right sides (pin1 is upper pin on left side) + define(`LRPINS', eval($4 / 4)) + # number of pins on top/bottom sides + define(`TBPINS', eval(`$4' / 2 - LRPINS)) + # pin pitch (1/1000 mil) + define(`PITCH',eval(`$6'*100000/254)) + # y-coordinate for upper pin on left/right sides (1/1000 mil) + define(`LRYMAX', eval((LRPINS-1)*PITCH/2)) + # x-coordinate for right pin on top/bottom sides (1/1000 mil) + define(`TBXMAX', eval((TBPINS-1)*PITCH/2)) + # total horizontal package width (1/1000 mil) + define(`LRWIDTHMM', ifelse(0,`$5',`787',eval($5))) + define(`LRWIDTH', ifelse(0,`$5',`787',eval(`$5'*10000000/254))) + # total vertical package width (1/1000 mil) + define(`TBWIDTHMM', ifelse(0,`$5',`551',eval($5))) + define(`TBWIDTH',ifelse(0,`$5',`551',eval(`$5'*10000000/254))) + # how much pads extend beyond the package edge (1/1000 mil) (the 75 is 0.75 mm) + define(`EXTOUT', eval(75*100000/254)) + # how much pads extend inward from the package pad edge (1/1000 mil) + define(`EXTIN', eval(5*100000/254)) + # pad length/width (1/1000 mil) + define(`PADLENGTH', eval(`$8'*100000/254)) + define(`PADWIDTH', eval(`$7'*100000/254)) + # pad width (mil/100) + define(`PADWIDTHMIL100', eval(PADWIDTH/10)) + # min/max x coordinates for the pads on the left/right sides of the package (mil/100) + define(`LRXMAX',eval((LRWIDTH/2 + EXTOUT - PADWIDTH/2)/10)) + define(`LRXMIN',eval((LRWIDTH/2 -PADLENGTH - EXTIN + PADWIDTH/2)/10)) + # min/max y coordinates for the pads on the top/bottom sides of the package (mil/100) + define(`TBYMAX',eval((TBWIDTH/2 + EXTOUT - PADWIDTH/2)/10)) + define(`TBYMIN',eval((TBWIDTH/2 -PADLENGTH - EXTIN + PADWIDTH/2)/10)) + + # pad size and drill size (mil/100) for the mounting holes + define(`MOUNTPAD', 7700) + define(`MOUNTDRILL', 2000) + # soldermask relief size for mounting holes (mil/100) + define(`MOUNTMASK', eval(MOUNTPAD + 1000)) + + # silkscreen width (mils/100) + define(`SILKW', 1000) + # how much the silk screen is moved away from the package (1/1000 mil) + define(`SILKEXT', eval(200*100000/254 + SILKW*10/2 + 5*1000)) + # upper right corner for silk screen (mil/100) + define(`SILKX', eval((LRWIDTH/2 + SILKEXT )/10)) + define(`SILKY', eval((TBWIDTH/2 + SILKEXT )/10)) + # refdes text size (mil/100) + define(`TEXTSIZE', 100) + # x,y coordinates for refdes label (mil/100) + define(`TEXTX', -SILKX) + define(`TEXTY', eval(-SILKY - 1000 - TEXTSIZE/2)) + # square exposed paddle size (mil/100) + define(`EPSIZE', eval(`$9'*10000/254)) + + # location of mounting holes (mil/100) + define(`MOUNTX', eval((LRWIDTH/2 + 39370)/10)) + define(`MOUNTY', eval((TBWIDTH/2 + 39370)/10)) + + # latch silkscreen width (mils/100) + define(`LSILKW', 100) + # points for latch silk on the left/right sides of the part (mil/100) + define(`LATCHLRYMIN', eval((-TBWIDTH/2 - 25*100000/254 )/10)) + define(`LATCHLRYMAX', eval(( TBWIDTH/2 + 25*100000/254 )/10)) + define(`LATCHLRXMIN', SILKX) + define(`LATCHLRXMAX', eval(( LRWIDTH/2 + 400*100000/254 )/10)) + # points for latch silk on the top/bottom sides of the part (mil/100) + define(`LATCHTBXMIN', eval((-LRWIDTH/2 - 25*100000/254 )/10)) + define(`LATCHTBXMAX', eval(( LRWIDTH/2 + 25*100000/254 )/10)) + define(`LATCHTBYMIN', SILKY) + define(`LATCHTBYMAX', eval(( TBWIDTH/2 + 400*100000/254 )/10)) + + # points for silk showing where the exposed paddle contacts are (mil/100) + define(`CONTL', 100) + ifelse(1, eval(TBWIDTHMM>4), `define(`CONTL', 200)') + ifelse(1, eval(TBWIDTHMM>5), `define(`CONTL', 300)') + + # spacing between rows of EP contacts in 1/100 mm. + define(`CONTS', 0) + ifelse(1, eval(TBWIDTHMM>5), `define(`CONTS', eval(TBWIDTHMM*100 - 430))') + + define(`EPY', eval((CONTL*100000/254)/10)) + define(`EPXMIN', eval(((CONTS/2 - 20/2)*100000/254)/10)) + define(`EPXMAX', eval(((CONTS/2 + 20/2)*100000/254)/10)) + + # soldermask opening (mil/100) + define(`MASKSIZE', eval((400*100000/254 + TBWIDTH)/10)) + + +# element_flags, description, pcb-name, value, mark_x, mark_y, +# text_x, text_y, text_direction, text_scale, text_flags +Element[0x00000000 "$1" "$2" "$3" 0 0 TEXTX TEXTY 0 TEXTSIZE 0x00000000] +( + +# left row +define(`CURPIN', 1) +define(`idx',0) +forloop(`i', 1, LRPINS, + `define(`Y', eval((-LRYMAX + PITCH*idx)/10))' + `Pad[-LRXMAX Y -LRXMIN Y PADWIDTHMIL100 0 0 "CURPIN" "CURPIN" 0x00000000]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# bottom row +define(`idx',0) +forloop(`i', 1, TBPINS, + `define(`X', eval((-TBXMAX + PITCH*idx)/10))' + `Pad[X TBYMAX X TBYMIN PADWIDTHMIL100 0 0 "CURPIN" "CURPIN" 0x00000800]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# right row +define(`idx',0) +forloop(`i', 1, LRPINS, + `define(`Y', eval(( LRYMAX - PITCH*idx)/10))' + `Pad[LRXMAX Y LRXMIN Y PADWIDTHMIL100 0 0 "CURPIN" "CURPIN" 0x00000000]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# top row +define(`idx',0) +forloop(`i', 1, TBPINS, + `define(`X', eval((TBXMAX - PITCH*idx)/10))' + `Pad[X -TBYMAX X -TBYMIN PADWIDTHMIL100 0 0 "CURPIN" "CURPIN" 0x00000800]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# Exposed paddle. Note that this pad also sets the soldermask +# relief for the entire part. +# Pad(X1, Y1, X2, Y3, width, clearance, +# soldermask, "pin name", "pin number", flags) +Pad[0 0 0 0 EPSIZE 0 MASKSIZE "CURPIN" "CURPIN" 0x00000100] +define(`CURPIN', incr(CURPIN)) +# Mounting pins + +# Pin(x, y, thickness, clearance, mask, drilling hole, name, +# number, flags +Pin[ MOUNTX MOUNTY MOUNTPAD 1000 MOUNTMASK MOUNTDRILL "Mount1" "CURPIN" 0x0] +define(`CURPIN', incr(CURPIN)) +Pin[ -MOUNTX MOUNTY MOUNTPAD 1000 MOUNTMASK MOUNTDRILL "Mount2" "CURPIN" 0x0] +define(`CURPIN', incr(CURPIN)) +Pin[ -MOUNTX -MOUNTY MOUNTPAD 1000 MOUNTMASK MOUNTDRILL "Mount3" "CURPIN" 0x0] +define(`CURPIN', incr(CURPIN)) +Pin[ MOUNTX -MOUNTY MOUNTPAD 1000 MOUNTMASK MOUNTDRILL "Mount4" "CURPIN" 0x0] + +# Silk screen around package +ElementLine[ SILKX SILKY SILKX -SILKY SILKW] +ElementLine[ SILKX -SILKY -SILKX -SILKY SILKW] +ElementLine[-SILKX -SILKY -SILKX SILKY SILKW] +ElementLine[-SILKX SILKY SILKX SILKY SILKW] + +# Pin 1 indicator +ElementLine[-SILKX -SILKY eval(-SILKX - 1500) eval(-SILKY - 1500) SILKW] + +# Silk showing latch area + +# top +ElementLine[ LATCHTBXMIN -LATCHTBYMIN LATCHTBXMIN -LATCHTBYMAX LSILKW ] +ElementLine[ LATCHTBXMIN -LATCHTBYMAX LATCHTBXMAX -LATCHTBYMAX LSILKW ] +ElementLine[ LATCHTBXMAX -LATCHTBYMIN LATCHTBXMAX -LATCHTBYMAX LSILKW ] + +# bottom +ElementLine[ LATCHTBXMIN LATCHTBYMIN LATCHTBXMIN LATCHTBYMAX LSILKW ] +ElementLine[ LATCHTBXMIN LATCHTBYMAX LATCHTBXMAX LATCHTBYMAX LSILKW ] +ElementLine[ LATCHTBXMAX LATCHTBYMIN LATCHTBXMAX LATCHTBYMAX LSILKW ] + +# left +ElementLine[ -LATCHLRXMIN LATCHLRYMAX -LATCHLRXMAX LATCHLRYMAX LSILKW ] +ElementLine[ -LATCHLRXMAX LATCHLRYMAX -LATCHLRXMAX LATCHLRYMIN LSILKW ] +ElementLine[ -LATCHLRXMIN LATCHLRYMIN -LATCHLRXMAX LATCHLRYMIN LSILKW ] + +# right +ElementLine[ LATCHLRXMIN LATCHLRYMAX LATCHLRXMAX LATCHLRYMAX LSILKW ] +ElementLine[ LATCHLRXMAX LATCHLRYMAX LATCHLRXMAX LATCHLRYMIN LSILKW ] +ElementLine[ LATCHLRXMIN LATCHLRYMIN LATCHLRXMAX LATCHLRYMIN LSILKW ] + +# Silk showing area for exposed paddle socket contacts +ElementLine[ EPXMIN -EPY EPXMIN EPY LSILKW ] +ElementLine[ EPXMAX -EPY EPXMAX EPY LSILKW ] +ElementLine[ EPXMIN EPY EPXMAX EPY LSILKW ] +ElementLine[ EPXMIN -EPY EPXMAX -EPY LSILKW ] + +# packages with width >= 6.0 mm have 2 rows of contacts +ifelse(1, eval(TBWIDTHMM>5), +ElementLine[ -EPXMIN -EPY -EPXMIN EPY LSILKW ] +ElementLine[ -EPXMAX -EPY -EPXMAX EPY LSILKW ] +ElementLine[ -EPXMIN EPY -EPXMAX EPY LSILKW ] +ElementLine[ -EPXMIN -EPY -EPXMAX -EPY LSILKW ] +) + +)') + +# ------------------------------------------------------------------- + +# The following macros take: +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size (mm) +# $6: exposed paddle size (1/100 mm). 0 for no exposed paddle + + +# For an exposed paddle package, the paddle for an 'n' pin package is pin 'n+1' + +# 0.8 mm pitch +define(`PKG_JOHNSTECH_QFN_80', `PKG_GENERIC_JOHNSTECH7248_QFN(`$1',`$2',`$3',`$4',`$5', `80',`36',`50', `$6')') +# 0.65 mm pitch +define(`PKG_JOHNSTECH_QFN_65', `PKG_GENERIC_JOHNSTECH7248_QFN(`$1',`$2',`$3',`$4',`$5', `65',`36',`50', `$6')') +# 0.50 mm pitch, 0.6 mm pad length +define(`PKG_JOHNSTECH_QFN_50', `PKG_GENERIC_JOHNSTECH7248_QFN(`$1',`$2',`$3',`$4',`$5', `50',`36',`50', `$6')') +# 0.50 mm pitch, 0.4 mm pad length +define(`PKG_JOHNSTECH_QFN_50S',`PKG_GENERIC_JOHNSTECH7248_QFN(`$1',`$2',`$3',`$4',`$5', `50',`36',`50', `$6')') +# 0.40 mm pitch +define(`PKG_JOHNSTECH_QFN_40', `PKG_GENERIC_JOHNSTECH7248_QFN(`$1',`$2',`$3',`$4',`$5', `40',`36',`50', `$6')') + + +# PKG_GENERIC_JOHNSTECH7248_QFN +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size (mm) +# $6: pad pitch (1/100 mm) +# $7: PCB pad width (1/100 mm) +# $8: Package pad length (1/100 mm) +# $9: Exposed paddle size, 0 for no exposed paddle (1/100 mm) +# ------------------------------------------------------------------- + +# EXTRACT_BEGIN + +## Johnstech QFN Socket, Series 1MM (724812-724839) + +# 4x4 mm +define(`PKG_JOHNSTECH_QFN12_4', `PKG_JOHNSTECH_QFN_80(`$1',`$2',`$3', `12', `4', `210')') +#define(`PKG_JOHNSTECH_TQFN12_4', `PKG_JOHNSTECH_QFN_80(`$1',`$2',`$3', `12', `4', `210')') + +define(`PKG_JOHNSTECH_QFN16_4', `PKG_JOHNSTECH_QFN_65(`$1',`$2',`$3', `16', `4', `210')') +#define(`PKG_JOHNSTECH_TQFN16_4', `PKG_JOHNSTECH_QFN_65(`$1',`$2',`$3', `16', `4', `210')') + +define(`PKG_JOHNSTECH_QFN20_4', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `20', `4', `210')') +#define(`PKG_JOHNSTECH_TQFN20_4', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `20', `4', `210')') + +define(`PKG_JOHNSTECH_QFN24_4', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `24', `4', `210')') +#define(`PKG_JOHNSTECH_TQFN24_4', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `24', `4', `260')') + +# 5x5 mm +define(`PKG_JOHNSTECH_QFN16_5', `PKG_JOHNSTECH_QFN_80(`$1',`$2',`$3', `16', `5', `310')') +#define(`PKG_JOHNSTECH_TQFN16_5', `PKG_JOHNSTECH_QFN_80(`$1',`$2',`$3', `16', `5', `310')') + +define(`PKG_JOHNSTECH_QFN20_5', `PKG_JOHNSTECH_QFN_65(`$1',`$2',`$3', `20', `5', `310')') +#define(`PKG_JOHNSTECH_TQFN20_5', `PKG_JOHNSTECH_QFN_65(`$1',`$2',`$3', `20', `5', `310')') + +define(`PKG_JOHNSTECH_QFN28_5', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `28', `5', `310')') +#define(`PKG_JOHNSTECH_TQFN28_5', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `28', `5', `325')') + +define(`PKG_JOHNSTECH_QFN32_5', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `32', `5', `310')') +#define(`PKG_JOHNSTECH_TQFN32_5', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `32', `5', `310')') + +# 6x6 mm +define(`PKG_JOHNSTECH_QFN36_6', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `36', `6', `370')') +#define(`PKG_JOHNSTECH_TQFN36_6', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `36', `6', `370')') + +define(`PKG_JOHNSTECH_QFN40_6', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `40', `6', `410')') +#define(`PKG_JOHNSTECH_TQFN40_6', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `40', `6', `410')') + +# 7x7 mm +define(`PKG_JOHNSTECH_QFN32_7', `PKG_JOHNSTECH_QFN_65(`$1',`$2',`$3', `32', `7', `470')') +#define(`PKG_JOHNSTECH_TQFN32_7', `PKG_JOHNSTECH_QFN_65(`$1',`$2',`$3', `32', `7', `470')') + +define(`PKG_JOHNSTECH_QFN44_7', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `44', `7', `470')') +#define(`PKG_JOHNSTECH_TQFN44_7', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `44', `7', `470')') + +define(`PKG_JOHNSTECH_QFN48_7', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `48', `7', `560')') +#define(`PKG_JOHNSTECH_TQFN48_7', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `48', `7', `560')') + +# 8x8 mm +define(`PKG_JOHNSTECH_QFN56_8', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `56', `8', `665')') +#define(`PKG_JOHNSTECH_TQFN56_8', `PKG_JOHNSTECH_QFN_50S(`$1',`$2',`$3', `56', `8', `665')') + +# 10x10 mm +define(`PKG_JOHNSTECH_QFN68_10', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `68', `10', `770')') +#define(`PKG_JOHNSTECH_TQFN68_10', `PKG_JOHNSTECH_QFN_50(`$1',`$2',`$3', `68', `10', `770')') + +# EXTRACT_END +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/midcom.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,55 @@ +# -*- m4 -*- +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: midcom.inc,v 1.3 2007/03/10 08:12:22 msokolov Exp $ +# +# Midcom transformer packages + +# Midcom EP13 TH package, based on PKG_DIL +define(`PKG_EP13_TH', +` + define(`PINSPACE', `100') + define(`PADSIZE', `60') + define(`DRILLSIZE', `28') + define(`MAXY', 550) + define(`MAXX', 550) + define(`CENTERX', eval(MAXX / 2)) +Element(0x00 "`$1'" "`$2'" "`$3'" eval(CENTERX + 20) 100 3 100 0x00) +( + forloop(`i', 1, 5, + `PIN(eval(MAXX-75), eval((2*i-1) * PINSPACE/2 + 25), + eval(PADSIZE), eval(DRILLSIZE), i) + ') + forloop(`i', 1, 5, + `PIN(75, eval(MAXY - (2*i-1) * PINSPACE/2 - 25), + eval(PADSIZE), eval(DRILLSIZE), eval(i + 5)) + ') + ElementLine(0 0 0 MAXY 10) + ElementLine(0 MAXY MAXX MAXY 10) + ElementLine(MAXX MAXY MAXX 0 10) + ElementLine(0 0 MAXX 0 10) + # pin 1 marker + ElementLine(500 0 550 50 10) + Mark(75 75) +)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/minicircuits.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,66 @@ +# -*- m4 -*- +# +# $Id: minicircuits.inc,v 1.1 2007/02/19 05:28:32 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2003 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# +# Mini-Circuits Specific Footprints + + +# EXTRACT_BEGIN + +# COMMON_SMT_DIL_{MIL,MM} +# $4: number of pins +# $5: pad width (1/1000 mil or 1/100 mm) +# $6: pad length (1/1000 mil or 1/100 mm) +# $7: pad pitch (1/1000 mil 1/100 mm) +# $8: pad seperation for pads on opposite sides of +# the package (1/1000 mil or 1/100 mm) +# $9: define to make the pins get numbered starting with the highest pin +# instead of pin 1. Needed for certain brain damaged packages like +# the Mini-Circuits KK81 + +# +## Mini-Circuits CA Style Package +# +define(`PKG_MINICIRCUITS_CA531', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',6,20000,50000,37000,40000)') + +# +## Mini-Circuits CB Style Package +# +define(`PKG_MINICIRCUITS_CB518', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',10,30000,90000,50000,110000)') +define(`PKG_MINICIRCUITS_CB539', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',10,30000,90000,50000,135000)') + +# +## Mini-Circuits CD Style Package +# +define(`PKG_MINICIRCUITS_CD541', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',6,65000,100000,100000,100000)') +define(`PKG_MINICIRCUITS_CD542', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',6,65000,100000,100000,100000)') +define(`PKG_MINICIRCUITS_CD636', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',6,65000,100000,100000,100000)') +define(`PKG_MINICIRCUITS_CD637', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',6,65000,100000,100000,100000)') + +# +## Mini-Circuits KK Style Package +# +define(`PKG_MINICIRCUITS_KK81', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',6,50000,126000,100000,354000,"reverse")') + +# EXTRACT_END +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/misc.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,656 @@ +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: misc.inc,v 1.2 2007/02/26 03:52:35 msokolov Exp $ +# +# misc packages +# + +# ------------------------------------------------------------------- +# the definition of a SD (ZIP) package +# based on 'old style format' by Olaf Kaluza (olaf@criseis.ruhr.de) +# +# For example, see http://focus.ti.com/lit/ml/mczi002/mczi002.pdf +# for the Texas Instruments SDZ (R-PZIP-T16) Ceramic Zig Zag package +# That drawing shows the pin width varying from 0.45mm to 0.65mm +# (18 to 26 mils) and the width in the other dimension from .23mm +# to .35mm. The cross section is rectangular. This gives a diagonal +# from 0.505mm (19.9 mil) to 0.738mm (29 mil). +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# +define(`PKG_SD', + `define(`MAXY', eval(`$4' / 2 * 100 + 50)) +Element(0x00 "$1" "$2" "$3" 275 50 3 100 0x00) +( + forloop(`i', 1, eval($4 / 2), + `PIN(50, eval(100*(i-1)+50), 60, 35, eval(2*i-1)) + PIN(150, eval(100*(i-1)+100), 60, 35, eval(2*i)) + ') + + ElementLine(0 0 0 MAXY 20) + ElementLine(0 MAXY 200 MAXY 20) + ElementLine(200 MAXY 200 0 20) + ElementLine(200 0 0 0 20) + ElementLine(100 0 100 100 10) + ElementLine(100 100 0 100 10) + + Mark(50 50) +)') + +# ------------------------------------------------------------------- +# the definition of a plastic power package vertical +# for TO220 (2-7pins), TO251, TOP3, MULTIWATT(8-15pins) +# based on 'old style format' by Olaf Kaluza (olaf@criseis.ruhr.de) +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin count +# $5: pin spacing +# $6: body length (dimension parallel to rows of pins) +# $7: body width (dimension perpendicular to rows of pins) +# $8: pin/tab spacing +# $9: pad size +# $A: drill size +# $B: pin row spacing + +define(`GENERIC_PL_POWER', + `define(`pin1X', eval((`$6' - (`$4' - 1) * `$5')/2)) +Element(0x00 "$1" "$2" "$3" eval(`$6'+60) 50 3 100 0x00) +( + forloop(`i', 1, `$4', + `PIN(eval(pin1X + (i-1)*`$5'), ifelse(eval(i % 2 == 0), 0, eval(`$8'+`$B'), `$8'), `$9', `$A', i) + ') + ElementLine(0 0 0 `$7' 20) + ElementLine(0 `$7' `$6' `$7' 20) + ElementLine(`$6' `$7' `$6' 0 20) + ElementLine(`$6' 0 0 0 20) + ElementLine(0 50 `$6' 50 10) + ElementLine(eval(`$6'/2 - 75) 0 eval(`$6'/2 - 75) 50 10) + ElementLine(eval(`$6'/2 + 75) 0 eval(`$6'/2 + 75) 50 10) + Mark(pin1X eval(`$7'+`$A')) + )') + +# ------------------------------------------------------------------- +# the definition of a resistor (0.25W) package +# $1: canonical name +# $2: name on PCB +# $3: value +define(`PKG_R025', +`Element(0x00 "$1" "$2" "$3" 120 30 0 100 0x00) +( + PIN(0, 50, 50, 20, 1) + PIN(400, 50, 50, 20, 2) + ElementLine(100 0 300 0 20) + ElementLine(300 0 300 100 20) + ElementLine(300 100 100 100 20) + ElementLine(100 100 100 0 20) + ElementLine(0 50 100 50 20) + ElementLine(300 50 400 50 20) + Mark(0 50) +)') + +# ------------------------------------------------------------------- +# the definition of a SIL package without a common pin +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +define(`PKG_SIL', + `define(`MAXY', eval(`$4' * 100 -50)) +Element(0x00 "$1" "$2" "$3" 160 10 3 100 0x00) +( + forloop(`i', 1, $4, + `PIN(50, eval(i * 100 -50), 50, 20, i) + ') + ElementLine( 0 50 0 MAXY 20) + ElementLine(100 50 100 MAXY 20) + ElementArc(50 50 50 50 180 180 20) + ElementArc(50 MAXY 50 50 0 180 20) + forloop(`i', 1, eval($4 /2 -1), + `ElementLine(0 eval(i * 200) 100 eval(i * 200) 10) + ') + Mark(50 50) +)') + +# ------------------------------------------------------------------- +# the definition of a SIL package with a common pin +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +define(`PKG_CSIL', + `define(`MAXY', eval(`$4' * 100 -50)) +Element(0x00 "$1" "$2" "$3" 160 10 3 100 0x00) +( + forloop(`i', 1, $4, + `PIN(50, eval(i * 100 -50), 50, 20, i) + ') + ElementLine( 0 50 0 MAXY 20) + ElementLine(100 50 100 MAXY 20) + ElementLine( 0 100 100 100 10) + ElementArc(50 50 50 50 180 180 20) + ElementArc(50 MAXY 50 50 0 180 20) + Mark(50 50) +)') + +# ------------------------------------------------------------------- +# a QFP-132 pin flat pack +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +# based on mail by Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +define(`PKG_QFP132', +`Element(0x00 "$1" "$2" "$3" 250 200 0 150 0x00) +( + forloop(`i', 1, 17, + `define(`XPOS', eval(625 -i*25))' + `PAD(XPOS, 40, XPOS, 90, 15, i) + ') + forloop(`i', 1, 16, + `define(`XPOS', eval(1025 -i*25))' + `PAD(XPOS, 40, XPOS, 90, 15, eval(i+116)) + ') + forloop(`i', 1, 33, + `define(`YPOS', eval(175 +i*25))' + `PAD(30, YPOS, 80, YPOS, 15, i) + ') + forloop(`i', 1, 33, + `define(`XPOS', eval(175 +i*25))' + `PAD(XPOS, 1160, XPOS, 1110, 15, eval(i+50)) + ') + forloop(`i', 1, 33, + `define(`YPOS', eval(1025 -i*25))' + `PAD(1120, YPOS, 1170, YPOS, 15, i) + ') + + # Markierung pin 1 + ElementArc(600 150 10 10 0 360 5) + + # Nase links oben (PIN 17/18) + ElementLine( 125 175 75 150 20) + ElementLine( 75 150 75 125 20) + ElementLine( 75 125 125 75 20) + ElementLine( 125 75 150 75 20) + ElementLine( 150 75 175 125 20) + + # Verbindungsline zur Ecke rechts oben + ElementLine( 175 125 1025 125 20) + + # Nase rechts oben (PIN 116/117) + ElementLine(1025 125 1050 75 20) + ElementLine(1050 75 1075 75 20) + ElementLine(1075 75 1125 125 20) + ElementLine(1125 125 1125 150 20) + ElementLine(1125 150 1075 175 20) + + # Verbindungsline zur Ecke rechts unten + ElementLine(1075 175 1075 1025 20) + + # Nase rechts unten (PIN 83/84) + ElementLine(1075 1025 1125 1050 20) + ElementLine(1125 1050 1125 1075 20) + ElementLine(1125 1075 1075 1125 20) + ElementLine(1075 1125 1050 1125 20) + ElementLine(1050 1125 1025 1075 20) + + # Verbindungsline zur Ecke links unten + ElementLine(1025 1075 175 1075 20) + + # Nase links unten (PIN 50/51) + ElementLine( 175 1075 150 1125 20) + ElementLine( 150 1125 125 1125 20) + ElementLine( 125 1125 75 1075 20) + ElementLine( 75 1075 75 1050 20) + ElementLine( 75 1050 125 1025 20) + + # Verbindungsline zur Ecke links oben + ElementLine( 125 1025 125 175 20) + + # Markierung so anordnen, dass Pinanchse im 25-MIL-Raster zu liegen kommt + Mark(200 200) +)') + +# ------------------------------------------------------------------- +# LED +# Pin 1 is -, 2 is + +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: diameter +# +# based on mail by Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +define(`PKG_LED', + `define(`RADIUS1', eval(`$4' /2)) + define(`RADIUS2', eval(`$4' /2 +20)) +Element(0x00 "$1" "$2" "$3" 100 70 0 100 0x00) +( +# typical LED is 0.5 mm or 0.020" square pin. See for example +# http://www.lumex.com and part number SSL-LX3054LGD. +# 0.020" square is 0.0288" diagonal. A number 57 drill is +# 0.043" which should be enough. a 65 mil pad gives 11 mils +# of annular ring. + + PIN(-50, 0, 65, 43, 1) + PIN(50, 0, 65, 43, 2) + ifelse( eval(RADIUS1 - 10 > 85), 1, + ElementArc(0 0 RADIUS1 RADIUS1 0 360 10) +, + ElementArc(0 0 RADIUS1 RADIUS1 45 90 10) + ElementArc(0 0 RADIUS1 RADIUS1 225 90 10) +) + ifelse( eval(RADIUS2 - 10 > 85), 1, + ElementArc(0 0 RADIUS2 RADIUS2 0 360 10) +, + ElementArc(0 0 RADIUS2 RADIUS2 45 90 10) + ElementArc(0 0 RADIUS2 RADIUS2 225 90 10) +) + Mark(0 0) +)') + +# ------------------------------------------------------------------- +# diodes +# Pin 1 is K, 2 is A +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: distance in mil +# +define(`PKG_DIODE_LAY', + `define(`X1', eval(`$4' /3)) + define(`X2', eval(`$4' -X1)) + define(`Y', eval(`$4' /2)) + define(`DELTA', eval(X1 /2)) + define(`PINSIZE', ifelse(eval($4 >= 500), 1, 80, 50)) +Element(0x00 "$1" "$2" "$3" eval(X2+20) eval(Y-DELTA) 0 100 0x00) +( + PIN(0, Y, PINSIZE, 20, 1) + PIN($4, Y, PINSIZE, 20, 2) + + ElementLine(0 Y X1 Y 10) + ElementLine(X2 Y $4 Y 10) + + ElementLine(X1 Y X2 eval(Y-DELTA) 10) + ElementLine(X2 eval(Y-DELTA) X2 eval(Y+DELTA) 10) + ElementLine(X2 eval(Y+DELTA) X1 Y 10) + ElementLine(X1 eval(Y-DELTA) X1 eval(Y+DELTA) 10) + Mark(0 Y) +)') + +# ------------------------------------------------------------------- +# the definition of a general axial package +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: distance in mil +define(`PKG_AXIAL_LAY', + `define(`X1', eval(`$4' /4)) + define(`X2', eval(`$4' -X1)) + define(`Y1', eval(X1 /3)) + define(`Y2', eval(Y1 *2)) + define(`PINSIZE', ifelse(eval($4 >= 600), 1, 80, 50)) +Element(0x00 "$1" "$2" "$3" eval(X2+20) eval(Y2+20) 0 100 0x00) +( + PIN(0, Y1, PINSIZE, 20, 1) + PIN($4, Y1, PINSIZE, 20, 2) + + ElementLine(0 Y1 X1 Y1 10) + ElementLine(X2 Y1 $4 Y1 10) + + ElementLine(X1 0 X2 0 10) + ElementLine(X2 0 X2 Y2 10) + ElementLine(X2 Y2 X1 Y2 10) + ElementLine(X1 Y2 X1 0 10) + +# ElementArc(X1 Y 50 50 270 180 10) +# ElementArc(X2 Y 50 50 90 180 10) + + Mark(X1 Y1) +)') + +# ------------------------------------------------------------------- +# an crystal package +# Pin 1 is K, 2 is A +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: package width in MIL +# +define(`PKG_CRYSTAL', + `define(`X1', `100') + define(`X2', `$4') + define(`Y', `100') + define(`Y1', eval(Y -50)) + define(`Y2', eval(Y +50)) +Element(0x00 "$1" "`$2'" "$3" X1 eval(Y2+20) 0 100 0x00) +( + PIN(X1, Y, 60, 20, 1) + PIN(X2, Y, 60, 20, 2) + ElementLine(X1 Y1 X2 Y1 10) + ElementLine(X1 Y2 X2 Y2 10) + ElementArc(X1 Y 50 50 270 180 10) + ElementArc(X2 Y 50 50 90 180 10) + Mark (X1 Y) +)') + +# ------------------------------------------------------------------- +# a can oscillator package +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +define(`PKG_OSC', +`Element(0x00 "$1" "$2" "$3" 270 300 3 100 0x00) +( + Pin(100 100 50 20 "NC" 0x01) + Pin(100 700 50 20 "GND" 0x01) + Pin(400 700 50 20 "CLK" 0x01) + Pin(400 100 50 20 "VCC" 0x01) + + ElementLine(5 5 400 5 10) + ElementArc(400 100 95 95 180 90 10) + ElementLine(495 100 495 700 10) + ElementArc(400 700 95 95 90 90 10) + ElementLine(400 795 100 795 10) + ElementArc(100 700 95 95 0 90 10) + ElementLine(5 700 5 5 10) + + ElementLine(100 60 400 60 10) + ElementArc(400 100 40 40 180 90 10) + ElementLine(440 100 440 700 10) + ElementArc(400 700 40 40 90 90 10) + ElementLine(400 740 100 740 10) + ElementArc(100 700 40 40 0 90 10) + ElementLine(60 700 60 100 10) + ElementArc(100 100 40 40 270 90 10) + + Mark(100 100) +)') + +# ------------------------------------------------------------------- +# 8 bit ISA Slot card +# +# Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de), 12/95 +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +define(`PKG_ISA8', +`Element(0x00 "$1" "$2" "$3" 4000 0 0 100 0x00) +( + # Pins, entspr. Anschl. auf Loetseite (b31..b1) + Pin( 200 3850 60 20 "Gnd (b31)" 0x01) + Pin( 300 3850 60 20 "Osc" 0x01) + Pin( 400 3850 60 20 "+5V" 0x01) + Pin( 500 3850 60 20 "BALE" 0x01) + Pin( 600 3850 60 20 "TC" 0x01) + Pin( 700 3850 60 20 "/DAck2" 0x01) + Pin( 800 3850 60 20 "IRq3" 0x01) + Pin( 900 3850 60 20 "IRq4" 0x01) + Pin(1000 3850 60 20 "IRq5" 0x01) + Pin(1100 3850 60 20 "IRq6" 0x01) + Pin(1200 3850 60 20 "IRq7" 0x01) + Pin(1300 3850 60 20 "Clock" 0x01) + Pin(1400 3850 60 20 "/Ref" 0x01) + Pin(1500 3850 60 20 "DRq1" 0x01) + Pin(1600 3850 60 20 "/DAck1" 0x01) + Pin(1700 3850 60 20 "DRq3" 0x01) + Pin(1800 3850 60 20 "/DAck3" 0x01) + Pin(1900 3850 60 20 "/IOR" 0x01) + Pin(2000 3850 60 20 "/IOW" 0x01) + Pin(2100 3850 60 20 "/SMEMR" 0x01) + Pin(2200 3850 60 20 "/SMEMW" 0x01) + Pin(2300 3850 60 20 "Gnd" 0x01) + Pin(2400 3850 60 20 "+12V" 0x01) + Pin(2500 3850 60 20 "/0WS" 0x01) + Pin(2600 3850 60 20 "-12V" 0x01) + Pin(2700 3850 60 20 "DRq2" 0x01) + Pin(2800 3850 60 20 "-5V" 0x01) + Pin(2900 3850 60 20 "IEQ2" 0x01) + Pin(3000 3850 60 20 "+5V" 0x01) + Pin(3100 3850 60 20 "ResDrv" 0x01) + Pin(3200 3850 60 20 "Gnd (b1)" 0x01) + + # Pins, entspr. Anschl. auf Bestueckseite + Pin( 200 3950 60 20 "SA0 (a31)" 0x01) + Pin( 300 3950 60 20 "SA1" 0x01) + Pin( 400 3950 60 20 "SA2" 0x01) + Pin( 500 3950 60 20 "SA3" 0x01) + Pin( 600 3950 60 20 "SA4" 0x01) + Pin( 700 3950 60 20 "SA5" 0x01) + Pin( 800 3950 60 20 "SA6" 0x01) + Pin( 900 3950 60 20 "SA7" 0x01) + Pin(1000 3950 60 20 "SA8" 0x01) + Pin(1100 3950 60 20 "SA9" 0x01) + Pin(1200 3950 60 20 "SA10" 0x01) + Pin(1300 3950 60 20 "SA11" 0x01) + Pin(1400 3950 60 20 "SA12" 0x01) + Pin(1500 3950 60 20 "SA13" 0x01) + Pin(1600 3950 60 20 "SA14" 0x01) + Pin(1700 3950 60 20 "SA15" 0x01) + Pin(1800 3950 60 20 "SA16" 0x01) + Pin(1900 3950 60 20 "SA17" 0x01) + Pin(2000 3950 60 20 "SA18" 0x01) + Pin(2100 3950 60 20 "SA19" 0x01) + Pin(2200 3950 60 20 "AEN" 0x01) + Pin(2300 3950 60 20 "IOChRdy" 0x01) + Pin(2400 3950 60 20 "SD0" 0x01) + Pin(2500 3950 60 20 "SD1" 0x01) + Pin(2600 3950 60 20 "SD2" 0x01) + Pin(2700 3950 60 20 "SD3" 0x01) + Pin(2800 3950 60 20 "SD4" 0x01) + Pin(2900 3950 60 20 "SD5" 0x01) + Pin(3000 3950 60 20 "SD6" 0x01) + Pin(3100 3950 60 20 "SD7" 0x01) + Pin(3200 3950 60 20 "/IOChCk (a1)" 0x01) + + # Umrahmung + ElementLine( 0 100 100 100 2) + ElementLine( 100 0 100 100 2) + ElementLine( 100 100 4250 100 5) + ElementLine(4250 100 4250 3810 5) + ElementLine(4250 3810 3620 3810 5) + ElementLine(3620 3810 3620 3510 5) + ElementLine(3620 3510 3300 3510 5) + ElementLine(3300 3510 3300 3810 5) + ElementLine(3300 3810 100 3810 5) + ElementLine( 100 3810 100 3510 5) + ElementLine( 100 3510 0 3510 2) + + # Markierung == Pin B1 + Mark(3200 3850) +)') + +# ------------------------------------------------------------------- +# an ovenized-oscillator package +# +# $1: canonical name +# $2: name on PCB +# $3: value +# Text(620 320 0 100 "GROUND" 0x0001) +# Text(620 520 0 100 "VECTRON LABORATORIES, INC." 0x0001) +# Text(620 720 0 100 "CO711 SERIES OSC" 0x0001) +# Text(620 920 0 100 "711-04-006" 0x0001) +# Text(620 1680 0 100 "+12 -> 15 VOLTS DC" 0x0001) +define(`PKG_OVEN_OSC', +`Element(0x00 "$1" "$2" "$3" 580 280 0 100 0x00) +( + Pin(320 320 150 35 "NC" 0x01) + Pin(320 1000 150 35 "VCC" 0x01) + Pin(320 1680 150 35 "CLK" 0x01) + Pin(1680 320 150 35 "+12V" 0x01) + Pin(1680 1680 150 35 "GND" 0x01) + + ElementLine(2020 1125 2020 875 10) + ElementLine(2100 875 2020 875 10) + ElementLine(2100 975 2100 875 10) + ElementLine(2075 975 2100 975 10) + ElementLine(2075 1025 2075 975 10) + ElementLine(2100 1025 2075 1025 10) + ElementLine(2100 1125 2100 1025 10) + ElementLine(2100 1125 2020 1125 10) + + ElementLine(2000 320 2000 1680 10) + ElementLine(320 0 1680 0 10) + ElementLine(0 1680 0 320 10) + ElementLine(1680 2000 320 2000 10) + + ElementArc(320 320 320 320 270 90 10) + ElementArc(320 1680 320 320 0 90 10) + ElementArc(1680 320 320 320 180 90 10) + ElementArc(1680 1680 320 320 90 90 10) + + Mark(320 320) +)') + +# a radial capacitor package +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: package width in MIL +# +define(`PKG_RADIAL_CAN', + `define(`X1', eval(`$4' /4)) + define(`X2', eval(`$4' -X1)) + define(`X3', eval(`$4' /2)) + define(`Y', eval(`$4' /2)) + define(`R', eval(`$4' /2)) + define(`PINSIZE', ifelse(eval($4 >= 600), 1, 80, 50)) +Element(0x00 "$1" "$2" "$3" eval(`$4') 0 0 100 0x00) +( + PIN(X1, Y, 60, 20, 1) + PIN(X2, Y, 60, 20, 2) + ElementArc(X3 Y R R 0 360 10) + Mark (X1 Y) +)') + +# a core surface mount package +# 12/99 Larry Doolittle <LRDoolittle@lbl.gov> +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: device length in MIL +# $5: device width in MIL +# +# Note that the pad width, length, and separation are derived from +# the given device dimensions. I <LRDoolittle@lbl.gov> don't +# claim to have followed any industry standards here, these sizes +# are based on someone else's measurements: +# 0603 is 30x40 mil pads on 60 mil pad ctr +# 0805 is 44x60 mil pads on 80 mil pad ctr +# on a PC motherboard. If you know the "real" values, please educate +# me and/or adjust this code. +# +define(`PKG_SMD_BASE', + `define(`T', eval(`$4'/4+`$5'/2)) + define(`W', eval(T/2+15)) + define(`X1', `0') + define(`X2', ``$4'') + define(`Y', `0') + define(`Y1', eval(Y-(`$5'-T)/2-5)) + define(`Y2', eval(Y+(`$5'-T)/2+5)) + # Silkscreen box coordinates + define(`X1L', eval(X1-W)) + define(`X2L', eval(X2+W)) + define(`Y1L', eval(Y1-W)) + define(`Y2L', eval(Y2+W)) +Element(0x00 "$1" "$2" "$3" eval(10+T/2) eval(Y2L+15) 0 100 0x00) +( + # PAD(X1, Y1, X1, Y2, T, 1) + # PAD(X2, Y1, X2, Y2, T, 2) + # Use Pad instead of PAD so both pads come out square + Pad(X1 Y1 X1 Y2 T "1" 0x100) + Pad(X2 Y1 X2 Y2 T "2" 0x100) + ElementLine(X1L Y1L X1L Y2L 8) + ElementLine(X1L Y2L X2L Y2L 8) + ElementLine(X2L Y2L X2L Y1L 8) + ElementLine(X2L Y1L X1L Y1L 8) + SMD_OUTLINE_EXTRA +)') + +define(`PKG_SMD_SIMPLE', + `define(`SMD_OUTLINE_EXTRA', `') + PKG_SMD_BASE(`$1', `$2', `$3', `$4', `$5') +') + +define(`PKG_SMD_DIODE', + `define(`SMD_OUTLINE_EXTRA', + ` + define(`XBAR', eval(X1L+10)) + ElementLine( XBAR Y1L XBAR Y2L 8 ) + ') + PKG_SMD_BASE(`$1', `$2', `$3', `$4', `$5') +') + +define(`PKG_SMD_POLAR', + `define(`SMD_OUTLINE_EXTRA', + ` + # crude plus sign + # ElementLine( X1 eval(Y2L+20) X1 eval(Y2L+70) 8) + # ElementLine( eval(X1-25) eval(Y2L+45) eval(X1+25) eval(Y2L+45) 8) + define(`XBAR', eval(X1L+10)) + ElementLine( XBAR Y1L XBAR Y2L 8 ) + + ') + PKG_SMD_BASE(`$1', `$2', `$3', `$4', `$5') +') + +# a smd chip package, capacitor or resistor +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: package designator length in MIL *100 + width in MIL /10 +# ie 402 == 40 X 20; 603 == 60 X 30 +# +define(`PKG_SMD_CHIP', + `define(`X1', eval(eval(`$4' /100)*10)) + define(`Y1', eval(eval(`$4'- X1 *10) *10)) +# line radius (LR) depicts offset to pads lines and pad "band width" + define(`LR', ifelse(eval(Y1 < 40), 1, eval(Y1/4), 10)) +Element(0x00 "$1" "$2" "$3" 0 0 0 25 0x00) +( + PAD(LR LR LR eval(Y1-LR) eval(LR*2) ) + PAD(eval(X1-LR) LR eval(X1-LR) eval(Y1-LR) eval(LR*2) ) + + ElementLine( 0 0 X1 0 5) + ElementLine(X1 0 X1 Y1 5) + ElementLine(X1 Y1 0 Y1 5) + ElementLine( 0 Y1 0 0 5) + + Mark(eval(X1/2) eval(Y1/2)) +)') +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/panasonic.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,56 @@ +# -*- m4 -*- +# +# $Id: panasonic.inc,v 1.1 2007/02/19 05:28:33 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2003, 2004 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# +# Panasonic Specific Footprints + + +# EXTRACT_BEGIN + +# +## Panasonic EXB Series Chip Resistor Array +# + +# COMMON_SMT_DIL_MM +# $4: number of pins +# $5: pad width (1/100 mm) +# $6: pad length (1/100 mm) +# $7: pad pitch (1/100 mm) +# $8: pad seperation for pads on opposite sides of +# the package (1/100 mm) +# $9: define to make the pins get numbered starting with the highest pin +# instead of pin 1. Needed for certain brain damaged packages like +# the Mini-Circuits KK81 + +define(`PKG_PANASONIC_EXB14V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',4,30,30,50,30)') +define(`PKG_PANASONIC_EXB24V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',4,38,48,65,50)') +define(`PKG_PANASONIC_EXB28V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',8,25,50,50,40)') +define(`PKG_PANASONIC_EXBV4V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',4,43,70,80,80)') +define(`PKG_PANASONIC_EXBV8V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',8,43,70,80,80)') +define(`PKG_PANASONIC_EXB34V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',4,45,80,80,80)') +define(`PKG_PANASONIC_EXB38V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',8,45,80,80,80)') +define(`PKG_PANASONIC_EXBS8V', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',8,63,120,127,110)') +define(`PKG_PANASONIC_EXB2HV', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',16,25,50,50,100)') + +# EXTRACT_END +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/pci.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,139 @@ +# $Id: pci.inc,v 1.1 2007/02/19 05:28:34 msokolov Exp $ +# +# Definitions for PCI boards +# by D.J. Barrow dj_barrow@ariasoft.ie +# +# please note that you will need to edit the saved pcb file +# by hand to move the board outline onto a seperate layer +# I suggest one of the unused layers. + +define(`GETNUMARRAYS',`eval(($#)/2)') +# $1: canonical name +# $2: name on PCB +# $3: boardheight,number of pins,arcradius,..., number of pins +define(`PKG_PCIPINARRAY', + ` + define(`cnt',`1') + define(`ARGS',`$4, $5, $6, $7') + args(ARGS) + define(`LEFTOFFSET',`100') + define(`EDGEGAP',`12') + define(`PINDIST',`50') + define(`PINWIDTH',`25') + define(`NUMARRAYS',`GETNUMARRAYS(ARGS)') + define(`TOTALPINS1',forloop(`IDX',0,eval(NUMARRAYS-1), + ``arg'eval((IDX*2)+2) + ')0) + define(`TOTALPINS',eval(TOTALPINS1)) + ifelse(1,eval(NUMARRAYS>1),` + define(`TOTALDIAMETER1',forloop(`IDX',0,eval(NUMARRAYS-2), + ``arg'eval((IDX*2)+3) + ')0) + define(`TOTALDIAMETER',eval(TOTALDIAMETER1)) + ') + define(`PINCENTER',`eval(LEFTOFFSET+(PINDIST/2))') + define(`PINRADIUS',`eval(PINWIDTH/2)') + define(`PINLEFT',`eval(PINCENTER-PINRADIUS)') + define(`PINRIGHT',`eval(PINCENTER+PINRADIUS)') + define(`PENWIDTH',`eval(PINRADIUS+4)') + define(`PENRADIUS',`eval(PENWIDTH/2)') + define(`MAXIDX',`eval(TOTALPINS - 1)') + define(`ARRAYWIDTH', `eval((TOTALPINS*PINDIST)+TOTALDIAMETER)') + define(`CENTERX', `eval(((ARRAYWIDTH+LEFTOFFSET)/2))') + define(`MINY',`20') + define(`MIDY',`220') + define(`MAXY',`270') + define(`ARCRADIUS',`12') + define(`ARCDIAMETER',`eval(ARCRADIUS*2)') + define(`LMAXY',`eval(MAXY+ARCRADIUS)') + define(`BOARDTOP',`eval(LMAXY-arg1)') + define(`SCREWBORDER',275) +Element(0x00 "$1" "$2" "$3" CENTERX 10 1 30 0x00) +( + Mark(CENTERX 135) + define(`ADDSIDE',0) + define(`FLAG',0x0) + define(`LOOPIDX1',eval(NUMARRAYS-1)) + define(`LEFT1',`eval(PINLEFT-ARCRADIUS)') + define(`ARCRADIUS2',`100') + define(`SLOTWIDTH',`1000') + define(`BRACKETLEFT',`-1525') + define(`LEFT2',`eval(LEFT1-ARCRADIUS2)') + define(`LEFT3',`eval(LEFT1+ARCRADIUS2-SLOTWIDTH)') + define(`LEFT4',`eval(LEFT1-SLOTWIDTH)') + ElementArc(LEFT2 0 ARCRADIUS2 ARCRADIUS2 180 90 1) + ElementLine(LEFT2 -ARCRADIUS2 LEFT3 -ARCRADIUS2 1) + ElementArc(LEFT3 0 ARCRADIUS2 ARCRADIUS2 270 90 1) + ElementLine(LEFT4 0 LEFT4 MAXY 1) + define(`LEFT5',`eval(LEFT4-ARCRADIUS)') + ElementArc(LEFT5 MAXY ARCRADIUS ARCRADIUS 90 90 1) + ElementLine(LEFT5 LMAXY BRACKETLEFT LMAXY 1) + forloop(`SIDE',0,1, + ` + define(`IDX',`0') + define(`ADDDIAMETER',`0') + forloop(`IDX1',0,LOOPIDX1, + ` + define(`CURRNUMPINS',`arg'eval((IDX1*2)+2)) + ifelse(SIDE,`0',` + define(`CURRLEFT',`eval((PINDIST*IDX)+(ADDDIAMETER)+PINLEFT)') + define(`CURRRIGHT',`eval(CURRLEFT+((CURRNUMPINS-1)*PINDIST)+PINWIDTH)') + ElementLine(CURRLEFT LMAXY CURRRIGHT LMAXY 2) + ElementArc(CURRLEFT MAXY ARCRADIUS ARCRADIUS 0 90 2) + ElementArc(CURRRIGHT MAXY ARCRADIUS ARCRADIUS 90 90 2) + define(`CURRLEFT1',`eval(CURRLEFT-ARCRADIUS)') + define(`CURRRIGHT1',`eval(CURRRIGHT+ARCRADIUS)') + ElementLine(CURRLEFT1 0 CURRLEFT1 MAXY 1) + ElementLine(CURRRIGHT1 0 CURRRIGHT1 MAXY 1) + ifelse(1,eval((NUMARRAYS>1)&&(IDX1<LOOPIDX1)),` + define(`CURRDIAMETER',`arg'eval((IDX1*2)+3)) + define(`CURRRADIUS',`eval(CURRDIAMETER/2)') + ElementArc(eval(CURRRIGHT+EDGEGAP+(CURRDIAMETER/2)) 0 CURRRADIUS CURRRADIUS 180 180 1) + ') + ifelse(1,eval(IDX1==LOOPIDX1),` + ElementLine(BRACKETLEFT LMAXY BRACKETLEFT BOARDTOP 1) + ElementLine(BRACKETLEFT BOARDTOP CURRRIGHT1 BOARDTOP 1) + ElementLine(CURRRIGHT1 BOARDTOP CURRRIGHT1 0 1) + + ElementArc(eval(BRACKETLEFT+SCREWBORDER) eval(LMAXY-SCREWBORDER) 125 125 0 360 1) + ElementArc(eval(BRACKETLEFT+SCREWBORDER) eval(BOARDTOP+SCREWBORDER) 125 125 0 360 1) + ') + ') + forloop(`IDX2',0,eval(CURRNUMPINS-1), + ` + define(`CURRX',`eval((PINDIST*IDX)+(ADDDIAMETER))') + define(`MINX',`eval(PINLEFT+CURRX)') + define(`MIDX',`eval(PINCENTER+CURRX)') + define(`MAXX',`eval(PINRIGHT+CURRX)') + define(`PINIDX',`eval(IDX+1+ADDSIDE)') + EDGECONN(MINX,MINY,MAXX,MINY,PENWIDTH,PINIDX,FLAG) + EDGECONN(MINX,MINY,MINX,MIDY,PENWIDTH,PINIDX,FLAG) + EDGECONN(MINX,MIDY,MIDX,MAXY,PENWIDTH,PINIDX,FLAG) + EDGECONN(MIDX,MINY,MIDX,MAXY,PENWIDTH,PINIDX,FLAG) + EDGECONN(MAXX,MINY,MAXX,MIDY,PENWIDTH,PINIDX,FLAG) + EDGECONN(MAXX,MIDY,MIDX,MAXY,PENWIDTH,PINIDX,FLAG) + define(`IDX',incr(IDX)) + ') + + ifelse(1,eval((NUMARRAYS>1)&&(IDX1<LOOPIDX1)),` + define(`ADDDIAMETER1',forloop(`IDX2',0,eval(IDX1), + ``arg'eval((IDX2*2)+3)+')0) + define(`ADDDIAMETER',eval(ADDDIAMETER1+(EDGEGAP*2)-PINDIST+PINWIDTH)) + ') + ') + define(`ADDSIDE',`TOTALPINS') + define(`FLAG',0x80) + ') + +)') + + + +define(`PKG_PCI5V_AVE_HEIGHT', `PKG_PCIPINARRAY(`$1', `$2', `$3', 2810,49,100,11)'); +define(`PKG_PCI5V_MIN_HEIGHT', `PKG_PCIPINARRAY(`$1', `$2', `$3', 1420,49,100,11)'); +define(`PKG_PCI5V_MAX_HEIGHT', `PKG_PCIPINARRAY(`$1', `$2', `$3', 4200,49,100,11)'); +define(`PKG_PCI5V_SMALL_HEIGHT', `PKG_PCIPINARRAY(`$1', `$2', `$3', 2063,49,100,11)'); + + + + + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/plcc.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,409 @@ +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: plcc.inc,v 1.3 2012/11/07 19:02:54 msokolov Exp $ +# +# PLCC packages +# + +# ------------------------------------------------------------------- +# ThanX to Johan Andersson (johan@homemail.com), modified by Thomas Nau +# the definition of a plcc package +# modified for correct pad numbering by Holm Tiffe +# +# modified 11-Dec-1999 Larry Doolittle <LRDoolittle@lbl.gov> +# to shorten the pads by 10 mils; PUSHOUT=5 PUSHIN=40 +# +# modified 22-Dec-1999 Larry Doolittle <LRDoolittle@lbl.gov> +# put back the 10 mils on the outside; PUSHOUT=5, PUSHIN=50 +# +# One last tweak 12-Jan-2000 LRD, now that the shop complained I +# didn't leave them any room to solder (looks like the 22-Dec +# change was backwards); PUSHOUT=20, PUSHIN=40 +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: additional border (will be ignored) +# +define(`PKG_PLCC', + `define(`NUMPINS', `$4') + ifelse(eval(NUMPINS = 32),1,`define(`QUARTER',7)',`define(`QUARTER', eval($4 /4))') + define(`OFFSET', eval((QUARTER +1) /2)) + define(`WIDTH', eval((QUARTER-1) *50 +2*75)) + ifelse(eval(NUMPINS = 32),1,`define(`SIDE',eval((NUMPINS-2*QUARTER)/2))', `define(`SIDE',QUARTER)') + define(`HEIGHT', eval((SIDE-1)* 50 + 2*75)) + define(`CENTER', eval(WIDTH / 2)) + define(`PUSHOUT', 20) # was 15 + define(`PUSHIN', 40) # was 50 +Element(0x00 "$1" "$2" "$3" 100 CENTER 0 100 0x00) +( + # top left half +define(`X', CENTER) +define(`Y', 0) +define(`count', 1) +forloop(`i', 1, OFFSET, + `PAD(X, eval(Y-PUSHOUT), X, eval(Y+PUSHIN), 20, count)' `define(`count', incr(count))' + `define(`X', eval(X-50))' + ) + + + # left row +define(`X', 0) +define(`Y', 75) +define(`count', eval(OFFSET+1)) +forloop(`i', 1, SIDE, + `PAD(eval(X-PUSHOUT), Y, eval(X+PUSHIN), Y, 20, count)' `define(`count', incr(count))' + `define(`Y', eval(Y+50))' + ) + + # bottom row +define(`X', 75) +define(`Y', HEIGHT) +forloop(`i', 1, QUARTER, + `PAD(X, eval(Y+PUSHOUT), X, eval(Y-PUSHIN), 20, count)' `define(`count', incr(count))' + `define(`X', eval(X+50))' +) + + # right row +define(`X', WIDTH) +define(`Y', eval(HEIGHT-75)) +forloop(`i', 1, SIDE, + `PAD(eval(X+PUSHOUT), Y, eval(X-PUSHIN), Y, 20, count)' `define(`count', incr(count))' + `define(`Y', eval(Y-50))' +) + + # top right row +define(`X', eval(WIDTH-75)) +define(`Y', 0) +forloop(`i', 1, eval(OFFSET-1), + `PAD(X, eval(Y-PUSHOUT), X, eval(Y+PUSHIN), 20, count)' `define(`count', incr(count))' + `ifelse(eval(count > NUMPINS), 1, `define(`count', 1)')' + `define(`X', eval(X-50))' +) + +# ElementLine(50 0 WIDTH 0 20) +# ElementLine(WIDTH 0 WIDTH WIDTH 20) +# ElementLine(WIDTH WIDTH 0 WIDTH 20) +# ElementLine(0 WIDTH 0 50 20) +# ElementLine(0 50 50 0 20) + +# Modified by Thomas Olson to eliminate silkscreen blobbing over pads. +# Approach one: eliminate ElementLine transgression over pads. leave corners +# only. + +define(`OLWIDTH', eval(WIDTH-50)) +define(`OLHEIGHT', eval(HEIGHT-50)) + + ElementLine(OLWIDTH 0 WIDTH 0 10) + ElementLine(WIDTH 0 WIDTH 50 10) + ElementLine(WIDTH OLHEIGHT WIDTH HEIGHT 10) + ElementLine(WIDTH HEIGHT OLWIDTH HEIGHT 10) + ElementLine(50 HEIGHT 0 HEIGHT 10) + ElementLine(0 HEIGHT 0 OLHEIGHT 10) + ElementLine(0 50 50 0 10) + +# Approach two: move outline to edge of pads. +# The outline should be 15 off. But since the pad algorithm +# is not making the square pads correctly I give it a total of 30 +# to clear the pads. + +# Try 40 mils, and parameterize it. 1/12/00 LRD +define(`NOSMUDGE', 40) +define(`OLWIDTH', eval(WIDTH+NOSMUDGE)) +define(`OLHEIGHT', eval(HEIGHT+NOSMUDGE)) + + ElementLine(50 -NOSMUDGE OLWIDTH -NOSMUDGE 10) + ElementLine(OLWIDTH -NOSMUDGE OLWIDTH OLHEIGHT 10) + ElementLine(OLWIDTH OLHEIGHT -NOSMUDGE OLHEIGHT 10) + ElementLine(-NOSMUDGE OLHEIGHT -NOSMUDGE 50 10) + ElementLine(-NOSMUDGE 50 50 -NOSMUDGE 10) + + ElementArc(CENTER 100 20 20 0 360 10) + + Mark(0 0) +)') + +# ------------------------------------------------------------------- +# the definition of a plcc package with through-hole socket +# +# for example, Assmann A-CCS##-{Z,G} series +# or mil-max 940-XX-XXX-24-000000 series. +# +# mil-max specifies 0.035" drill hole and 0.062" pad. +# Assman says 0.0315" hole. Also the mil-max outside +# dimensions are ever so slightly larger than Assmann so +# use those. See for example +# http://www.milmax.com/images/products/pdf/092.PDF +# +# modified for correct pin numbering by Holm Tiffe +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: additional border +# +define(`PKG_PLCC_SOCKET', + `define(`QUARTER', eval($4 /4)) + define(`OFFSET', eval((QUARTER +1) / 2)) + define(`BORDER', `$5') + define(`WIDTH', eval((OFFSET+1) *100 +2*BORDER)) + define(`CENTER', eval(WIDTH / 2)) + define(`NUMPINS', `$4') + define(`PADSIZE', `62') + define(`DRILL', `35') +Element(0x00 "$1" "$2" "$3" eval(BORDER+200) CENTER 0 100 0x00) + +# PLCC - 44 is a special case, pad 1 in inner row + +ifelse(eval(NUMPINS = 44 || NUMPINS = 28 || NUMPINS = 32), 1, `( + +define(`X',eval(CENTER+50)) +define(`Y',eval(BORDER+100)) +define(`count',1) + +ifelse(eval(NUMPINS=44),1,`define(`ltr',3)',`define(`ltr',2)') +ifelse(eval(NUMPINS=32),1,`define(`QUARTER',9)') + +# top left row +forloop(`i', 1, ltr, + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(eval(X-100), eval(Y-100), PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`X', eval(X-100))' +) + +#left row +define(`X',eval(X-100)) +forloop(`i', 1, eval((QUARTER-1)/2), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(eval(X+100), Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`Y', eval(Y+100))' +) +PIN(X, Y, PADSIZE, DRILL, count) +define(`count', incr(count)) + +# bottom row +define(`X',eval(X+100)) +define(`Y',eval(Y+100)) +forloop(`i', 1, eval(ltr*2-1), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(X, eval(Y-100), PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`X', eval(X+100))' +) +PIN(X, Y, PADSIZE, DRILL, count) +define(`count', incr(count)) + +# right row +define(`X',eval(X+100)) +define(`Y',eval(Y-100)) +forloop(`i', 1, eval((QUARTER-1)/2), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(eval(X-100), Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`Y', eval(Y-100))' +) +PIN(X, Y, PADSIZE, DRILL, count) +define(`count', incr(count)) + +# top rigth row +define(`X',eval(X-100)) +define(`Y',eval(Y-100)) +forloop(`i', 1, eval(ltr-1), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(X, eval(Y+100), PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`X', eval(X-100))' +) +PIN(X, Y, PADSIZE, DRILL, count) + +ifelse(eval(NUMPINS=32),1,`define(`HEIGHT',eval(WIDTH+100))',`define(`HEIGHT',WIDTH)') + ElementLine(0 0 WIDTH 0 20) + ElementLine(WIDTH 0 WIDTH HEIGHT 20) + ElementLine(WIDTH HEIGHT 0 HEIGHT 20) + ElementLine(0 HEIGHT 0 0 20) + ElementLine(0 100 100 0 10) + ElementLine(eval(CENTER-50) 0 CENTER 50 10) + ElementLine(CENTER 50 eval(CENTER+50) 0 10) + + Mark(CENTER BORDER) + + +#------------------------------------------------------------------------ +# all other sockets, currently 20,52,68 and 84 pins + +)', `( + +# the default case, Pad 1 is on outer top row, in the middle + + +#top left row + +define(`X',CENTER) +define(`Y',BORDER) +define(`count',1) +forloop(`i', 1, eval((QUARTER-1)/4), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(X, eval(Y+100), PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`X',eval(X-100))' +) +PIN(X, Y, PADSIZE, DRILL, count) +define(`count', incr(count)) + +# left row +define(`Y',eval(BORDER+100)) +define(`X',BORDER) +forloop(`i', 1, eval((QUARTER-1)/2), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(eval(X+100), Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`Y',eval(Y+100))' +) +PIN(X, Y, PADSIZE, DRILL, count) +define(`count', incr(count)) + +# bottom row +define(`X',eval(BORDER+100)) +define(`Y',eval(WIDTH-BORDER)) +forloop(`i', 1, eval((QUARTER-1)/2), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(X, eval(Y-100), PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`X',eval(X+100))' +) +PIN(X, Y, PADSIZE, DRILL, count) +define(`count', incr(count)) + +# right row +define(`X',eval(WIDTH-BORDER)) +define(`Y',eval(WIDTH-BORDER-100)) +forloop(`i', 1, eval((QUARTER-1)/2), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(eval(X-100), Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`Y',eval(Y-100))' +) +PIN(X, Y, PADSIZE, DRILL, count) +define(`count', incr(count)) + +#top right row + +define(`X',eval(WIDTH-BORDER-100)) +define(`Y',BORDER) +forloop(`i', 1, eval((QUARTER-1)/4), + `PIN(X, Y, PADSIZE, DRILL, count)' `define(`count', incr(count))' + `PIN(X, eval(Y+100), PADSIZE, DRILL, count)' `define(`count', incr(count))' + `define(`X',eval(X-100))' +) + + ElementLine(0 0 WIDTH 0 20) + ElementLine(WIDTH 0 WIDTH WIDTH 20) + ElementLine(WIDTH WIDTH 0 WIDTH 20) + ElementLine(0 WIDTH 0 0 20) + ElementLine(0 100 100 0 10) + ElementLine(eval(CENTER-50) 0 CENTER 50 10) + ElementLine(CENTER 50 eval(CENTER+50) 0 10) + + Mark(CENTER BORDER) + +)')') + +# New PLCC footprint by Michael Spacefalcon +# intended for use with Assmann SMT sockets. +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pins on the top and bottom sides (7 for PLCC32) +# $5: pins on the left and right sides (9 for PLCC32) +# $6: socket body size allowance in mils +define(`PKG_PLCC_SMTSOCKET', + ` +Element[0x00 "$1" "$2" "$3" 200000 200000 0 0 0 100 0x00] +( + # computations for the pads first + define(`step', 5000) + define(`halfC', eval(($4-1) * step / 2)) + define(`halfD', eval(($5-1) * step / 2)) + define(`padwidth', 3000) + define(`xpadfarend', eval(halfC + 9750)) # 195 mils / 2 + define(`xpadnearend', eval(xpadfarend - 7500)) + define(`ypadfarend', eval(halfD + 9750)) + define(`ypadnearend', eval(ypadfarend - 7500)) + + # fudge for the Gerber-style aperture silliness + define(`xpadfarendadj', eval(xpadfarend - padwidth / 2)) + define(`xpadnearendadj', eval(xpadnearend + padwidth / 2)) + define(`ypadfarendadj', eval(ypadfarend - padwidth / 2)) + define(`ypadnearendadj', eval(ypadnearend + padwidth / 2)) + define(`clearance', 1000) + define(`maskextra', 600) + + # now actually emit the pads + define(`pinno', 1) + forloop2(`x', 0, -halfC, -step, ` + Pad[x -ypadfarendadj x -ypadnearendadj + padwidth clearance eval(padwidth + maskextra) + "" "pinno" "square"] + define(`pinno', incr(pinno)) + ') + forloop2(`y', -halfD, halfD, step, ` + Pad[-xpadfarendadj y -xpadnearendadj y + padwidth clearance eval(padwidth + maskextra) + "" "pinno" "square"] + define(`pinno', incr(pinno)) + ') + forloop2(`x', -halfC, halfC, step, ` + Pad[x ypadfarendadj x ypadnearendadj + padwidth clearance eval(padwidth + maskextra) + "" "pinno" "square"] + define(`pinno', incr(pinno)) + ') + forloop2(`y', halfD, -halfD, -step, ` + Pad[xpadfarendadj y xpadnearendadj y + padwidth clearance eval(padwidth + maskextra) + "" "pinno" "square"] + define(`pinno', incr(pinno)) + ') + forloop2(`x', halfC, step, -step, ` + Pad[x -ypadfarendadj x -ypadnearendadj + padwidth clearance eval(padwidth + maskextra) + "" "pinno" "square"] + define(`pinno', incr(pinno)) + ') + + # now mark the board space for the socket body with silk + define(`silkX', eval(halfC + $6 * 100 / 2)) + define(`silkY', eval(halfD + $6 * 100 / 2)) + define(`corner', 7500) + define(`silkW', 1000) + ElementLine[-silkX -eval(silkY-corner) -eval(silkX-corner) -silkY silkW] + ElementLine[-eval(silkX-corner) -silkY silkX -silkY silkW] + ElementLine[silkX -silkY silkX silkY silkW] + ElementLine[silkX silkY -silkX silkY silkW] + ElementLine[-silkX silkY -silkX -eval(silkY-corner) silkW] +)') + +define(`PKG_PLCC20S', `PKG_PLCC_SMTSOCKET(`$1', `$2', `$3', 5, 5, 416)') +define(`PKG_PLCC28S', `PKG_PLCC_SMTSOCKET(`$1', `$2', `$3', 7, 7, 416)') +define(`PKG_PLCC32S', `PKG_PLCC_SMTSOCKET(`$1', `$2', `$3', 7, 9, 417)') +define(`PKG_PLCC44S', `PKG_PLCC_SMTSOCKET(`$1', `$2', `$3', 11, 11, 417)') +define(`PKG_PLCC52S', `PKG_PLCC_SMTSOCKET(`$1', `$2', `$3', 13, 13, 418)') +define(`PKG_PLCC68S', `PKG_PLCC_SMTSOCKET(`$1', `$2', `$3', 17, 17, 419)') +define(`PKG_PLCC84S', `PKG_PLCC_SMTSOCKET(`$1', `$2', `$3', 21, 21, 419)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/qfn.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,193 @@ +# -*- m4 -*- +# $Id: qfn.inc,v 1.2 2007/02/26 03:52:37 msokolov Exp $ +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 2003 Dan McMahill +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# +# +# QFN packages +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size (mm) +# $6: pad pitch (1/100 mm) +# $7: PCB pad width (1/100 mm) +# $8: Package pad length (1/100 mm) +# $9: Exposed paddle size, 0 for no exposed paddle (1/100 mm) + +define(`PKG_GENERIC_QFN', + ` + # number of pins on left/right sides (pin1 is upper pin on left side) + define(`LRPINS', eval($4 / 4)) + # number of pins on top/bottom sides + define(`TBPINS', eval(`$4' / 2 - LRPINS)) + # pin pitch (1/1000 mil) + define(`PITCH',eval(`$6'*100000/254)) + # y-coordinate for upper pin on left/right sides (1/1000 mil) + define(`LRYMAX', eval((LRPINS-1)*PITCH/2)) + # x-coordinate for right pin on top/bottom sides (1/1000 mil) + define(`TBXMAX', eval((TBPINS-1)*PITCH/2)) + # total horizontal package width (1/1000 mil) + define(`LRWIDTHMM', ifelse(0,`$5',`787',eval($5))) + define(`LRWIDTH', ifelse(0,`$5',`787',eval(`$5'*10000000/254))) + # total vertical package width (1/1000 mil) + define(`TBWIDTH',ifelse(0,`$5',`551',eval(`$5'*10000000/254))) + # how much pads extend beyond the package edge (1/1000 mil) (the 25 is 0.25 mm) + define(`EXTOUT', eval(25*100000/254)) + # how much pads extend inward from the package pad edge (1/1000 mil) + define(`EXTIN', eval(5*100000/254)) + # pad length/width (1/1000 mil) + define(`PADLENGTH', eval(`$8'*100000/254)) + define(`PADWIDTH', eval(`$7'*100000/254)) + # pad width (mil/100) + define(`PADWIDTHMIL100', eval(PADWIDTH/10)) + # min/max x coordinates for the pads on the left/right sides of the package (mil/100) + define(`LRXMAX',eval((LRWIDTH/2 + EXTOUT - PADWIDTH/2)/10)) + define(`LRXMIN',eval((LRWIDTH/2 -PADLENGTH - EXTIN + PADWIDTH/2)/10)) + # min/max y coordinates for the pads on the top/bottom sides of the package (mil/100) + define(`TBYMAX',eval((TBWIDTH/2 + EXTOUT - PADWIDTH/2)/10)) + define(`TBYMIN',eval((TBWIDTH/2 -PADLENGTH - EXTIN + PADWIDTH/2)/10)) + + # silkscreen width (mils/100) + define(`SILKW', 1000) + # how much the silk screen is moved away from the package (1/1000 mil) + define(`SILKEXT', eval(EXTOUT + SILKW*10/2 + 5*1000)) + # upper right corner for silk screen (mil/100) + define(`SILKX', eval((LRWIDTH/2 + SILKEXT )/10)) + define(`SILKY', eval((TBWIDTH/2 + SILKEXT )/10)) + # refdes text size (mil/100) + define(`TEXTSIZE', 100) + # x,y coordinates for refdes label (mil/100) + define(`TEXTX', -SILKX) + define(`TEXTY', eval(-SILKY - 1000 - TEXTSIZE/2)) + # square exposed paddle size (mil/100) + define(`EPSIZE', eval(`$9'*10000/254)) + + # width of the pad solder mask relief (1/100 mil). + # grow by 1.5 mils on each side + define(`PADMASK', eval(2*150 + PADWIDTHMIL100)) + + # width of the paddle soldermask relief (1/100 mil) + # grow by 200 mils on each side + define(`EPMASK', eval(2*200 + EPSIZE)) + +# element_flags, description, pcb-name, value, mark_x, mark_y, +# text_x, text_y, text_direction, text_scale, text_flags +Element[0x00000000 "$1" "$2" "$3" 0 0 TEXTX TEXTY 0 TEXTSIZE 0x00000000] +( + + +# Pad[X1, Y1, X2, Y3, width, clearance, +# soldermask, "pin name", "pin number", flags] + +# left row +define(`CURPIN', 1) +define(`idx',0) +forloop(`i', 1, LRPINS, + `define(`Y', `eval((-LRYMAX + PITCH*idx)/10)')' + `Pad[-LRXMAX Y -LRXMIN Y PADWIDTHMIL100 0 PADMASK "CURPIN" "CURPIN" 0x00000100]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# bottom row +define(`idx',0) +forloop(`i', 1, TBPINS, + `define(`X', `eval((-TBXMAX + PITCH*idx)/10)')' + `Pad[X TBYMAX X TBYMIN PADWIDTHMIL100 0 PADMASK "CURPIN" "CURPIN" 0x00000900]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# right row +define(`idx',0) +forloop(`i', 1, LRPINS, + `define(`Y', `eval(( LRYMAX - PITCH*idx)/10)')' + `Pad[LRXMAX Y LRXMIN Y PADWIDTHMIL100 0 PADMASK "CURPIN" "CURPIN" 0x00000100]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# top row +define(`idx',0) +forloop(`i', 1, TBPINS, + `define(`X', `eval((TBXMAX - PITCH*idx)/10)')' + `Pad[X -TBYMAX X -TBYMIN PADWIDTHMIL100 0 PADMASK "CURPIN" "CURPIN" 0x00000900]' + `define(`CURPIN', incr(CURPIN))' + `define(`idx',incr(idx))' +) + +# Exposed paddle (if this is an exposed paddle part) +ifelse(1, eval(EPSIZE>0), +# Pad(X1, Y1, X2, Y3, width, clearance, +# soldermask, "pin name", "pin number", flags) + Pad[0 0 0 0 EPSIZE 0 EPMASK "CURPIN" "CURPIN" 0x00000100] + define(`CURPIN', incr(CURPIN)) +) + +# Silk screen around package +ElementLine[ SILKX SILKY SILKX -SILKY SILKW] +ElementLine[ SILKX -SILKY -SILKX -SILKY SILKW] +ElementLine[-SILKX -SILKY -SILKX SILKY SILKW] +ElementLine[-SILKX SILKY SILKX SILKY SILKW] + +# Pin 1 indicator +ElementLine[-SILKX -SILKY eval(-SILKX - 1500) eval(-SILKY - 1500) SILKW] + +)') + +# ------------------------------------------------------------------- + +# The following macros take: +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size (mm) +# $6: exposed paddle size (1/100 mm). 0 for no exposed paddle + + +# For an exposed paddle package, the paddle for an 'n' pin package is pin 'n+1' + +# 0.8 mm pitch +define(`PKG_QFN_80', `PKG_GENERIC_QFN(`$1',`$2',`$3',`$4',`$5', `80',`42',`60', `$6')') +# 0.65 mm pitch +define(`PKG_QFN_65', `PKG_GENERIC_QFN(`$1',`$2',`$3',`$4',`$5', `65',`37',`60', `$6')') +# 0.50 mm pitch, 0.6 mm pad length +define(`PKG_QFN_50', `PKG_GENERIC_QFN(`$1',`$2',`$3',`$4',`$5', `50',`28',`60', `$6')') +# 0.50 mm pitch, 0.4 mm pad length +define(`PKG_QFN_50S',`PKG_GENERIC_QFN(`$1',`$2',`$3',`$4',`$5', `50',`28',`40', `$6')') +# 0.40 mm pitch +define(`PKG_QFN_40', `PKG_GENERIC_QFN(`$1',`$2',`$3',`$4',`$5', `40',`25',`60', `$6')') + + +# PKG_GENERIC_QFN +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size (mm) +# $6: pad pitch (1/100 mm) +# $7: PCB pad width (1/100 mm) +# $8: Package pad length (1/100 mm) +# $9: Exposed paddle size, 0 for no exposed paddle (1/100 mm) +# ------------------------------------------------------------------- +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/qfp.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,257 @@ +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: qfp.inc,v 1.2 2007/02/26 03:52:38 msokolov Exp $ +# +# QFP packages +# + +# ------------------------------------------------------------------- +# ThanX to Johan Andersson (johan@homemail.com), modified by Thomas Nau +# the definition of a plcc package for base code to make qfp package. +# modified for correct pad numbering by Holm Tiffe +# +# Code from plcc.inc modified by Thomas Olson to make this qfp.inc definition. +# Although in retrospec quad flat packs are more diverse than this algorithm will do. +# Many qfp are the same physical size but have more thus narrower pads. +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: additional border (will be ignored) +# +define(`PKG_OLD_QFP', + `define(`QUARTER', eval($4 /4)) + define(`OFFSET', eval((QUARTER +1) /2)) + define(`WIDTH', eval((QUARTER-1) *31 +2*42)) + define(`CENTER', eval(WIDTH / 2)) + define(`NUMPINS', `$4') +Element(0x00 "$1" "$2" "$3" 100 CENTER 0 100 0x00) +( + + # left row +define(`X', 0) +define(`Y', 42) +#define(`count', eval(OFFSET+1)) +define(`count', 1) +forloop(`i', 1, QUARTER, + `PAD(eval(X-65), Y, eval(X+5), Y, 20, count)' `define(`count', incr(count))' + `define(`Y', eval(Y+31))' + ) + + # bottom row +define(`X', 42) +define(`Y', WIDTH) +forloop(`i', 1, QUARTER, + `PAD(X, eval(Y+65), X, eval(Y-5), 20, count)' `define(`count', incr(count))' + `define(`X', eval(X+31))' +) + + # right row +define(`X', WIDTH) +define(`Y', eval(WIDTH-42)) +forloop(`i', 1, QUARTER, + `PAD(eval(X+65), Y, eval(X-5), Y, 20, count)' `define(`count', incr(count))' + `define(`Y', eval(Y-31))' +) + + # top row +define(`X', eval(WIDTH-42)) +define(`Y', 0) +forloop(`i', 1, QUARTER, + `PAD(X, eval(Y-65), X, eval(Y+5), 20, count)' `define(`count', incr(count))' + `ifelse(eval(count > NUMPINS), 1, `define(`count', 1)')' + `define(`X', eval(X-31))' +) + + ElementLine(28 0 WIDTH 0 10) + ElementLine(WIDTH 0 WIDTH WIDTH 10) + ElementLine(WIDTH WIDTH 0 WIDTH 10) + ElementLine(0 WIDTH 0 28 10) + ElementLine(0 28 28 0 10) + + ElementArc(80 80 20 20 0 360 10) + + Mark(0 0) +)') + +# ------------------------------------------------------------------- + + +# Yet another QFP Package family -- untested (but looks pretty) +# Concepts stolen from PLCC and older QFP macros above. +# December 1999, Larry Doolittle <LRDoolittle@lbl.gov> +# This is intended to be fully general, and replace all other QFP code. +# It can handle square or rectangular packages of variable pitch. +# It sings, it dances, it might even be made to handle PLCCs and +# the Motorola package outlines with those cool-looking tabs on the +# plastic. +# +# PKG_GEN_QFP is the general case, PKG_LQFP and PKG_QFP call it +# with different setup. +# PITCH pad center-to-center distance ***IN UNITS OF 0.1 MICROMETER*** +# (weird, I know, but this sets 1 mil=254 units exactly, so +# pitches defined in either Imperial or Metric may be used) +# PAD_WIDTH width of pad (mils) +# XPADS Number of pads in X direction +# YPADS Number of pads in Y direction +# (total number of pads is 2*(XPADS+YPADS) ) +# X_LENGTH X length in mils from end-to-end of the pads +# Y_LENGTH Y length in mils from end-to-end of the pads +# ISTART Where along the left row (YPADS long) to find pin 1. +# (generally ISTART=1 for pin 1 in the corner, but ISTART +# is 11 for some 84-pin square packages and 17 for some +# 132-pin square packages) +# +# Feb 3, 2000 LRD: allow XPADS == 0 to represent SOIC packages + +define(`PKG_GEN_QFP', + ` + define(`PX', eval((PITCH*(XPADS-1)+127)/254)) + define(`PY', eval((PITCH*(YPADS-1)+127)/254)) + define(`PHW', eval(PAD_WIDTH/2)) +Element(0x00 "$1" "$2" "$3" 100 0 0 100 0x00) +( + define(`count', 1) + + # left row, going down + define(`X_OUTER', PHW) + define(`X_INNER', eval(PAD_LENGTH-PHW)) + define(`Y0', eval((Y_LENGTH-PY)/2)) + forloop(`i', ISTART, YPADS, + `define(`Y', eval(Y0+(PITCH*(i-1)+127)/254) )' + `PAD(X_OUTER, Y, X_INNER, Y, PAD_WIDTH, count)' + `define(`count',incr(count))' + ) + + # bottom row, going right + ifelse(XPADS,0,,` + define(`Y_OUTER', eval(Y_LENGTH-PHW)) + define(`Y_INNER', eval(Y_LENGTH+PHW-PAD_LENGTH)) + define(`X0', eval((X_LENGTH-PX)/2)) + forloop(`i', 1, XPADS, + `define(`X', eval(X0+(PITCH*(i-1)+127)/254) )' + `PAD(X, Y_OUTER, X, Y_INNER, PAD_WIDTH, count)' + `define(`count',incr(count))' + )') + + # right row, going up + define(`X_OUTER', eval(X_LENGTH-PHW)) + define(`X_INNER', eval(X_LENGTH+PHW-PAD_LENGTH)) + define(`Y0', eval((Y_LENGTH+PY)/2)) + forloop(`i', 1, YPADS, + `define(`Y', eval(Y0-(PITCH*(i-1)+127)/254) )' + `PAD(X_OUTER, Y, X_INNER, Y, PAD_WIDTH, count)' + `define(`count',incr(count))' + ) + + # top row, going left + ifelse(XPADS,0,,` + define(`Y_OUTER', PHW) + define(`Y_INNER', eval(PAD_LENGTH+PHW-PAD_WIDTH)) + define(`X0', eval((X_LENGTH+PX)/2)) + forloop(`i', 1, XPADS, + `define(`X', eval(X0-(PITCH*(i-1)+127)/254) )' + `PAD(X, Y_OUTER, X, Y_INNER, PAD_WIDTH, count)' + `define(`count',incr(count))' + )') + + # left row, going down again, maybe + define(`X_OUTER', PHW) + define(`X_INNER', eval(PAD_LENGTH-PHW)) + define(`Y0', eval((Y_LENGTH-PY)/2)) + ifelse(ISTART,1,,`forloop(`i', 1, eval(ISTART-1), + `define(`Y', eval(Y0+(PITCH*(i-1)+127)/254) )' + `PAD(X_OUTER, Y, X_INNER, Y, PAD_WIDTH, count)' + `define(`count',incr(count))' + )') + + define(`NOSMUDGE', 10) + define(`SSOX', eval(NOSMUDGE+PAD_LENGTH)) + define(`SSOY', ifelse(XPADS,0,0,eval(NOSMUDGE+PAD_LENGTH))) + define(`PPX', eval(X_LENGTH-SSOX)) + define(`PPY', eval(Y_LENGTH-SSOY)) + ElementLine(SSOX SSOY PPX SSOY 8) + ElementLine(PPX SSOY PPX PPY 8) + ElementLine(PPX PPY SSOX PPY 8) + ElementLine(SSOX PPY SSOX SSOY 8) + + # Pin 1 Indicator + define(`Y1', ifelse(ISTART,1,eval(SSOY+40), + eval(Y0+(PITCH*(ISTART-1)+127)/254))) + ElementArc(eval(SSOX+40) Y1 20 20 0 360 10) + + # Moderately useful place for the Mark. This way, + # if the pins can line up with the grid, they do. + Mark(eval((X_LENGTH-PX)/2) eval((Y_LENGTH-PY)/2)) +)') + +# PKG_QFP: square quad flat pack, 0.8 mm pitch, based on PKG_GEN_QFP above +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: total number of pins (package is assumed square) +# This configuration should correspond to the old PKG_QFP, renamed +# PKG_OLD_QFP above for comparison. The two implementations have, +# among other things, different coordinate zeros. + +define(`PKG_QFP', + `define(`PITCH', 8000) + define(`PAD_WIDTH', 20) + define(`PAD_LENGTH', 90) + define(`XPADS', eval($4 /4)) + define(`YPADS', eval($4 /4)) + define(`X_LENGTH', eval((PITCH*(XPADS-1)+127)/254+232)) + define(`Y_LENGTH', X_LENGTH) + define(`ISTART', 1) + PKG_GEN_QFP($1, $2, $3)' +) + +# PKG_208_LQFP: leaded quad flat pack, 0.5 mm pitch, based on PKG_GEN_QFP above +# $1: canonical name +# $2: name on PCB +# $3: value +# This configuration based on a mechanical drawing of a +# Cirrus Logic EP7211 in a 208-Pin LQFP + +define(`PKG_208_LQFP', + `define(`PITCH', 5000) + define(`PAD_LENGTH', 60) + define(`PAD_WIDTH', 10) + define(`XPADS', 52) + define(`YPADS', 52) + define(`X_LENGTH', 1220) + define(`Y_LENGTH', 1220) + define(`ISTART', 1) + PKG_GEN_QFP($1, $2, $3)' +) + +# Interesting hack, this. pcb -> sh -> m4 -> tcl +# Refer to qfp-ui, a tcl program that should accompany this file. +# Search path for this puppy comes from QueryLibrary.sh, which +# I (LRD) patched to merge M4PATH into PATH +define(`PKG_MENU_QFP', + `esyscmd(qfp-ui "$1" "$2" "$3")' +) +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/qfp2.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,99 @@ +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: qfp2.inc,v 1.2 2007/02/26 03:52:40 msokolov Exp $ +# +# QFP packages +# + +# ------------------------------------------------------------------- +# ThanX to Johan Andersson (johan@homemail.com), modified by Thomas Nau +# the definition of a plcc package for base code to make qfp package. +# modified for correct pad numbering by Holm Tiffe +# +# Code from plcc.inc modified by Thomas Olson to make this qfp.inc definition. +# Although in retrospec quad flat packs are more diverse than this algorithm will do. +# Many qfp are the same physical size but have more thus narrower pads. +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: additional border (will be ignored) +# +define(`PKG_QFP2', + `define(`QUARTER', eval($4 /4)) + define(`OFFSET', eval((QUARTER +1) /2)) + define(`WIDTH', eval((QUARTER-1) *25 +2*50)) + define(`CENTER', eval(WIDTH / 2)) + define(`NUMPINS', `$4') +Element(0x00 "$1" "$2" "$3" 100 CENTER 0 100 0x00) +( + + # left row +define(`X', 0) +define(`Y', 50) +#define(`count', `eval(OFFSET+1)') +define(`count', 1) +forloop(`i', 1, QUARTER, + `PAD(eval(X-65), Y, eval(X+5), Y, 15, count)' `define(`count', incr(count))' + `define(`Y', eval(Y+25))' + ) + + # bottom row +define(`X', 50) +define(`Y', WIDTH) +forloop(`i', 1, QUARTER, + `PAD(X, eval(Y+65), X, eval(Y-5), 15, count)' `define(`count', incr(count))' + `define(`X', eval(X+25))' +) + + # right row +define(`X', WIDTH) +define(`Y', eval(WIDTH-50)) +forloop(`i', 1, QUARTER, + `PAD(eval(X+65), Y, eval(X-5), Y, 15, count)' `define(`count', incr(count))' + `define(`Y', eval(Y-25))' +) + + # top row +define(`X', eval(WIDTH-50)) +define(`Y', 0) +forloop(`i', 1, QUARTER, + `PAD(X, eval(Y-65), X, eval(Y+5), 15, count)' `define(`count', incr(count))' + `ifelse(eval(count > NUMPINS), 1, `define(`count', 1)')' + `define(`X', eval(X-25))' +) + + ElementLine(28 0 WIDTH 0 10) + ElementLine(WIDTH 0 WIDTH WIDTH 10) + ElementLine(WIDTH WIDTH 0 WIDTH 10) + ElementLine(0 WIDTH 0 28 10) + ElementLine(0 28 28 0 10) + + ElementArc(80 80 20 20 0 360 10) + + Mark(0 0) +)') + +# -------------------------------------------------------------------
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/qfpdj.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,152 @@ +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# Improvments by D.J. Barrow dj_barrow@ariasoft.ie +# Further improved by W. Kazubski <wk@ire.pw.edu.pl> +# +# RCS: $Id: qfpdj.inc,v 1.2 2007/02/26 03:52:40 msokolov Exp $ +# +# QFP packages +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size in mm (0 if rectangular 20x14 mm) +# $6: pad pitch in 1/100 mmm +# $7: pad thickness in 1/100 mmm +# $8: pad min offset ( edge nearest package ) +# $9: pad max offset ( edge furthest away from package ) +# $A: pin 1 in middle +# +define(`PKG_GENERIC_QFP', + `define(`QUARTER', ifelse(0,`$5',eval($4 * 3 / 10),eval($4 / 4))) + define(`QUARTER2', eval(`$4' / 2 - QUARTER)) + define(`OFFSET', eval((QUARTER +1) /2)) + define(`WIDTH', ifelse(0,`$5',`787',eval(`$5'*10000/254))) + define(`WIDTH2',ifelse(0,`$5',`551',eval(`$5'*10000/254))) + define(`PITCH',eval(`$6'*100000/254)) + define(`BORDER', eval((WIDTH-(QUARTER-1)*PITCH/1000)/2)) + define(`BORDER2', eval((WIDTH2-(QUARTER2-1)*PITCH/1000)/2)) + define(`CENTER', eval(WIDTH2 / 2)) + define(`NUMPINS', `$4') + define(`PADTHICKNESS',eval(`$7'*100/254)) + define(`PADMINOFFSET',eval(`$8'+PADTHICKNESS/2)) + define(`PADMAXOFFSET',eval(`$9'-PADTHICKNESS/2)) + define(`FARPIN', eval(WIDTH-BORDER)) + define(`FARPIN2',eval(WIDTH2-BORDER2)) + define(`PIN1INMIDDLE',`$A') + define(`EDGECUT',ifelse(1,eval(PIN1INMIDDLE),`0',`28')) + define(`STARTPIN',ifelse(1,eval(PIN1INMIDDLE),eval(((QUARTER+1)/2)+1),`1')) + define(`CIRCLECENTRE',ifelse(1,eval(PIN1INMIDDLE),eval(WIDTH/2),35)) +Element(0x00 "$1" "$2" "$3" 100 CENTER 0 100 0x00) +( + + # left row +define(`X', 0) +define(`QFPPIN',`STARTPIN') +define(`idx',0) +forloop(`i', 1, QUARTER, + `define(`Y', eval(BORDER+((PITCH*idx)/1000)))' + `PAD(eval(X-PADMAXOFFSET), Y, eval(X-PADMINOFFSET), Y, PADTHICKNESS, QFPPIN)' + `define(`QFPPIN', incr(QFPPIN))' + `define(`idx',incr(idx))' +) + + # bottom row +define(`Y', WIDTH) +define(`idx',0) +forloop(`i', 1, QUARTER2, + `define(`X', eval(BORDER2+((PITCH*idx)/1000)))' + `PAD(X, eval(Y+PADMAXOFFSET), X, eval(Y+PADMINOFFSET), PADTHICKNESS, QFPPIN)' + `define(`QFPPIN', incr(QFPPIN))' + `define(`idx',incr(idx))' +) + + # right row +define(`X', WIDTH2) +define(`idx',0) +forloop(`i', 1, QUARTER, + `define(`Y', eval(FARPIN-((PITCH*idx)/1000)))' + `PAD(eval(X+PADMAXOFFSET), Y, eval(X+PADMINOFFSET), Y, PADTHICKNESS, QFPPIN)' + `define(`QFPPIN', incr(QFPPIN))' + `define(`idx',incr(idx))' +) + + # top row +define(`idx',0) +define(`Y', 0) +forloop(`i', 1, QUARTER2, + `define(`X',eval(FARPIN2-((PITCH*idx)/1000)))' + `PAD(X, eval(Y-PADMAXOFFSET), X, eval(Y-PADMINOFFSET), PADTHICKNESS, QFPPIN)' + `define(`QFPPIN', incr(QFPPIN))' + `ifelse(eval(QFPPIN > NUMPINS), 1, `define(`QFPPIN', 1)')' + `define(`idx',incr(idx))' +) + + ElementLine(EDGECUT 0 WIDTH2 0 10) + ElementLine(WIDTH2 0 WIDTH2 WIDTH 10) + ElementLine(WIDTH2 WIDTH 0 WIDTH 10) + ElementLine(0 WIDTH 0 EDGECUT 10) + ElementLine(0 EDGECUT EDGECUT 0 10) + ElementArc(CIRCLECENTRE 35 10 10 0 360 10) + + Mark(0 0) +)') + +# ------------------------------------------------------------------- +# ThanX to Johan Andersson (johan@homemail.com), modified by Thomas Nau +# the definition of a plcc package for base code to make qfp package. +# modified for correct pad numbering by Holm Tiffe +# +# Code from plcc.inc modified by Thomas Olson to make this qfp.inc definition. +# Although in retrospec quad flat packs are more diverse than this algorithm will do. +# Many qfp are the same physical size but have more thus narrower pads. +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: body size in mm +# $6: pad pitch in 1/100 mmm +# $7: pad thickness +# + +# pins 1.9-2.1mm long +define(`PKG_QFP_100',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5',`100',`50',`20',`100',`0')') +define(`PKG_QFP_80L',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `80',`50',`20',`100',`0')') +define(`PKG_QFP_65L',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `65',`40',`20',`100',`0')') +define(`PKG_QFP_50L',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `50',`28',`20',`100',`0')') + +# pins 1.6mm long +define(`PKG_QFP_80', `PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `80',`40',`20', `80',`0')') +define(`PKG_QFP_65', `PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `65',`40',`20', `80',`0')') +define(`PKG_QFP_50', `PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `50',`28',`20', `80',`0')') + +# pins 1mm long +define(`PKG_LQFP_80',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `80',`40', `5', `50',`0')') +define(`PKG_LQFP_65',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `65',`40', `5', `50',`0')') +define(`PKG_LQFP_50',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `50',`28', `5', `50',`0')') +define(`PKG_LQFP_40',`PKG_GENERIC_QFP(`$1',`$2',`$3',`$4',`$5', `40',`25', `5', `50',`0')') + +# ------------------------------------------------------------------- +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/resistor_adjust.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,83 @@ +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# + +#----------------------------------------------------------------- +# ma librairie --- C. PETER 14 11 99 +# +# l'origine 0 0 est en haut a gauche (x vers la droite, y vers le bas) +# Element(0x00 "$1" "$2" "$3" pos_x_text pos_y_text ? taille_text 0x00) +# PIN(pos_x, pos_y, diametre, percage, type?) type : 1 carre, 2 ronde +# ElementLine(debut_x debut_y fin_x fin_y epaisseur-trait) +# ElementArc(centre_x centre_y rayon_x rayon_y debut_arc fin_arc ep-trait) +# Mark fixe la position du curseur lors de la creation des composants + +# ------------------------------------------------------------------- +# R_AJ_H +# Pin 1 is 1, 2 is c, 3 is 2 +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +define(`PKG_R_AJ_H', +`Element(0x00 "$1" "$2" "$3" 100 325 0 100 0x00) +( + PIN(50, 450, 80, 30, 1) + PIN(250, 450, 80, 30, 3) + PIN(150, 50, 80, 30, 2) + ElementLine(0 150 0 500 20) + ElementLine(0 500 300 500 20) + ElementLine(300 500 300 150 20) + ElementArc(150 150 100 100 0 360 10) + ElementArc(150 150 150 150 0 -180 20) + Mark(50 450) +)') + + +# ------------------------------------------------------------------- +# R_AJ_V +# Pin 1 is 1, 2 is c, 3 is 2 +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +define(`PKG_R_AJ_V', +`Element(0x00 "$1" "$2" "$3" 100 45 0 100 0x00) +( + PIN(50, 50, 80, 30, 1) + PIN(250, 50, 80, 30, 3) + PIN(150, 0, 80, 30, 2) + ElementLine(0 0 0 100 20) + ElementLine(0 0 300 0 20) + ElementLine(300 0 300 100 20) + ElementLine(0 100 300 100 20) + Mark(50 50) +)') + + +# ------------------------------------------------------------------- + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/rules.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,53 @@ +# +# $Id: rules.inc,v 1.1 2007/02/19 05:28:38 msokolov Exp $ +# +# design rule definitions -- +# tune design rules here +# +# revisions: +# Oct 12 2002 - Egil Kvaleberg <egil@kvaleberg.no> +# Initial version +# +# NOTE: The HOLE specification is the diameter of the finished hole. +# For through-hole plated PCBs, the actual drill dimension will be +# be larger. How much depends on process parameters +# + +# +# pads for comopnents with thin pins (e.g TO92) +# +define(`rPAD1', 50) +define(`rHOLE1', 24) + +# +# pads for components on 100mil pitch +# hole 2 for ICs etc +# hole 2c for headers etc. with square pins +# +# NOTE: rPAD2 should really be 62mil +# +define(`rPAD2', 60) +define(`rHOLE2', 28) +define(`rHOLE2c', 40) + +# +# pads for larger transistors +# +define(`rPAD3', 80 ) +define(`rHOLE3', 50) + +# +# 3mm pads for mounting +# BUG: drill is bad +# +define(`rPAD4', 120) +define(`rHOLE4', 80) + +# +# standard silkscreen line +# thin, fat, fatter +# +define(`rSILK', 10) +define(`rSILK2', 20) +define(`rSILK3', 30) +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/smt.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,763 @@ +# -*- m4 -*- +# $Id: smt.inc,v 1.5 2011/07/30 05:19:45 msokolov Exp $ +# +# surface mounted components +# +# revisions: +# Oct 10 2002 - Egil Kvaleberg <egil@kvaleberg.no> +# Initial stub +# +# + + +# ------------------------------------------------------------------- +# +# internal: general purpose two pole surface mount +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: length of component in mil +# $5: width of component in mil, also width of pad +# $6: length of pad, expressed in percent of component length +# $7: 1 if pin 1 should be marked +# +define(`COMMON_SMT_2PAD_MIL', + `define(`sizX', `$4') + define(`sizY', `$5') + define(`metalX', eval((sizX * $6) / 100)) + define(`addFRAME', eval(sizY / 5)) + define(`addTIN', eval(sizY / 5)) + define(`padX', eval(metalX + 2*addTIN)) + define(`padY', eval(sizY + 2*addTIN)) + define(`width', eval(sizX/2 + addFRAME + addTIN)) + define(`height', eval(sizY/2 + addFRAME + addTIN)) + define(`centerX', eval((sizX - padX + 2*addTIN)/2)) + define(`silkW', ifelse(eval(sizY >= 50), 1, 10, eval(sizY/5))) + # how much to grow the pads by for soldermask + define(`maskGrow', 3) + # clearance from planes + define(`clearance', 10) +Element(0x00 "$1" "`$2'" "$3" 0 0 eval(width + 20) 0 3 100 0x00) +( + ifelse(eval($7 > 0), 1, + `ElementLine(eval(-width-silkW) eval(-height + addFRAME) eval(-width-silkW) eval(height-addFRAME) eval(2*silkW)) + ElementLine(eval(-width-silkW) eval( height - addFRAME) eval(-width + padX/2 -silkW) height silkW) + ElementLine(eval(-width + padX/2 - silkW) height width height silkW) + ElementLine(width height width -height silkW) + ElementLine(width -height eval(-width + padX/2 -silkW) -height silkW) + ElementLine(eval(-width + padX/2 -silkW) -height eval(-width-silkW) eval(-height + addFRAME) silkW) + ', + `ElementLine(-width -height -width height silkW) + ElementLine(-width height width height silkW) + ElementLine(width height width -height silkW) + ElementLine(width -height -width -height silkW) + ') + + ifelse(eval(padX > padY), 1, + `Pad(eval((-2*centerX - padX + padY)/2) 0 + eval((-2*centerX + padX - padY)/2) 0 + padY eval(2*clearance) eval(padY + 2*maskGrow) "1" "1" 0x00000100) + Pad(eval(( 2*centerX - padX + padY)/2) 0 + eval(( 2*centerX + padX - padY)/2) 0 + padY eval(2*clearance) eval(padY + 2*maskGrow) "2" "2" 0x00000100) + ', + `Pad(-centerX eval((-padY+padX)/2) + -centerX eval((padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "1" "1" 0x00000100) + Pad(centerX eval((-padY+padX)/2) + centerX eval((padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "2" "2" 0x00000100) + ') + +)') + +# ------------------------------------------------------------------- +# +# internal: general purpose two pole surface mount +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pad X (size of pad in direction perpendicular to axis of part) [1/100 mm] +# $5: pad Y (size of pad in direction parallel to axis of part) [1/100 mm] +# $6: pad center to center spacing [1/100 mm] +# $7: courtyard size in direction parallel to axis of part [1/100 mm] (V1) +# $8: courtyard size in direction perpendicular to axis of part [1/100 mm] (V2) +# $9: length of silk screen line [1/100 mm] (R1) +# $A: spacing of silk screen line [1/100 mm] (R2) +# +define(`PKG_SMT_2PAD_MM100', + # grab the input values and convert to 1/100 mil + `define(`X', eval(($4 * 10000)/254)) + define(`Y', eval(($5 * 10000)/254)) + define(`C', eval(($6 * 10000)/254)) + define(`V1', eval(($7 * 10000)/254)) + define(`V2', eval(($8 * 10000)/254)) + define(`R1', eval(($9 * 10000)/254)) + define(`R2', eval(($A * 10000)/254)) + # how much to grow the pads by for soldermask [1/100 mil] + define(`maskGrow', 300) + # clearance from planes [1/100 mil] + define(`clearance', 1000) + # silk screen width [1/100 mil] + define(`SILKW', `800') + # courtyard silk screen width [1/100 mil] + define(`CYW', `100') +# element_flags, description, pcb-name, value, mark_x, mark_y, +# text_x, text_y, text_direction, text_scale, text_flags +Element[0x00000000 "$1" "`$2'" "$3" 0 0 -3150 -3150 0 100 ""] +( +# +# Pad[x1, y1, x2, y2, thickness, clearance, mask, name , pad number, flags] + ifelse(eval(Y > X), 1, + `Pad[eval( (-1*C - (Y - X))/2) 0 + eval( (-1*C + (Y - X))/2) 0 + X eval(2*clearance) eval(X + 2*maskGrow) "1" "1" "square"] + Pad[eval( ( C - (Y - X))/2) 0 + eval( ( C + (Y - X))/2) 0 + X eval(2*clearance) eval(X + 2*maskGrow) "2" "2" "square"] + ', + `Pad[eval( -1*C/2 ) eval(-(X-Y)/2) + eval( -1*C/2 ) eval( (X-Y)/2) + Y eval(2*clearance) eval(Y + 2*maskGrow) "1" "1" "square"] + Pad[eval( C/2 ) eval(-(X-Y)/2) + eval( C/2 ) eval( (X-Y)/2) + Y eval(2*clearance) eval(Y + 2*maskGrow) "2" "2" "square"] + ') + + ifelse(eval(R1 > 0), 1, + `ElementLine[eval(-1*R1/2) eval(-1*R2/2) eval(R1/2) eval(-1*R2/2) SILKW] + ElementLine[eval(-1*R1/2) eval( R2/2) eval(R1/2) eval( R2/2) SILKW] + ',) + +# +# This draws a 1 mil placement courtyard outline in silk. It should probably +# not be included since you won't want to try and fab a 1 mil silk line. Then +# again, it is most useful during parts placement. It really is time for some +# additional non-fab layers... +` +# ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(-1*V1/2) eval( V2/2) CYW] +# ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval( V1/2) eval(-1*V2/2) CYW] +# ElementLine[eval( V1/2) eval( V2/2) eval( V1/2) eval(-1*V2/2) CYW] +# ElementLine[eval( V1/2) eval( V2/2) eval(-1*V1/2) eval( V2/2) CYW] + +)') + +# ------------------------------------------------------------------- +# +# Hack by Michael Sokolov: an attempt to make footprints just like +# PKG_SMT_2PAD_MM100, but with silk screen like it used to be with +# PKG_SMT_2PAD_MIL. +# +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pad X (size of pad in direction perpendicular to axis of part) [1/100 mm] +# $5: pad Y (size of pad in direction parallel to axis of part) [1/100 mm] +# $6: pad center to center spacing [1/100 mm] +# $7: courtyard size in direction parallel to axis of part [1/100 mm] (V1) +# $8: courtyard size in direction perpendicular to axis of part [1/100 mm] (V2) +# $9: silk line with *in PCB units* [1/100 mil] +# +define(`PKG_SMT_2PAD_MS', + # grab the input values and convert to 1/100 mil + `define(`X', eval(($4 * 10000)/254)) + define(`Y', eval(($5 * 10000)/254)) + define(`C', eval(($6 * 10000)/254)) + define(`V1', eval(($7 * 10000)/254 + $9)) + define(`V2', eval(($8 * 10000)/254 + $9)) + # how much to grow the pads by for soldermask [1/100 mil] + define(`maskGrow', 300) + # clearance from planes [1/100 mil] + define(`clearance', 1000) + # courtyard silk line width [1/100 mil] + define(`CYW', $9) +# element_flags, description, pcb-name, value, mark_x, mark_y, +# text_x, text_y, text_direction, text_scale, text_flags +Element[0x00000000 "$1" "`$2'" "$3" 0 0 -3150 -3150 0 100 ""] +( +# +# Pad[x1, y1, x2, y2, thickness, clearance, mask, name , pad number, flags] + ifelse(eval(Y > X), 1, + `Pad[eval( (-1*C - (Y - X))/2) 0 + eval( (-1*C + (Y - X))/2) 0 + X eval(2*clearance) eval(X + 2*maskGrow) "1" "1" "square"] + Pad[eval( ( C - (Y - X))/2) 0 + eval( ( C + (Y - X))/2) 0 + X eval(2*clearance) eval(X + 2*maskGrow) "2" "2" "square"] + ', + `Pad[eval( -1*C/2 ) eval(-(X-Y)/2) + eval( -1*C/2 ) eval( (X-Y)/2) + Y eval(2*clearance) eval(Y + 2*maskGrow) "1" "1" "square"] + Pad[eval( C/2 ) eval(-(X-Y)/2) + eval( C/2 ) eval( (X-Y)/2) + Y eval(2*clearance) eval(Y + 2*maskGrow) "2" "2" "square"] + ') + + ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(-1*V1/2) eval( V2/2) CYW] + ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval( V1/2) eval(-1*V2/2) CYW] + ElementLine[eval( V1/2) eval( V2/2) eval( V1/2) eval(-1*V2/2) CYW] + ElementLine[eval( V1/2) eval( V2/2) eval(-1*V1/2) eval( V2/2) CYW] + +)') + +# ------------------------------------------------------------------- +# +# +# general purpose 3 pole surface mount +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: outer pad width (mil) (in direction perpendicular to part) +# $5: outer pad length (mil) (in direction parallel with part) +# $6: outer pad spacing (mil) (center to center) +# $7: inner pad width (mil) (in direction perpendicular to part) +# $8: inner pad length (mil) (in direction parallel with part) +# $9: distance from edge of pad to silk (mil) (in direction +# perpendicular to part) +# $A: distance from edge of pad to silk (mil) (in direction +# parallel with part) +# $B: Set to "no" to skip silk screen on the sides of the part +define(`COMMON_SMT_3PAD_MIL', + ` + define(`PADW', `$4') + define(`PADL', `$5') + define(`PADS', `$6') + define(`PADW2',`$7') + define(`PADL2',`$8') + define(`SLKW', `$9') + define(`SLKL', `$A') + + # silk screen width (mils) + define(`SILKW', `10') + + # silk screen bounding box + define(`XMIN', eval( -PADS/2 - PADL/2 - SLKL - SILKW/2)) + define(`XMAX', eval( PADS/2 + PADL/2 + SLKL + SILKW/2)) + define(`YMIN', eval(-PADW2/2 - SLKW - SILKW/2)) + define(`YMAX', eval( PADW2/2 + SLKW + SILKW/2)) + define(`SKIP_SILK', `$B') + + +Element(0x00 "$1" "`$2'" "$3" eval(XMIN+20) eval(YMAX+20) 0 100 0x00) +( + ifelse(0, eval(PADW>PADL), + # Pads which have the perpendicular pad dimension less + # than or equal to the parallel pad dimension + Pad(eval(-1*( PADS + PADL - PADW)/2) 0 + eval((-1*PADS + PADL - PADW)/2) 0 eval(PADW) "1" 0x100) + Pad(eval(-1*(-1*PADS + PADL - PADW)/2) 0 + eval(( PADS + PADL - PADW)/2) 0 eval(PADW) "3" 0x100) + , + # Pads which have the perpendicular pad dimension greater + # than or equal to the parallel pad dimension + Pad(eval(-1*PADS/2) eval(-1*(PADW - PADL)/2) + eval(-1*PADS/2) eval((PADW - PADL)/2) eval(PADL) "1" 0x100) + Pad(eval( PADS/2) eval(-1*(PADW - PADL)/2) + eval( PADS/2) eval((PADW - PADL)/2) eval(PADL) "3" 0x100) + ) + + ifelse(0, eval(PADW2>PADL2), + # Pads which have the perpendicular pad dimension less + # than or equal to the parallel pad dimension + Pad(eval((-PADL2 + PADW2)/2) 0 + eval(( PADL2 - PADW2)/2) 0 PADW2 "2" 0x100) + , + # Pads which have the perpendicular pad dimension greater + # than or equal to the parallel pad dimension + Pad(0 eval((-PADW2 + PADL2)/2) + 0 eval(( PADW2 - PADL2)/2) PADL2 "2" 0x100) + ) + + # silk screen + # ends + ElementLine(XMIN YMIN XMIN YMAX SILKW) + ElementLine(XMAX YMAX XMAX YMIN SILKW) + # sides +ifelse(SKIP_SILK,"no", + #skip side silk + , + ElementLine(XMIN YMIN XMAX YMIN SILKW) + ElementLine(XMAX YMAX XMIN YMAX SILKW) +) + # Mark the common centroid of the part + Mark(0 0) +)') + + +# +# ------------------------------------------------------------------- +# +# SOT23 style transistor: 3, 4, 5 or 6 pins +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing, lengthwise, mil +# $5: pin spacing across, in mil +# $6: size of pad, in percent of spacing across +# $7: pin numbers, "abc", where a is lower left, b is lower right, c is upper +# if "abcd", c is upper right, d is upper left, and a is a wider pad +# +define(`COMMON_SMT_TRANSISTOR_MIL', + `define(`spaceX', `$4') # 78 for SOT23 + define(`spaceY', `$5') # 82 for SOT23 + define(`padY', eval((spaceY * $6) / 100)) # 41 for SOT23 + define(`padX', ifelse(eval(len(`$7') >= 5), 1, + eval((spaceX * 31) / 100), + eval((padY * 85) / 100) + )) # 34 for SOT23, 24 for SOT25 + define(`addFRAME', eval(padY / 5)) + define(`maxX', eval(2*addFRAME+spaceX+padX)) + define(`maxY', eval(2*addFRAME+spaceY+padY)) + define(`centerX', eval(maxX / 2)) + define(`centerY1', eval(addFRAME + padY/2)) + define(`centerX1', eval(addFRAME + padX/2)) + define(`deltaY', eval((padY-padX)/2)) + define(`silkW', ifelse(eval(spaceY >= 50), 1, 10, eval(spaceY/5))) + define(`indeX', `0') + +Element(0x00 "$1" "`$2'" "$3" eval(maxX+20) 0 3 100 0x00) +( + ElementLine(0 0 0 maxY silkW) + ElementLine(0 maxY maxX maxY silkW) + ElementLine(maxX maxY maxX 0 silkW) + ElementLine(maxX 0 0 0 silkW) + + # 1st side, 1st pin + ifelse(len(`$7'), 4, + `# extra width + Pad(eval(centerX1+deltaY) eval(centerY1+spaceY) + eval(centerX1+2*deltaY) eval(centerY1+spaceY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + ', + `Pad(centerX1 eval(centerY1+spaceY-deltaY) + centerX1 eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + ') + define(`indeX',incr(indeX)) + + # 1st side, 2nd pin + ifelse(eval(len(`$7') == 6), 1, + `Pad(centerX eval(centerY1+spaceY-deltaY) + centerX eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + ') + + # 1st side, 3rd pin + Pad(eval(centerX1+spaceX) eval(centerY1+spaceY-deltaY) + eval(centerX1+spaceX) eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + + # 2nd side, 3rd pin + ifelse(eval(len(`$7') >= 4), 1, + `Pad(eval(centerX1+spaceX) eval(centerY1-deltaY) + eval(centerX1+spaceX) eval(centerY1+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + ') + + # 2nd side, 2nd pin + ifelse(eval(len(`$7') != 4), 1, + `Pad(centerX eval(centerY1-deltaY) + centerX eval(centerY1+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + ') + + # 2nd side, 1st pin + ifelse(eval(len(`$7') >= 4), 1, + `Pad(centerX1 eval(centerY1-deltaY) + centerX1 eval(centerY1+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + ') + + Mark(centerX1 eval(centerY1+spaceY)) +)') +# +# ------------------------------------------------------------------- +# +# SOT223 style transistor, multiple pins on one side, large pin on other side +# supports 2+1, 3+1 and 4+1 pins +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing, lengthwise, mil +# $5: pin spacing across, in mil +# $6: size of pad, in percent of spacing across +# $7: pin numbers, "abcd", where abc is three pins on one side, d the extra pin +# +define(`COMMON_SMT_TRANSISTORX_MIL', + `define(`spaceX', `$4') + define(`spaceY', `$5') + define(`padY', eval((spaceY * $6) / 100)) + define(`padX', ifelse(eval(len(`$7') >= 5), 1, + eval((spaceX * 21) / 100), + eval((spaceX * 31) / 100) + )) + define(`addFRAME', eval(padY / 5)) + define(`maxX', eval(2*addFRAME+spaceX+padX)) + define(`maxY', eval(2*addFRAME+spaceY+padY)) + define(`centerX', eval(maxX / 2)) + define(`centerY1', eval(addFRAME + padY/2)) + define(`centerX1', eval(addFRAME + padX/2)) + define(`deltaY', eval((padY-padX)/2)) + define(`silkW', ifelse(eval(spaceY >= 50), 1, 10, eval(spaceY/5))) + define(`indeX', `0') + +Element(0x00 "$1" "`$2'" "$3" eval(maxX+20) 0 3 100 0x00) +( + ElementLine(0 0 0 maxY silkW) + ElementLine(0 maxY maxX maxY silkW) + ElementLine(maxX maxY maxX 0 silkW) + ElementLine(maxX 0 0 0 silkW) + + # 1st pin on pin side + Pad(centerX1 eval(centerY1+spaceY-deltaY) + centerX1 eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + + ifelse(eval(len(`$7') == 4), 1, + `Pad(centerX eval(centerY1+spaceY-deltaY) + centerX eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + ') + ifelse(eval(len(`$7') == 5), 1, + `Pad(eval(centerX1+spaceX/3) eval(centerY1+spaceY-deltaY) + eval(centerX1+spaceX/3) eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + Pad(eval(centerX1+2*spaceX/3) eval(centerY1+spaceY-deltaY) + eval(centerX1+2*spaceX/3) eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + ') + + # last pin on pin side + Pad(eval(centerX1+spaceX) eval(centerY1+spaceY-deltaY) + eval(centerX1+spaceX) eval(centerY1+spaceY+deltaY) + padX "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + define(`indeX',incr(indeX)) + + # extra wide pin on opposite side + Pad(eval(centerX+spaceX/4) centerY1 + eval(centerX-spaceX/4) centerY1 + padY "substr(`$7',indeX,1)" "substr(`$7',indeX,1)" 0x100) + + Mark(centerX1 eval(centerY1+spaceY)) +)') +# +# ------------------------------------------------------------------- +# +# +# definition of a SMT dual inline package of any size +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: width of component itself in mils (228 for SO) -> 261 +# $6: pin spacing in 1/100 mils (500 for SO) +# $7: pad fatness in mils (20 for SO) +# $8: pad basic length in mils, will add extra tin here (50 for SO) +# +define(`COMMON_SMT_DUALINLINE', + `define(`pinCOUNT', `$4') + define(`pinS100', `$6') + define(`padY', `$7') + define(`addTIN', eval(padY / 5)) + define(`maxX', eval($5 + 2*addTIN)) + define(`padX', eval($8 + 2*addTIN)) + define(`maxY', eval((pinCOUNT/2 * pinS100) / 100)) + define(`lowX1', eval(padY/2)) + define(`highX1', eval(padX-padY)) + define(`lowX2', eval(maxX - (padX-padY))) + define(`highX2', eval(maxX - padY/2)) + define(`centerX', eval(maxX / 2)) +Element(0x00 "$1" "`$2'" "$3" eval(centerX + 20) 50 3 100 0x00) +( + forloop(`i', 1, eval(pinCOUNT/2), + `PAD(lowX1, eval((i*pinS100 - pinS100/2)/100), + highX1, eval((i*pinS100 - pinS100/2)/100), padY, i) + ') + forloop(`i', 1, eval(pinCOUNT/2), + `PAD(lowX2, eval(maxY - (i*pinS100 - pinS100/2)/100), + highX2, eval(maxY - (i*pinS100 - pinS100/2)/100), padY, eval(i + pinCOUNT/2)) + ') + ElementLine(0 0 eval(centerX - pinS100/200) 0 rSILK) + ElementArc(centerX 0 eval(pinS100/200) eval(pinS100/200) 0 180 rSILK) + ElementLine(eval(centerX + pinS100/200) 0 maxX 0 rSILK) + ElementLine(maxX 0 maxX maxY rSILK) + ElementLine(maxX maxY 0 maxY rSILK) + ElementLine(0 maxY 0 0 rSILK) + Mark(eval(padX/2) eval(pinS100/200)) +)') + + +# +# ------------------------------------------------------------------- +# +# general purpose two pole surface mount +# size args for a 0805 is 8,5 for 0402 is 4,2 etc +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: length of component in mil +# $5: width of component in mil +# +define(`PKG_SMT_2PAD_MIL', + `COMMON_SMT_2PAD_MIL(`$1', `$2', `$3', `$4', `$5', 20, 0)') +# +# general purpose two pole surface mount, pin 1 is marked +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: length of component in 1/10 mm +# $5: width of component in 1/10 mm +# +define(`PKG_SMT_2PAD_EIA', + `COMMON_SMT_2PAD_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 20, 1)') +# +# +# general purpose diode surface mount, pin 1 is marked +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: length of component in 1/10 mm +# $5: width of component in 1/10 mm +# +define(`PKG_SMT_DIODE', + `COMMON_SMT_2PAD_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 30, 1)') +# +# +# diode in transistor housing, 2 active pins, 1 is cathode, 2 is anode +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing lengthwise in 1/10 mm +# $5: pin spacing across in 1/10 mm +# +define(`PKG_SMT_TRANSISTOR2', + `COMMON_SMT_TRANSISTOR_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 50, `231')') +# +# +# +# general purpose transistor, 3 pins +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing lengthwise in 1/10 mm +# $5: pin spacing across in 1/10 mm +# +define(`PKG_SMT_TRANSISTOR3', + `COMMON_SMT_TRANSISTOR_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 50, `123')') +# +# +# general purpose transistor, 4 pins +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing lengthwise in 1/10 mm +# $5: pin spacing across in 1/10 mm +# +define(`PKG_SMT_TRANSISTOR4', + `COMMON_SMT_TRANSISTOR_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 50, `1234')') +# +# +# general purpose transistor, 5 pins +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing lengthwise in 1/10 mm +# $5: pin spacing across in 1/10 mm +# +define(`PKG_SMT_TRANSISTOR5', + `COMMON_SMT_TRANSISTOR_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 50, `12345')') +define(`PKG_SMT_TRANSISTOR5A', + `COMMON_SMT_TRANSISTOR_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 50, `45123')') +# +# +# general purpose transistor, 6 pins +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing lengthwise in 1/10 mm +# $5: pin spacing across in 1/10 mm +# +define(`PKG_SMT_TRANSISTOR6', + `COMMON_SMT_TRANSISTOR_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 50, `123456')') +# +# +# general purpose transistor, 3 pins on one side, cooling tab/pin on other +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin spacing lengthwise in 1/10 mm +# $5: pin spacing across in 1/10 mm +# +define(`PKG_SMT_TRANSISTOR4X', + `COMMON_SMT_TRANSISTORX_MIL(`$1', `$2', `$3', + eval(($4*1000)/254), eval(($5*1000)/254), 50, `1234')') +# +# SO package, narrow and wide +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: pin count +# $5: total width +# $6: pin pitch 1/100mil +# +# BUG: total package size in Y is larger +# +# +# 14 plasticX,Y=157,344 +# 24W plasticX,Y=299,614 +define(`PKG_SO', `COMMON_SMT_DUALINLINE(`$1',`$2',`$3',`$4',`$5',`$6',20,50)') +# +# 8..28 +# NOTE: 24 plasticX,Y=245,368 +define(`PKG_SSO', `COMMON_SMT_DUALINLINE(`$1',`$2',`$3',`$4',`$5',`$6',16,40)') +# +# 28, 32A, 32B +# NOTE: 28 plasticX,Y=469,319 +# NOTE: 32A plasticX,Y=728,319 +# BUG: check total size wrt rounding, it shoudl +# BUG: numbering is all different -- check +define(`PKG_TSOP', `COMMON_SMT_DUALINLINE(`$1',`$2',`$3',`$4',`$5',`$6',12,40)') +# +# 8, TSSOP56 TSSOP64 +# NOTE: 8 plasticX,Y=177,122 +# BUG: check total size wrt rounding +# BUG: numbering is all different -- check +define(`PKG_TSSOP', `COMMON_SMT_DUALINLINE(`$1',`$2',`$3',`$4',260,2600,14,40)') +# +# BUG: add SO8ePAD = SO8 plus dX=95+ dy=122+ solder pad +#efine(`xKG_SO', `COMMON_SMT_DUALINLINE(`$1',`$2',`$3',`$4',244,5000,20,50)') +# BUG: add PowerSO.PDF = MO166 - include dx=244+ dy=630 wide strip / X,Y=437,630 +#efine(`PKG_MO166', `COMMON_SMT_DUALINLINE(`$1',`$2',`$3',`$4',570,5000,25,50)') # 24: + + +# ------------------------------------------------------------------- +# the definition of a SMT dual inline package +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: number of pins +# $5: pad width (1/1000 mil) +# $6: pad length (1/1000 mil) +# $7: pad pitch (1/1000 mil) +# $8: pad seperation (gap in the copper) for pads on opposite sides of +# the package (1/1000 mil) +# $9: define to make the pins get numbered starting with the highest pin +# instead of pin 1. Needed for certain brain damaged packages like +# the Mini-Circuits KK81 +# pin 1 will be upper left, pin N/2 will be lower left, +# pin N will be upper right as defined here +define(`COMMON_SMT_DIL_MIL', + ` + # number of pads + define(`NPADS', `$4') + # pad width in 1/1000 mil + define(`PADWIDTH', `$5') + # pad length in 1/1000 mil + define(`PADLENGTH',`$6') + # pad pitch 1/1000 mil + define(`PITCH',`$7') + # seperation between pads on opposite sides 1/1000 mil + define(`PADSEP',`$8') + + # X coordinates for the right hand column of pads (1/100 mils) + define(`X1', eval( (PADSEP/2 + PADLENGTH - PADWIDTH/2)/10)) + define(`X2', eval( (PADSEP/2 + PADWIDTH/2)/10)) + + # pad clearance to plane layer in 1/100 mil + define(`PADCLEAR', 1000) + + # pad soldermask width in 1/100 mil + define(`PADMASK', eval(PADWIDTH/10 + 600)) + + # silk screen width (1/100 mils) + define(`SILKW', `1000') + define(`SILKSEP', `500') + + + # figure out if we have an even or odd number of pins per side + define(`TMP1', eval(NPADS/4)) + define(`TMP2', eval((4*TMP1 - NPADS) == 0)) + ifelse(TMP2, 1, `define(`EVEN',"yes")', `define(`EVEN',"no")') + + # silk bounding box is -XMAX,-YMAX, XMAX,YMAX (1/100 mils) + define(`XMAX', `eval( (PADSEP/2 + PADLENGTH + 5*SILKW)/10 + SILKSEP )') + ifelse(EVEN,"yes", + `define(`YMAX', eval( ((NPADS/4)*PITCH - PITCH/2 + PADWIDTH/2 + 5*SILKW)/10 + SILKSEP ))', + `define(`YMAX', eval( ((NPADS/4)*PITCH + PADWIDTH/2 + 5*SILKW)/10 + SILKSEP ))' + ) + + define(`REV', `$9') + + ifelse(REV,"reverse", + `define(`CURPIN', NPADS)' + , + `define(`CURPIN', `1')' + ) +# element_flags, description, pcb-name, value, mark_x, mark_y, +# text_x, text_y, text_direction, text_scale, text_flags +Element[0x00000000 "$1" "`$2'" "$3" 0 0 -2000 -6000 0 100 0x00000000] +( +# +# Pad[x1, y1, x2, y2, thickness, clearance, mask, name , pad number, flags] + forloop(`i', 1, eval(NPADS / 2), + `ifelse(EVEN,"yes", + `Pad[ -X1 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH)/10) + -X2 eval( (-(NPADS/4)*PITCH - PITCH/2 + i*PITCH)/10) + eval(PADWIDTH/10) PADCLEAR PADMASK "CURPIN" "CURPIN" 0x00000100]', + `Pad[ -X1 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH)/10) + -X2 eval( (-(NPADS/4)*PITCH - PITCH + i*PITCH)/10) + eval(PADWIDTH/10) PADCLEAR PADMASK "CURPIN" "CURPIN" 0x00000100]') + + ifelse(REV,"reverse", + `define(`CURPIN', decr(CURPIN))', + `define(`CURPIN', incr(CURPIN))' + ) + ') + forloop(`i', eval((NPADS / 2) + 1), NPADS, + `ifelse(EVEN,"yes", + `Pad[ X1 eval( ((NPADS/4)*PITCH + PITCH/2 - (i-NPADS/2)*PITCH)/10) + X2 eval( ((NPADS/4)*PITCH + PITCH/2 - (i-NPADS/2)*PITCH)/10) + eval(PADWIDTH/10) PADCLEAR PADMASK "CURPIN" "CURPIN" 0x00000100]', + `Pad[ X1 eval( ((NPADS/4)*PITCH + PITCH - (i-NPADS/2)*PITCH)/10) + X2 eval( ((NPADS/4)*PITCH + PITCH - (i-NPADS/2)*PITCH)/10) + eval(PADWIDTH/10) PADCLEAR PADMASK "CURPIN" "CURPIN" 0x00000100]') + ifelse(REV,"reverse", + `define(`CURPIN', decr(CURPIN))', + `define(`CURPIN', incr(CURPIN))' + ) + ') + + ElementLine[-XMAX -YMAX -XMAX YMAX SILKW] + ElementLine[-XMAX YMAX XMAX YMAX SILKW] + ElementLine[ XMAX YMAX XMAX -YMAX SILKW] + ElementLine[-XMAX -YMAX -2500 -YMAX SILKW] + ElementLine[ XMAX -YMAX 2500 -YMAX SILKW] + + # punt on the arc on small parts as it can cover the pads + ifelse(eval((PADSEP)/1000 > 70), 1, `ElementArc[0 -YMAX 2500 2500 0 180 SILKW]', ) + +)') + +# dimensions are given in 1/100 mm. +# $5-$8 are pad width, length, pitch, and sep +define(`COMMON_SMT_DIL_MM', `COMMON_SMT_DIL_MIL(`$1',`$2',`$3',`$4', + eval($5*100000/254),eval($6*100000/254),eval($7*100000/254),eval($8*100000/254), `$9')') + +define(`PKG_US', `COMMON_SMT_DIL_MM(`$1',`$2',`$3',`$4',30,70,50,200)') +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/smtosc.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,71 @@ +# -*- m4 -*- +# $Id: smtosc.inc,v 1.2 2007/08/31 08:02:06 msokolov Exp $ +# +# SMT oscillator packages + +# $1: canonical name +# $2: name on PCB +# $3: value +# $4: X dimension of component in mm/100 for silk outline +# $5: Y dimension of component in mm/100 for silk outline +# $6: X coordinate of pad centre in mm/100 +# $7: Y coordinate of pad centre in mm/100 +# $8: pad X dimension in mm/100 +# $9: pad Y dimension in mm/100 +# +define(`PKG_SMT_OSC', + `define(`sizX', eval($4 * 10000 / 254)) + define(`sizY', eval($5 * 10000 / 254)) + define(`centreX', eval($6 * 10000 / 254)) + define(`centreY', eval($7 * 10000 / 254)) + define(`padX', eval($8 * 10000 / 254)) + define(`padY', eval($9 * 10000 / 254)) + # silk outline + define(`silkW', 1000) + define(`width', eval(sizX/2 + silkW/2)) + define(`height', eval(sizY/2 + silkW/2)) + # how much to grow the pads by for soldermask + define(`maskGrow', 300) + # clearance from planes + define(`clearance', 1000) +Element[0x00 "`$1'" "`$2'" "`$3'" 0 0 eval(width + 2000) 0 3 100 0x00] +( + # outline + ElementLine[-width -height -width height silkW] + ElementLine[-width height width height silkW] + ElementLine[width height width -height silkW] + ElementLine[width -height -width -height silkW] + + # pads + ifelse(eval(padX > padY), 1, + `Pad[eval(-centreX - (padX - padY)/2) centreY + eval(-centreX + (padX - padY)/2) centreY + padY eval(2*clearance) eval(padY + 2*maskGrow) "EN" "1" 0x100] + Pad[eval( centreX - (padX - padY)/2) centreY + eval( centreX + (padX - padY)/2) centreY + padY eval(2*clearance) eval(padY + 2*maskGrow) "GND" "2" 0x100] + Pad[eval( centreX - (padX - padY)/2) -centreY + eval( centreX + (padX - padY)/2) -centreY + padY eval(2*clearance) eval(padY + 2*maskGrow) "OUT" "3" 0x100] + Pad[eval(-centreX - (padX - padY)/2) -centreY + eval(-centreX + (padX - padY)/2) -centreY + padY eval(2*clearance) eval(padY + 2*maskGrow) "VCC" "4" 0x100] + ', + `Pad[-centreX eval(centreY - (padY-padX)/2) + -centreX eval(centreY + (padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "EN" "1" 0x100] + Pad[centreX eval(centreY - (padY-padX)/2) + centreX eval(centreY + (padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "GND" "2" 0x100] + Pad[centreX eval(-centreY - (padY-padX)/2) + centreX eval(-centreY + (padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "OUT" "3" 0x100] + Pad[-centreX eval(-centreY - (padY-padX)/2) + -centreX eval(-centreY + (padY-padX)/2) + padX eval(2*clearance) eval(padX + 2*maskGrow) "VCC" "4" 0x100] + ') +)') + +# 7.5x5.0 mm SMT oscillator package, based on the Digi-Key catalog drawing +# for ECS-395[13][CM] +define(`PKG_OSC7550', `PKG_SMT_OSC(`$1',`$2',`$3',750,670,254,210,180,200)')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/template.pcb Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,44 @@ +# Default blank PCB from pcb-20060822 + +PCB["" 600000 500000] + +Grid[1000.000000 0 0 0] +Cursor[0 0 0.000000] +Thermal[0.500000] +DRC[1000 1000 1000 1000 1500 1000] +Flags(0x0000000000001c40) +Groups("1,c:2,s:3:4:5:6:7:8") +Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"] + +# font omitted, PCB will reinsert it on load & save. + +Layer(1 "component") +( +) +Layer(2 "solder") +( +) +Layer(3 "GND") +( +) +Layer(4 "power") +( +) +Layer(5 "signal1") +( +) +Layer(6 "signal2") +( +) +Layer(7 "signal3") +( +) +Layer(8 "signal4") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/to.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,422 @@ +# +# COPYRIGHT +# +# PCB, interactive printed circuit board design +# Copyright (C) 1994,1995,1996 Thomas Nau +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +# Contact addresses for paper mail and Email: +# Thomas Nau, Schlehenweg 15, 88471 Baustetten, Germany +# Thomas.Nau@rz.uni-ulm.de +# +# RCS: $Id: to.inc,v 1.2 2007/02/26 03:52:43 msokolov Exp $ +# +# TO packages + +# ------------------------------------------------------------------- +# a TO3 housing +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +# by Olaf Kaluza <criseis!olaf@ruhrgebiet.individual.net> +define(`PKG_TO3_90', +`Element(0x00 "$1" "$2" "$3" 400 800 0 100 0x00) +( + PIN(650, 1000, 120, 40, 1) + PIN(650, 550, 120, 40, 2) + PIN(1320, 775, 250, 120, 3) + PIN(125, 775, 250, 120, 4) + + ElementArc(700 775 500 500 70 40 20) + ElementArc(700 775 500 500 250 40 20) + ElementArc(1320 775 180 180 125 110 20) + ElementArc(125 775 180 180 305 110 20) + ElementLine(25 925 530 1245 20) + ElementLine(25 625 530 305 20) + ElementLine(870 305 1430 630 20) + ElementLine(870 1245 1430 920 20) + + Mark(650 775) +)') + +# by Volker Bosch, 45 degree, TO3 +define(`PKG_TO3_45', +`Element(0x00 "$1" "$2" "$3" 480 510 0 100 0x00) +( + PIN(750, 750, 120, 30, 1) + PIN(960, 380, 120, 30, 2) + PIN(1300, 830, 250, 120, 3) + PIN(280, 210, 250, 120, 4) + + ElementLine(660 1010 1300 1010 20) + ElementLine(1210 230 1470 770 20) + ElementLine(110 270 375 810 20) + ElementLine(280 30 920 30 20) + + ElementArc(790 520 420 420 0 360 20) + ElementArc(790 520 510 510 215 40 20) + ElementArc(790 520 510 510 35 40 20) + + ElementArc(1300 830 180 180 90 110 20) + ElementArc(280 210 180 180 270 110 20) + + Mark(750 750) +)') + +# ------------------------------------------------------------------- +# a TO5 housing +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +# by Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +define(`PKG_TO5', +`Element(0x00 "$1" "$2" "$3" 110 110 0 100 0x00) +( + PIN(100, 200, 80, 20, 1) + PIN(200, 300, 80, 20, 2) + PIN(300, 200, 80, 20, 3) + + ElementArc(200 200 150 150 0 360 10) + ElementArc(200 200 170 170 0 360 20) + ElementLine(65 95 35 65 20) + ElementLine(35 65 65 35 20) + ElementLine(65 35 95 65 20) + + Mark(100 200) +)') + +# ------------------------------------------------------------------- +# a TO92 housing +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +# by Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +# lineare Anordnung der Pins +define(`PKG_TO92', +`Element(0x00 "$1" "$2" "$3" 60 70 0 100 0x00) +( + PIN(50, 200, 80, 20, 1) + PIN(150, 200, 80, 20, 2) + PIN(250, 200, 80, 20, 3) + + ElementArc(150 200 100 100 315 270 10) + ElementLine( 80 130 220 130 10) + + Mark(50 200) +)') + +# ------------------------------------------------------------------- +# a TO126 housing +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +# by Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +define(`PKG_TO126LAY', +`Element(0x00 "$1" "$2" "$3" 80 480 1 100 0x00) +( + PIN(110, 600, 75, 50, 1) + PIN(200, 600, 75, 50, 2) + PIN(290, 600, 75, 50, 3) + + # Befestigungsbohrung + PIN(200, 170, 130, 110, 4) + + # Anschlussdraehte + ElementLine(100 600 100 500 30) + ElementLine(200 600 200 500 30) + ElementLine(300 600 300 500 30) + + # Gehaeuse + ElementLine( 50 500 350 500 20) + ElementLine(350 500 350 70 20) + ElementLine(350 70 50 70 20) + ElementLine( 50 70 50 500 20) + + Mark(100 600) +)') + +define(`PKG_TO126LAY_WIDE', +`Element(0x00 "$1" "$2" "$3" 80 480 1 100 0x00) +( + PIN(110, 600, 75, 50, 1) + PIN(200, 700, 75, 50, 2) + PIN(290, 600, 75, 50, 3) + + # Befestigungsbohrung + PIN(200, 170, 130, 110, 4) + + # Anschlussdraehte + ElementLine(100 600 100 500 30) + ElementLine(200 700 200 500 30) + ElementLine(300 600 300 500 30) + + # Gehaeuse + ElementLine( 50 500 350 500 20) + ElementLine(350 500 350 70 20) + ElementLine(350 70 50 70 20) + ElementLine( 50 70 50 500 20) + + Mark(100 600) +)') + +define(`PKG_TO126STAND', +`Element(0x00 "$1" "$2" "$3" 60 170 0 100 0x00) +( + PIN(110, 100, 75, 50, 1) + PIN(200, 100, 75, 50, 2) + PIN(290, 100, 75, 50, 3) + + ElementLine(50 50 350 50 20) + ElementLine(350 50 350 150 20) + ElementLine(350 150 50 150 20) + ElementLine(50 150 50 50 20) + + Mark(100 100) +)') + +define(`PKG_TO126STAND_WIDE', +`Element(0x00 "$1" "$2" "$3" 270 170 0 100 0x00) +( + PIN(110, 100, 75, 50, 1) + PIN(200, 200, 75, 50, 2) + PIN(290, 100, 75, 50, 3) + + # Gehaeuse + ElementLine(200 200 200 150 30) + ElementLine( 50 50 350 50 20) + ElementLine(350 50 350 150 20) + ElementLine(350 150 50 150 20) + ElementLine( 50 150 50 50 20) + + # Bohrung + ElementLine(150 50 150 150 10) + ElementLine(250 50 250 150 10) + + Mark(100 100) +)') + +# ------------------------------------------------------------------- +# a TO220 housing +# +# $1: canonical name +# $2: name on PCB +# $3: value +# +# by Volker Bosch (bosch@iema.e-technik.uni-stuttgart.de) +define(`PKG_TO220LAY', +`Element(0x00 "$1" "$2" "$3" 50 570 1 100 0x00) +( + PIN(100, 800, 90, 60, 1) + PIN(200, 800, 90, 60, 2) + PIN(300, 800, 90, 60, 3) + + # Befestigungsbohrung + PIN(200, 130, 150, 130, 4) + + # Anschlussdraehte + ElementLine(100 800 100 620 30) + ElementLine(200 800 200 620 30) + ElementLine(300 800 300 620 30) + + # Gehaeuse + ElementLine( 0 620 400 620 20) + ElementLine(400 620 400 245 20) + ElementLine(400 245 0 245 20) + ElementLine( 0 245 0 620 20) + + # Kuehlfahne mit Kerben + ElementLine( 0 245 400 245 20) + ElementLine(400 245 400 120 20) + ElementLine(400 120 385 120 20) + ElementLine(385 120 385 50 20) + ElementLine(385 50 400 50 20) + ElementLine(400 50 400 10 20) + ElementLine(400 10 0 10 20) + ElementLine( 0 10 0 50 20) + ElementLine( 0 50 15 50 20) + ElementLine( 15 50 15 120 20) + ElementLine( 15 120 0 120 20) + ElementLine( 0 120 0 245 20) + + Mark(200 800) +)') + +define(`PKG_TO220LAY_WIDE', +`Element(0x00 "$1" "$2" "$3" 50 570 1 100 0x00) +( + PIN(100, 800, 90, 60, 1) + PIN(200, 900, 90, 60, 2) + PIN(300, 800, 90, 60, 3) + + # Befestigungsbohrung + PIN(200, 130, 150, 130, 4) + + # Anschlussdraehte + ElementLine(100 800 100 620 30) + ElementLine(200 900 200 620 30) + ElementLine(300 800 300 620 30) + + # Gehaeuse + ElementLine( 0 620 400 620 20) + ElementLine(400 620 400 245 20) + ElementLine(400 245 0 245 20) + ElementLine( 0 245 0 620 20) + + # Kuehlfahne mit Kerben + ElementLine( 0 245 400 245 20) + ElementLine(400 245 400 120 20) + ElementLine(400 120 385 120 20) + ElementLine(385 120 385 50 20) + ElementLine(385 50 400 50 20) + ElementLine(400 50 400 10 20) + ElementLine(400 10 0 10 20) + ElementLine( 0 10 0 50 20) + ElementLine( 0 50 15 50 20) + ElementLine( 15 50 15 120 20) + ElementLine( 15 120 0 120 20) + ElementLine( 0 120 0 245 20) + + Mark(200 800) +)') + +define(`PKG_TO220STAND', +`Element(0x00 "$1" "$2" "$3" 0 10 0 100 0x00) +( + PIN(100, 200, 90, 60, 1) + PIN(200, 200, 90, 60, 2) + PIN(300, 200, 90, 60, 3) + + # Gehaeuse + ElementLine( 0 80 400 80 20) + ElementLine(400 80 400 260 20) + ElementLine(400 260 0 260 20) + ElementLine( 0 260 0 80 20) + + # Kuehlfahne icl. Bohrung + ElementLine( 0 80 400 80 20) + ElementLine(400 80 400 140 20) + ElementLine(400 140 0 140 20) + ElementLine( 0 140 0 80 20) + + ElementLine(130 80 130 140 10) + ElementLine(270 80 270 140 10) + + Mark(100 200) +)') + +define(`PKG_TO220STAND_WIDE', +`Element(0x00 "$1" "$2" "$3" 0 10 0 100 0x00) +( + PIN(100, 200, 90, 60, 1) + PIN(200, 300, 90, 60, 2) + PIN(300, 200, 90, 60, 3) + + # Gehaeuse + ElementLine( 0 80 400 80 20) + ElementLine(400 80 400 260 20) + ElementLine(400 260 0 260 20) + ElementLine( 0 260 0 80 20) + + # Kuehlfahne icl. Bohrung + ElementLine( 0 80 400 80 20) + ElementLine(400 80 400 140 20) + ElementLine(400 140 0 140 20) + ElementLine( 0 140 0 80 20) + + ElementLine(130 80 130 140 10) + ElementLine(270 80 270 140 10) + + # Anschlussdraht + ElementLine(200 300 200 260 30) + + Mark(100 200) +)') + +# Small outline transistors, taken from some nice data sheets +# by NEC/CEL for the NE688 series. +# WX, WY are width of the pad footprint +# DX, DY are center-to-center pad spacing +# OX, OY are outline size for drawing +# There is good reason to make OY match the size of plastic package, +# but I suggest making OX small enough to not get ink on the pad, +# even if that understates the size of the real package. +# Jan 6, 2000 Larry Doolittle <LRDoolittle@lbl.gov> +# Status: Untested, but looks pretty :-) + +define(`PKG_BASE_SOT', +`Element(0x00 "$1" "$2" "$3" 0 eval(DY+WY/2+10) 0 100 0x00) +( + define(`WID', WY) + define(`RX', eval((WX-WID)/2)) + define(`X1', 0) + define(`Y1', DY) + define(`X2', 0) + define(`Y2', 0) + define(`X3', DX) + define(`Y3', eval(DY/2)) + # Use Pad instead of PAD so all pads come out square + Pad(eval(X1-RX) Y1 eval(X1+RX) Y1 WID "1" 0x100) + Pad(eval(X2-RX) Y2 eval(X2+RX) Y2 WID "2" 0x100) + Pad(eval(X3-RX) Y3 eval(X3+RX) Y3 WID "3" 0x100) + + define(`LX', eval((DX-OX)/2)) + define(`LY', eval((DY-OY)/2)) + define(`MX', eval((DX+OX)/2)) + define(`MY', eval((DY+OY)/2)) + ElementLine(LX LY LX MY 6) + ElementLine(LX MY MX MY 6) + ElementLine(MX MY MX LY 6) + ElementLine(MX LY LX LY 6) + +)') + +define(`PKG_SOT23_CEL',` + define(`WX', 40) + define(`WY', 32) + define(`DX', 95) + define(`DY', 78) + define(`OX', 46) + define(`OY', 114) + PKG_BASE_SOT(`$1',`$2',`$3') +') + +define(`PKG_SOT323_CEL',` + define(`WX', 32) + define(`WY', 24) + define(`DX', 67) + define(`DY', 51) + define(`OX', 26) + define(`OY', 79) + PKG_BASE_SOT(`$1',`$2',`$3') +') + +define(`PKG_NEC19',` + define(`WX', 24) + define(`WY', 24) + define(`DX', 50) + define(`DY', 40) + define(`OX', 18) + define(`OY', 62) + PKG_BASE_SOT(`$1',`$2',`$3') +')
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/ueda.m4 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,8 @@ +divert(-1) + +define(`make_footprint', + `ifdef(`PKG_$1',`PKG_$1(`$1',`$2',`$3')', + `make_footprint_file(`$1',`$2',`$3')')') +define(`make_footprint_file',`syscmd(ueda-instfileelem `$1' `$2' `$3')') + +divert(0)dnl
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/m4-fp/zif.inc Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +define(`PKG_ZIF', + `define(`NUMPINS', `$4') + define(`CENTER', eval(NUMPINS*19)) +Element(0x00 "$1" "$2" "$3" 100 CENTER 0 100 0x00) +( + +define(`X', 0) +define(`count', 1) +forloop(`i', 1, NUMPINS, + `PAD(X, 12, X, 97, 24, count)' `define(`count', incr(count))' + `define(`X', eval(X+39))' +) +PAD(-124, -41, -124, -151, 82, eval(NUMPINS+1)) +PAD(eval(X+124-39), -41, eval(X+124-39), -151, 82, eval(NUMPINS+2)) +)') + +# -------------------------------------------------------------------
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,1 @@ +mkheader
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/12V-minus-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=-12V +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 75 250 9 8 1 0 0 0 1 +-12V
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/12V-minus-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 200 200 400 1 0 1 +{ +attr forcenet=-12V +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 50 50 9 8 1 0 0 0 1 +-12V
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/12V-plus-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=+12V +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 75 250 9 8 1 0 0 0 1 ++12V
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/26LS31-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,25 @@ +L 400 600 400 200 3 0 0 0 -1 -1 +L 400 200 700 400 3 0 0 0 -1 -1 +L 700 400 400 600 3 0 0 0 -1 -1 +V 650 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 400 400 400 1 0 0 +{ +T 200 500 5 8 1 1 0 7 1 +pinnumber=%d +T 200 500 5 8 0 1 0 6 1 +pinname=A +} +P 900 300 600 300 1 0 0 +{ +T 800 400 5 8 1 1 0 7 1 +pinnumber=%d +T 800 350 5 8 0 1 0 6 1 +pinname=Y +} +P 900 500 700 500 1 0 0 +{ +T 800 600 5 8 1 1 0 7 1 +pinnumber=%d +T 800 550 5 8 0 1 0 6 1 +pinname=Z +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/26LS31-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,25 @@ +L 400 600 400 200 3 0 0 0 -1 -1 +L 400 200 700 400 3 0 0 0 -1 -1 +L 700 400 400 600 3 0 0 0 -1 -1 +V 650 300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 400 400 400 1 0 0 +{ +T 200 500 5 8 1 1 0 7 1 +pinnumber=%d +T 200 500 5 8 0 1 0 6 1 +pinname=A +} +P 900 500 600 500 1 0 0 +{ +T 800 600 5 8 1 1 0 7 1 +pinnumber=%d +T 800 550 5 8 0 1 0 6 1 +pinname=Y +} +P 900 300 700 300 1 0 0 +{ +T 800 400 5 8 1 1 0 7 1 +pinnumber=%d +T 800 350 5 8 0 1 0 6 1 +pinname=Z +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/26LS31.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,21 @@ +# A is the TTL input +# Y is the positive output +# Z is the negative output + +#pin name pin number +A:1 1 +Y:1 2 +Z:1 3 +Gpos 4 +Z:2 5 +Y:2 6 +A:2 7 +GND 8 +A:3 9 +Y:3 10 +Z:3 11 +Gneg 12 +Z:4 13 +Y:4 14 +A:4 15 +Vcc 16
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/26LS3132-com.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,32 @@ +P 0 1100 300 1100 1 0 0 +{ +T 200 1150 5 8 1 1 0 6 1 +pinnumber=4 +T 350 1100 9 8 1 1 0 0 1 +pinlabel=G +attr pinname=Gpos +} +P 0 700 300 700 1 0 0 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=12 +T 350 700 9 8 1 1 0 0 1 +pinlabel=G +attr pinname=Gneg +} +L 350 824 470 824 3 0 0 0 -1 -1 +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=8 +T 1000 350 9 8 1 1 0 3 1 +pinname=GND +} +P 1000 1800 1000 1500 1 0 0 +{ +T 1050 1600 5 8 1 1 0 0 1 +pinnumber=16 +T 1000 1450 9 8 1 1 0 5 1 +pinname=Vcc +} +B 300 300 1400 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/26LS32.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +#pin name pin number +Rcvr_In_N:1 1 +Rcvr_In_P:1 2 +Rcvr_Out:1 3 +Gpos 4 +Rcvr_Out:2 5 +Rcvr_In_P:2 6 +Rcvr_In_N:2 7 +GND 8 +Rcvr_In_N:3 9 +Rcvr_In_P:3 10 +Rcvr_Out:3 11 +Gneg 12 +Rcvr_Out:4 13 +Rcvr_In_P:4 14 +Rcvr_In_N:4 15 +Vcc 16
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/29x040-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,369 @@ +v 20040111 1 +T 2400 9700 8 10 1 1 0 6 1 +refdes=U? +T 400 9650 9 10 1 1 0 0 1 +device=29x040 +T 400 10050 5 10 0 0 0 0 1 +footprint=PLCC32 +T 400 10250 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 10450 5 10 0 0 0 0 1 +description=512Kx8 flash memory +T 400 10650 5 10 0 0 0 0 1 +numslots=0 +P 1400 9900 1400 9600 1 0 0 +{ +T 1450 9700 5 8 1 1 0 0 1 +pinnumber=32 +T 1450 9700 5 8 0 1 0 2 1 +pinseq=32 +T 1400 9550 9 8 1 1 0 5 1 +pinlabel=VCC +T 1400 9400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2700 9200 2400 9200 1 0 0 +{ +T 2500 9250 5 8 1 1 0 0 1 +pinnumber=13 +T 2500 9150 5 8 0 1 0 2 1 +pinseq=13 +T 2350 9200 9 8 1 1 0 6 1 +pinlabel=DQ0 +T 2350 9200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8800 2400 8800 1 0 0 +{ +T 2500 8850 5 8 1 1 0 0 1 +pinnumber=14 +T 2500 8750 5 8 0 1 0 2 1 +pinseq=14 +T 2350 8800 9 8 1 1 0 6 1 +pinlabel=DQ1 +T 2350 8800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8400 2400 8400 1 0 0 +{ +T 2500 8450 5 8 1 1 0 0 1 +pinnumber=15 +T 2500 8350 5 8 0 1 0 2 1 +pinseq=15 +T 2350 8400 9 8 1 1 0 6 1 +pinlabel=DQ2 +T 2350 8400 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8000 2400 8000 1 0 0 +{ +T 2500 8050 5 8 1 1 0 0 1 +pinnumber=17 +T 2500 7950 5 8 0 1 0 2 1 +pinseq=17 +T 2350 8000 9 8 1 1 0 6 1 +pinlabel=DQ3 +T 2350 8000 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7600 2400 7600 1 0 0 +{ +T 2500 7650 5 8 1 1 0 0 1 +pinnumber=18 +T 2500 7550 5 8 0 1 0 2 1 +pinseq=18 +T 2350 7600 9 8 1 1 0 6 1 +pinlabel=DQ4 +T 2350 7600 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 7200 2400 7200 1 0 0 +{ +T 2500 7250 5 8 1 1 0 0 1 +pinnumber=19 +T 2500 7150 5 8 0 1 0 2 1 +pinseq=19 +T 2350 7200 9 8 1 1 0 6 1 +pinlabel=DQ5 +T 2350 7200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6800 2400 6800 1 0 0 +{ +T 2500 6850 5 8 1 1 0 0 1 +pinnumber=20 +T 2500 6750 5 8 0 1 0 2 1 +pinseq=20 +T 2350 6800 9 8 1 1 0 6 1 +pinlabel=DQ6 +T 2350 6800 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 6400 2400 6400 1 0 0 +{ +T 2500 6450 5 8 1 1 0 0 1 +pinnumber=21 +T 2500 6350 5 8 0 1 0 2 1 +pinseq=21 +T 2350 6400 9 8 1 1 0 6 1 +pinlabel=DQ7 +T 2350 6400 5 8 0 1 0 8 1 +pintype=tri +} +P 100 9200 400 9200 1 0 0 +{ +T 300 9250 5 8 1 1 0 6 1 +pinnumber=12 +T 300 9150 5 8 0 1 0 8 1 +pinseq=12 +T 450 9200 9 8 1 1 0 0 1 +pinlabel=A0 +T 450 9200 5 8 0 1 0 2 1 +pintype=in +} +P 100 8800 400 8800 1 0 0 +{ +T 300 8850 5 8 1 1 0 6 1 +pinnumber=11 +T 300 8750 5 8 0 1 0 8 1 +pinseq=11 +T 450 8800 9 8 1 1 0 0 1 +pinlabel=A1 +T 450 8800 5 8 0 1 0 2 1 +pintype=in +} +P 100 8400 400 8400 1 0 0 +{ +T 300 8450 5 8 1 1 0 6 1 +pinnumber=10 +T 300 8350 5 8 0 1 0 8 1 +pinseq=10 +T 450 8400 9 8 1 1 0 0 1 +pinlabel=A2 +T 450 8400 5 8 0 1 0 2 1 +pintype=in +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=9 +T 300 7950 5 8 0 1 0 8 1 +pinseq=9 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=A3 +T 450 8000 5 8 0 1 0 2 1 +pintype=in +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=8 +T 300 7550 5 8 0 1 0 8 1 +pinseq=8 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=A4 +T 450 7600 5 8 0 1 0 2 1 +pintype=in +} +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=7 +T 300 7150 5 8 0 1 0 8 1 +pinseq=7 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=A5 +T 450 7200 5 8 0 1 0 2 1 +pintype=in +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=6 +T 300 6750 5 8 0 1 0 8 1 +pinseq=6 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=A6 +T 450 6800 5 8 0 1 0 2 1 +pintype=in +} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=5 +T 300 6350 5 8 0 1 0 8 1 +pinseq=5 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=A7 +T 450 6400 5 8 0 1 0 2 1 +pintype=in +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=27 +T 300 5950 5 8 0 1 0 8 1 +pinseq=27 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=A8 +T 450 6000 5 8 0 1 0 2 1 +pintype=in +} +P 100 5600 400 5600 1 0 0 +{ +T 300 5650 5 8 1 1 0 6 1 +pinnumber=26 +T 300 5550 5 8 0 1 0 8 1 +pinseq=26 +T 450 5600 9 8 1 1 0 0 1 +pinlabel=A9 +T 450 5600 5 8 0 1 0 2 1 +pintype=in +} +P 100 5200 400 5200 1 0 0 +{ +T 300 5250 5 8 1 1 0 6 1 +pinnumber=23 +T 300 5150 5 8 0 1 0 8 1 +pinseq=23 +T 450 5200 9 8 1 1 0 0 1 +pinlabel=A10 +T 450 5200 5 8 0 1 0 2 1 +pintype=in +} +P 100 4800 400 4800 1 0 0 +{ +T 300 4850 5 8 1 1 0 6 1 +pinnumber=25 +T 300 4750 5 8 0 1 0 8 1 +pinseq=25 +T 450 4800 9 8 1 1 0 0 1 +pinlabel=A11 +T 450 4800 5 8 0 1 0 2 1 +pintype=in +} +P 100 4400 400 4400 1 0 0 +{ +T 300 4450 5 8 1 1 0 6 1 +pinnumber=4 +T 300 4350 5 8 0 1 0 8 1 +pinseq=4 +T 450 4400 9 8 1 1 0 0 1 +pinlabel=A12 +T 450 4400 5 8 0 1 0 2 1 +pintype=in +} +P 100 4000 400 4000 1 0 0 +{ +T 300 4050 5 8 1 1 0 6 1 +pinnumber=28 +T 300 3950 5 8 0 1 0 8 1 +pinseq=28 +T 450 4000 9 8 1 1 0 0 1 +pinlabel=A13 +T 450 4000 5 8 0 1 0 2 1 +pintype=in +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=29 +T 300 3550 5 8 0 1 0 8 1 +pinseq=29 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=A14 +T 450 3600 5 8 0 1 0 2 1 +pintype=in +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=3 +T 300 3150 5 8 0 1 0 8 1 +pinseq=3 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=A15 +T 450 3200 5 8 0 1 0 2 1 +pintype=in +} +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=2 +T 300 2750 5 8 0 1 0 8 1 +pinseq=2 +T 450 2800 9 8 1 1 0 0 1 +pinlabel=A16 +T 450 2800 5 8 0 1 0 2 1 +pintype=in +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=30 +T 300 2350 5 8 0 1 0 8 1 +pinseq=30 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=A17 +T 450 2400 5 8 0 1 0 2 1 +pintype=in +} +P 100 2000 400 2000 1 0 0 +{ +T 300 2050 5 8 1 1 0 6 1 +pinnumber=1 +T 300 1950 5 8 0 1 0 8 1 +pinseq=1 +T 450 2000 9 8 1 1 0 0 1 +pinlabel=A18 +T 450 2000 5 8 0 1 0 2 1 +pintype=in +} +P 100 1600 300 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=22 +T 300 1550 5 8 0 1 0 8 1 +pinseq=22 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=CE +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +V 350 1600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 1200 300 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=24 +T 300 1150 5 8 0 1 0 8 1 +pinseq=24 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=OE +T 450 1200 5 8 0 1 0 2 1 +pintype=in +} +V 350 1200 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 800 300 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=31 +T 300 750 5 8 0 1 0 8 1 +pinseq=31 +T 450 800 9 8 1 1 0 0 1 +pinlabel=WE +T 450 800 5 8 0 1 0 2 1 +pintype=in +} +V 350 800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1400 100 1400 400 1 0 0 +{ +T 1450 200 5 8 1 1 0 0 1 +pinnumber=16 +T 1450 200 5 8 0 1 0 2 1 +pinseq=16 +T 1400 450 9 8 1 1 0 3 1 +pinlabel=GND +T 1400 600 5 8 0 1 0 3 1 +pintype=pwr +} +B 400 400 2000 9200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/3.3V-plus-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=+3.3V +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 200 250 9 8 1 0 0 3 1 ++3.3V
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/5V-minus-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=-5V +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 75 250 9 8 1 0 0 0 1 +-5V
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/5V-plus-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=+5V +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 75 250 9 8 1 0 0 0 1 ++5V
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/5V-plus-analog.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=+5VAA +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 200 250 9 8 1 0 0 3 1 ++5VAA
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/5V-plus-digital.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=+5VDD +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 200 250 9 8 1 0 0 3 1 ++5VDD
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7400-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,26 @@ +L 300 200 300 800 3 0 0 0 -1 -1 +L 300 800 700 800 3 0 0 0 -1 -1 +L 300 200 700 200 3 0 0 0 -1 -1 +A 700 500 300 270 180 3 0 0 0 -1 -1 +V 1050 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1100 500 1300 500 1 0 1 +{ +T 1100 550 5 8 1 1 0 0 1 +pinnumber=%d +T 950 500 9 8 0 1 0 6 1 +pinname=Y +} +P 300 300 0 300 1 0 1 +{ +T 200 350 5 8 1 1 0 6 1 +pinnumber=%d +T 350 300 9 8 0 1 0 0 1 +pinname=B +} +P 300 700 0 700 1 0 1 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=%d +T 350 700 9 8 0 1 0 0 1 +pinname=A +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7400-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,28 @@ +L 260 200 600 200 3 0 0 0 -1 -1 +L 260 800 600 800 3 0 0 0 -1 -1 +A 0 500 400 312 97 3 0 0 0 -1 -1 +V 250 700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 250 300 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 988 500 1300 500 1 0 1 +{ +T 1100 550 5 8 1 1 0 0 1 +pinnumber=%d +T 950 500 9 8 0 1 0 6 1 +pinname=Y +} +P 200 700 0 700 1 0 1 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=%d +T 350 700 9 8 0 1 0 0 1 +pinname=A +} +P 200 300 0 300 1 0 1 +{ +T 200 350 5 8 1 1 0 6 1 +pinnumber=%d +T 350 300 9 8 0 1 0 0 1 +pinname=B +} +A 600 600 400 270 76 3 0 0 0 -1 -1 +A 600 400 400 14 76 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7400.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,15 @@ +#pin name pin number +A:1 1 +B:1 2 +Y:1 3 +A:2 4 +B:2 5 +Y:2 6 +GND 7 +Y:3 8 +A:3 9 +B:3 10 +Y:4 11 +A:4 12 +B:4 13 +Vcc 14
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7404-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,19 @@ +L 300 800 800 500 3 0 0 0 -1 -1 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +V 850 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=%d +T 350 500 9 8 0 1 0 0 1 +pinname=A +} +P 1100 500 900 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=%d +T 750 500 9 8 0 1 0 6 1 +pinname=Y +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7404-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,19 @@ +L 300 800 800 500 3 0 0 0 -1 -1 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +V 250 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1100 500 800 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=%d +T 750 500 9 8 0 1 0 6 1 +pinname=Y +} +P 200 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=%d +T 350 500 9 8 0 1 0 0 1 +pinname=A +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7404.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,15 @@ +#pin name pin number +A:1 1 +Y:1 2 +A:2 3 +Y:2 4 +A:3 5 +Y:3 6 +GND 7 +Y:4 8 +A:4 9 +Y:5 10 +A:5 11 +Y:6 12 +A:6 13 +Vcc 14
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7405-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,20 @@ +L 300 800 800 500 3 0 0 0 -1 -1 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +V 850 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=%d +T 350 500 9 8 0 1 0 0 1 +pinname=A +} +P 1100 500 900 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=%d +T 750 500 9 8 0 1 0 6 1 +pinname=Y +} +L 488 313 619 606 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7407-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,19 @@ +L 300 800 800 500 3 0 0 0 -1 -1 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 500 3 0 0 0 -1 -1 +L 300 500 300 200 3 0 0 0 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=%d +T 350 500 9 8 0 1 0 0 1 +pinname=A +} +P 1100 500 800 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=%d +T 750 500 9 8 0 1 0 6 1 +pinname=Y +} +L 488 313 619 606 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7474-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,52 @@ +P 0 1400 300 1400 1 0 0 +{ +T 200 1450 5 8 1 1 0 6 1 +pinnumber=%d +T 350 1400 9 8 1 1 0 0 1 +pinname=D +} +P 2000 1400 1700 1400 1 0 0 +{ +T 1800 1450 5 8 1 1 0 0 1 +pinnumber=%d +T 1650 1400 9 8 1 1 0 6 1 +pinname=Q +} +P 0 1000 200 1000 1 0 0 +{ +attr pinname=R +T 200 1050 5 8 1 1 0 6 1 +pinnumber=%d +T 350 1000 9 8 1 1 0 0 1 +pinlabel=CLR +} +V 250 1000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 2000 1000 1800 1000 1 0 0 +{ +attr pinname=Qbar +T 1800 1050 5 8 1 1 0 0 1 +pinnumber=%d +T 1650 1000 9 8 1 1 0 6 1 +pinlabel=Q +} +P 0 600 200 600 1 0 0 +{ +attr pinname=S +T 200 650 5 8 1 1 0 6 1 +pinnumber=%d +T 350 600 9 8 1 1 0 0 1 +pinlabel=PRE +} +V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 0 200 300 200 1 0 0 +{ +attr pinname=C +T 200 250 5 8 1 1 0 6 1 +pinnumber=%d +T 375 200 9 8 1 1 0 0 1 +pinlabel=CLK +} +V 1750 1000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 300 0 1400 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 250 375 200 3 0 0 0 -1 -1 +L 375 200 300 150 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/7474.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,15 @@ +#pin name pin number +R:1 1 +D:1 2 +C:1 3 +S:1 4 +Q:1 5 +Qbar:1 6 +GND 7 +Qbar:2 8 +Q:2 9 +S:2 10 +C:2 11 +D:2 12 +R:2 13 +Vcc 14
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/74xx-pwr.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,19 @@ +T 200 2050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 200 2350 5 10 0 0 0 0 1 +description=Generic symbol for power & ground pins of 74xx logic ICs +P 400 1400 400 1100 1 0 0 +{ +T 450 1200 5 8 1 1 0 0 1 +pinnumber=%d +T 400 1050 9 8 1 1 0 5 1 +pinname=Vcc +} +P 400 0 400 300 1 0 0 +{ +T 450 100 5 8 1 1 0 0 1 +pinnumber=%d +T 400 350 9 8 1 1 0 3 1 +pinname=GND +} +B 200 300 400 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/ADM709-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,50 @@ +v 20040111 1 +T 1800 1200 8 10 1 1 0 6 1 +refdes=U? +T 0 1150 9 10 1 0 0 0 1 +ADM709 +T 0 1350 5 10 0 0 0 0 1 +device=ADM709 +T 0 1550 5 10 0 0 0 0 1 +footprint=SO8 +T 0 1750 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 0 2150 5 10 0 0 0 0 1 +description=Power supply monitor and reset generator +T 0 2350 5 10 0 0 0 0 1 +numslots=0 +P 900 1400 900 1100 1 0 0 +{ +T 950 1200 5 8 1 1 0 0 1 +pinnumber=2 +T 950 1200 5 8 0 1 0 2 1 +pinseq=2 +T 900 1050 9 8 1 1 0 5 1 +pinlabel=Vcc +T 900 900 5 8 0 1 0 5 1 +pintype=pwr +} +P 900 0 900 300 1 0 0 +{ +T 950 100 5 8 1 1 0 0 1 +pinnumber=3 +T 950 100 5 8 0 1 0 2 1 +pinseq=3 +T 900 350 9 8 1 1 0 3 1 +pinlabel=GND +T 900 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 2100 700 1800 700 1 0 0 +{ +T 1900 750 5 8 1 1 0 0 1 +pinnumber=7 +T 1900 650 5 8 0 1 0 2 1 +pinseq=7 +T 1750 700 9 8 1 1 0 6 1 +pinlabel=RESET +T 1750 700 5 8 0 1 0 8 1 +pintype=out +} +L 1222 824 1750 824 3 0 0 0 -1 -1 +B 0 300 1800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/ADP3303-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,106 @@ +v 20040111 1 +T 1700 2800 8 10 1 1 0 6 1 +refdes=U? +T 300 2750 9 10 1 0 0 0 1 +ADP3303 +T 300 2950 5 10 0 0 0 0 1 +device=ADP3303 +T 300 3150 5 10 0 0 0 0 1 +footprint=SO8 +T 300 3350 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 3750 5 10 0 0 0 0 1 +description=Linear Regulator +T 300 3950 5 10 0 0 0 0 1 +numslots=0 +P 0 1900 300 1900 1 0 0 +{ +T 200 1950 5 8 1 1 0 6 1 +pinnumber=7 +T 200 1850 5 8 0 1 0 8 1 +pinseq=7 +T 350 1900 9 8 1 1 0 0 1 +pinlabel=IN +T 350 1900 5 8 0 1 0 2 1 +pintype=in +} +P 0 1500 300 1500 1 0 0 +{ +T 200 1550 5 8 1 1 0 6 1 +pinnumber=8 +T 200 1450 5 8 0 1 0 8 1 +pinseq=8 +T 350 1500 9 8 1 1 0 0 1 +pinlabel=IN +T 350 1500 5 8 0 1 0 2 1 +pintype=in +} +P 0 700 200 700 1 0 0 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=5 +T 200 650 5 8 0 1 0 8 1 +pinseq=5 +T 350 700 9 8 1 1 0 0 1 +pinlabel=SD +T 350 700 5 8 0 1 0 2 1 +pintype=in +} +V 250 700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 2000 2300 1700 2300 1 0 0 +{ +T 1800 2350 5 8 1 1 0 0 1 +pinnumber=3 +T 1800 2250 5 8 0 1 0 2 1 +pinseq=3 +T 1650 2300 9 8 1 1 0 6 1 +pinlabel=NR +T 1650 2300 5 8 0 1 0 8 1 +pintype=pas +} +P 2000 1900 1700 1900 1 0 0 +{ +T 1800 1950 5 8 1 1 0 0 1 +pinnumber=1 +T 1800 1850 5 8 0 1 0 2 1 +pinseq=1 +T 1650 1900 9 8 1 1 0 6 1 +pinlabel=OUT +T 1650 1900 5 8 0 1 0 8 1 +pintype=out +} +P 2000 1500 1700 1500 1 0 0 +{ +T 1800 1550 5 8 1 1 0 0 1 +pinnumber=2 +T 1800 1450 5 8 0 1 0 2 1 +pinseq=2 +T 1650 1500 9 8 1 1 0 6 1 +pinlabel=OUT +T 1650 1500 5 8 0 1 0 8 1 +pintype=out +} +P 2000 700 1800 700 1 0 0 +{ +T 1800 750 5 8 1 1 0 0 1 +pinnumber=6 +T 1800 650 5 8 0 1 0 2 1 +pinseq=6 +T 1650 700 9 8 1 1 0 6 1 +pinlabel=ERR +T 1650 700 5 8 0 1 0 8 1 +pintype=out +} +V 1750 700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=4 +T 1050 100 5 8 0 1 0 2 1 +pinseq=4 +T 1000 350 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 300 300 1400 2400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/CY62148B-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,369 @@ +v 20040111 1 +T 2400 9700 8 10 1 1 0 6 1 +refdes=U? +T 400 9650 9 9 1 0 0 0 1 +CY62148B +T 400 9850 5 10 0 0 0 0 1 +device=CY62148B +T 400 10050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 10250 5 10 0 0 0 0 1 +description=512Kx8 static RAM +T 400 10450 5 10 0 0 0 0 1 +numslots=0 +P 1400 9900 1400 9600 1 0 0 +{ +T 1450 9700 5 8 1 1 0 0 1 +pinnumber=32 +T 1450 9700 5 8 0 1 0 2 1 +pinseq=32 +T 1400 9550 9 8 1 1 0 5 1 +pinlabel=VCC +T 1400 9400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2700 9200 2400 9200 1 0 0 +{ +T 2500 9250 5 8 1 1 0 0 1 +pinnumber=13 +T 2500 9150 5 8 0 1 0 2 1 +pinseq=13 +T 2350 9200 9 8 1 1 0 6 1 +pinlabel=DQ0 +T 2350 9200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8800 2400 8800 1 0 0 +{ +T 2500 8850 5 8 1 1 0 0 1 +pinnumber=14 +T 2500 8750 5 8 0 1 0 2 1 +pinseq=14 +T 2350 8800 9 8 1 1 0 6 1 +pinlabel=DQ1 +T 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1000 6050 5 8 1 1 0 0 1 +pinnumber=16 +T 1000 6050 5 8 0 0 0 0 1 +pinseq=20 +T 1000 6050 5 8 0 1 0 0 1 +pinlabel=16 +T 1000 6050 5 8 0 1 0 0 1 +pintype=pas +} +V 600 6300 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 650 6300 1200 6300 1 0 1 +{ +T 1000 6350 5 8 1 1 0 0 1 +pinnumber=3 +T 1000 6350 5 8 0 0 0 0 1 +pinseq=21 +T 1000 6350 5 8 0 1 0 0 1 +pinlabel=3 +T 1000 6350 5 8 0 1 0 0 1 +pintype=pas +} +V 300 6600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 350 6600 1200 6600 1 0 1 +{ +T 1000 6650 5 8 1 1 0 0 1 +pinnumber=15 +T 1000 6650 5 8 0 0 0 0 1 +pinseq=22 +T 1000 6650 5 8 0 1 0 0 1 +pinlabel=15 +T 1000 6650 5 8 0 1 0 0 1 +pintype=pas +} +V 600 6900 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 650 6900 1200 6900 1 0 1 +{ +T 1000 6950 5 8 1 1 0 0 1 +pinnumber=2 +T 1000 6950 5 8 0 0 0 0 1 +pinseq=23 +T 1000 6950 5 8 0 1 0 0 1 +pinlabel=2 +T 1000 6950 5 8 0 1 0 0 1 +pintype=pas +} +V 300 7200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 350 7200 1200 7200 1 0 1 +{ +T 1000 7250 5 8 1 1 0 0 1 +pinnumber=14 +T 1000 7250 5 8 0 0 0 0 1 +pinseq=24 +T 1000 7250 5 8 0 1 0 0 1 +pinlabel=14 +T 1000 7250 5 8 0 1 0 0 1 +pintype=pas +} +V 600 7500 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 650 7500 1200 7500 1 0 1 +{ +T 1000 7550 5 8 1 1 0 0 1 +pinnumber=1 +T 1000 7550 5 8 0 0 0 0 1 +pinseq=25 +T 1000 7550 5 8 0 1 0 0 1 +pinlabel=1 +T 1000 7550 5 8 0 1 0 0 1 +pintype=pas +} +L 39 234 703 8 3 0 0 0 -1 -1 +L 701 7832 38 7566 3 0 0 0 -1 -1 +T 100 8000 8 10 1 1 0 0 1 +refdes=CONN?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/DE9-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,121 @@ +v 20031231 1 +T 1000 3200 8 10 0 0 0 0 1 +device=DE9 +T 200 3200 8 10 1 1 0 0 1 +refdes=CONN? +P 650 2700 1200 2700 1 0 1 +{ +T 1000 2750 5 8 1 1 0 0 1 +pinnumber=1 +T 1000 2750 5 8 0 0 0 0 1 +pinseq=1 +T 1000 2750 5 8 0 1 0 0 1 +pinlabel=1 +T 1000 2750 5 8 0 1 0 0 1 +pintype=pas +} +P 350 2400 1200 2400 1 0 1 +{ +T 1000 2450 5 8 1 1 0 0 1 +pinnumber=6 +T 1000 2450 5 8 0 0 0 0 1 +pinseq=6 +T 1000 2450 5 8 0 1 0 0 1 +pinlabel=6 +T 1000 2450 5 8 0 1 0 0 1 +pintype=pas +} +P 650 2100 1200 2100 1 0 1 +{ +T 1000 2150 5 8 1 1 0 0 1 +pinnumber=2 +T 1000 2150 5 8 0 0 0 0 1 +pinseq=2 +T 1000 2150 5 8 0 1 0 0 1 +pinlabel=2 +T 1000 2150 5 8 0 1 0 0 1 +pintype=pas +} +P 350 1800 1200 1800 1 0 1 +{ +T 1000 1850 5 8 1 1 0 0 1 +pinnumber=7 +T 1000 1850 5 8 0 0 0 0 1 +pinseq=7 +T 1000 1850 5 8 0 1 0 0 1 +pinlabel=7 +T 1000 1850 5 8 0 1 0 0 1 +pintype=pas +} +P 650 1500 1200 1500 1 0 1 +{ +T 1000 1550 5 8 1 1 0 0 1 +pinnumber=3 +T 1000 1550 5 8 0 0 0 0 1 +pinseq=3 +T 1000 1550 5 8 0 1 0 0 1 +pinlabel=3 +T 1000 1550 5 8 0 1 0 0 1 +pintype=pas +} +P 350 1200 1200 1200 1 0 1 +{ +T 1000 1250 5 8 1 1 0 0 1 +pinnumber=8 +T 1000 1250 5 8 0 0 0 0 1 +pinseq=8 +T 1000 1250 5 8 0 1 0 0 1 +pinlabel=8 +T 1000 1250 5 8 0 1 0 0 1 +pintype=pas +} +P 650 900 1200 900 1 0 1 +{ +T 1000 950 5 8 1 1 0 0 1 +pinnumber=4 +T 1000 950 5 8 0 0 0 0 1 +pinseq=4 +T 1000 950 5 8 0 1 0 0 1 +pinlabel=4 +T 1000 950 5 8 0 1 0 0 1 +pintype=pas +} +P 350 600 1200 600 1 0 1 +{ +T 1000 650 5 8 1 1 0 0 1 +pinnumber=9 +T 1000 650 5 8 0 0 0 0 1 +pinseq=9 +T 1000 650 5 8 0 1 0 0 1 +pinlabel=9 +T 1000 650 5 8 0 1 0 0 1 +pintype=pas +} +P 650 300 1200 300 1 0 1 +{ +T 1000 350 5 8 1 1 0 0 1 +pinnumber=5 +T 1000 350 5 8 0 0 0 0 1 +pinseq=5 +T 1000 350 5 8 0 1 0 0 1 +pinlabel=5 +T 1000 350 5 8 0 1 0 0 1 +pintype=pas +} +A 750 150 150 250 110 3 0 0 0 -1 -1 +A 75 300 75 180 60 3 0 0 0 -1 -1 +A 750 2890 150 0 110 3 0 0 0 -1 -1 +A 75 2700 75 120 60 3 0 0 0 -1 -1 +V 300 600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 300 1200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 300 1800 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 300 2400 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 600 300 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 600 900 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 600 1500 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 600 2100 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 600 2700 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 0 300 0 2700 3 0 0 0 -1 -1 +L 38 234 702 8 3 0 0 0 -1 -1 +L 700 3031 37 2765 3 0 0 0 -1 -1 +L 900 137 900 2905 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/Dialight_591-2xxx.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,3 @@ +#pin name pin (pad) number +C 1 +A 2
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/Dialight_591-3001.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,5 @@ +#pin name pin (pad) number +C:red 1 +A:red 2 +A:green 3 +C:green 4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/Dialight_591-3101.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,5 @@ +#pin name pin (pad) number +C:yellow 1 +A:yellow 2 +A:green 3 +C:green 4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/Dialight_591-3201.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,5 @@ +#pin name pin (pad) number +C:red 1 +A:red 2 +A:yellow 3 +C:yellow 4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/EIA-se-drvr-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,22 @@ +L 300 800 800 500 3 0 0 0 -1 -1 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 200 3 0 0 0 -1 -1 +V 850 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=%d +T 350 500 9 8 0 1 0 0 1 +pinname=Drvr_In +T 350 500 5 8 0 1 0 2 1 +pintype=in +} +P 1100 500 900 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=%d +T 750 500 9 8 0 1 0 6 1 +pinname=Drvr_Out +T 750 500 5 8 0 1 0 8 1 +pintype=out +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/EIA-se-rcvr-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,22 @@ +L 300 800 800 500 3 0 0 0 -1 -1 +L 800 500 300 200 3 0 0 0 -1 -1 +L 300 800 300 200 3 0 0 0 -1 -1 +V 850 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 300 500 0 500 1 0 1 +{ +T 200 550 5 8 1 1 0 6 1 +pinnumber=%d +T 350 500 9 8 0 1 0 0 1 +pinname=Rcvr_In +T 350 500 5 8 0 1 0 2 1 +pintype=in +} +P 1100 500 900 500 1 0 0 +{ +T 900 550 5 8 1 1 0 0 1 +pinnumber=%d +T 750 500 9 8 0 1 0 6 1 +pinname=Rcvr_Out +T 750 500 5 8 0 1 0 8 1 +pintype=out +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/EPF10K30ATx144-confjtag.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,152 @@ +v 20040111 1 +T 4400 4900 8 10 1 1 0 6 1 +refdes=U? +T 400 4850 9 10 1 1 0 0 1 +device=EPF10K30ATx144 +T 400 5250 5 10 0 0 0 0 1 +footprint=LQFP144_20 +T 400 5450 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 5850 5 10 0 0 0 0 1 +description=EPF10K30ATx144 FPGA, configuration and JTAG pins +T 400 6050 5 10 0 0 0 0 1 +numslots=0 +P 100 4400 400 4400 1 0 0 +{ +T 300 4450 5 8 1 1 0 6 1 +pinnumber=105 +T 300 4350 5 8 0 1 0 8 1 +pinseq=105 +T 450 4400 9 8 1 1 0 0 1 +pinname=TDI +T 450 4400 5 8 0 1 0 2 1 +pintype=in +} +P 100 4000 400 4000 1 0 0 +{ +T 300 4050 5 8 1 1 0 6 1 +pinnumber=34 +T 300 3950 5 8 0 1 0 8 1 +pinseq=34 +T 450 4000 9 8 1 1 0 0 1 +pinname=TMS +T 450 4000 5 8 0 1 0 2 1 +pintype=in +} +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=4 +T 300 3550 5 8 0 1 0 8 1 +pinseq=4 +T 450 3600 9 8 1 1 0 0 1 +pinname=TDO +T 450 3600 5 8 0 1 0 2 1 +pintype=out +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=1 +T 300 3150 5 8 0 1 0 8 1 +pinseq=1 +T 525 3200 9 8 1 1 0 0 1 +pinname=TCK +T 525 3200 5 8 0 1 0 2 1 +pintype=in +} +L 500 3200 400 3275 3 0 0 0 -1 -1 +L 500 3200 400 3125 3 0 0 0 -1 -1 +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=106 +T 300 2350 5 8 0 1 0 8 1 +pinseq=106 +T 450 2400 9 8 1 1 0 0 1 +pinname=nCE +T 450 2400 5 8 0 1 0 2 1 +pintype=in +} +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=74 +T 300 1550 5 8 0 1 0 8 1 +pinseq=74 +T 450 1600 9 8 1 1 0 0 1 +pinname=nCONFIG +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=35 +T 300 1150 5 8 0 1 0 8 1 +pinseq=35 +T 450 1200 9 8 1 1 0 0 1 +pinname=nSTATUS +T 450 1200 5 8 0 1 0 2 1 +pintype=tri +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=2 +T 300 750 5 8 0 1 0 8 1 +pinseq=2 +T 450 800 9 8 1 1 0 0 1 +pinname=CONF_DONE +T 450 800 5 8 0 1 0 2 1 +pintype=out +} +P 100 400 400 400 1 0 0 +{ +T 300 450 5 8 1 1 0 6 1 +pinnumber=14 +T 300 350 5 8 0 1 0 8 1 +pinseq=14 +T 450 400 9 8 1 1 0 0 1 +pinname=INIT_DONE +T 450 400 5 8 0 1 0 2 1 +pintype=out +} +P 4700 4400 4400 4400 1 0 0 +{ +T 4500 4450 5 8 1 1 0 0 1 +pinnumber=77 +T 4500 4350 5 8 0 1 0 2 1 +pinseq=77 +T 4350 4400 9 8 1 1 0 6 1 +pinname=MSEL0 +T 4350 4400 5 8 0 1 0 8 1 +pintype=in +} +P 4700 4000 4400 4000 1 0 0 +{ +T 4500 4050 5 8 1 1 0 0 1 +pinnumber=76 +T 4500 3950 5 8 0 1 0 2 1 +pinseq=76 +T 4350 4000 9 8 1 1 0 6 1 +pinname=MSEL1 +T 4350 4000 5 8 0 1 0 8 1 +pintype=in +} +P 4700 2400 4400 2400 1 0 0 +{ +T 4500 2450 5 8 1 1 0 0 1 +pinnumber=3 +T 4500 2350 5 8 0 1 0 2 1 +pinseq=3 +T 4350 2400 9 8 1 1 0 6 1 +pinname=nCEO +T 4350 2400 5 8 0 1 0 8 1 +pintype=out +} +B 400 0 4000 4800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 2000 1600 9 10 1 0 0 0 1 +CONFIGURATION +T 2400 1300 9 10 1 0 0 0 1 +& JTAG
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/EPF10K30ATx144-global.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,110 @@ +v 20040111 1 +T 4400 3300 8 10 1 1 0 6 1 +refdes=U? +T 400 3250 9 10 1 1 0 0 1 +device=EPF10K30ATx144 +T 400 3650 5 10 0 0 0 0 1 +footprint=LQFP144_20 +T 400 3850 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 4250 5 10 0 0 0 0 1 +description=EPF10K30ATx144 FPGA, global input pins +T 400 4450 5 10 0 0 0 0 1 +numslots=0 +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=55 +T 300 2750 5 8 0 1 0 8 1 +pinseq=55 +T 525 2800 9 8 1 1 0 0 1 +pinname=GCLK0 +T 525 2800 5 8 0 1 0 2 1 +pintype=in +} +L 500 2800 400 2875 3 0 0 0 -1 -1 +L 500 2800 400 2725 3 0 0 0 -1 -1 +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=125 +T 300 2350 5 8 0 1 0 8 1 +pinseq=125 +T 525 2400 9 8 1 1 0 0 1 +pinname=GCLK1 +T 525 2400 5 8 0 1 0 2 1 +pintype=in +} +L 500 2400 400 2475 3 0 0 0 -1 -1 +L 500 2400 400 2325 3 0 0 0 -1 -1 +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=54 +T 300 1550 5 8 0 1 0 8 1 +pinseq=54 +T 450 1600 9 8 1 1 0 0 1 +pinname=GIN0 +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=56 +T 300 1150 5 8 0 1 0 8 1 +pinseq=56 +T 450 1200 9 8 1 1 0 0 1 +pinname=GIN1 +T 450 1200 5 8 0 1 0 2 1 +pintype=in +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=124 +T 300 750 5 8 0 1 0 8 1 +pinseq=124 +T 450 800 9 8 1 1 0 0 1 +pinname=GIN2 +T 450 800 5 8 0 1 0 2 1 +pintype=in +} +P 100 400 400 400 1 0 0 +{ +T 300 450 5 8 1 1 0 6 1 +pinnumber=126 +T 300 350 5 8 0 1 0 8 1 +pinseq=126 +T 450 400 9 8 1 1 0 0 1 +pinname=GIN3 +T 450 400 5 8 0 1 0 2 1 +pintype=in +} +P 4700 1600 4400 1600 1 0 0 +{ +T 4500 1650 5 8 1 1 0 0 1 +pinnumber=122 +T 4500 1550 5 8 0 1 0 2 1 +pinseq=122 +T 4350 1600 9 8 1 1 0 6 1 +pinname=DEV_CLRn +T 4350 1600 5 8 0 1 0 8 1 +pintype=in +} +P 4700 1200 4400 1200 1 0 0 +{ +T 4500 1250 5 8 1 1 0 0 1 +pinnumber=128 +T 4500 1150 5 8 0 1 0 2 1 +pinseq=128 +T 4350 1200 9 8 1 1 0 6 1 +pinname=DEV_OE +T 4350 1200 5 8 0 1 0 8 1 +pintype=in +} +B 400 0 4000 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1800 1500 9 10 1 0 0 0 1 +GLOBAL +T 1900 1200 9 10 1 0 0 0 1 +INPUTS
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/EPF10K30ATx144-power.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,335 @@ +v 20040111 1 +T 9200 1800 8 10 1 1 0 0 1 +refdes=U? +T 200 1350 9 10 1 1 0 0 1 +device=EPF10K30ATx144 +T 300 2950 5 10 0 0 0 0 1 +footprint=LQFP144_20 +T 300 3150 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 300 3550 5 10 0 0 0 0 1 +description=EPF10K30ATx144 FPGA, power pins +T 300 3750 5 10 0 0 0 0 1 +numslots=0 +P 400 2300 400 2000 1 0 0 +{ +T 450 2100 5 8 1 1 0 0 1 +pinnumber=6 +T 450 2100 5 8 0 1 0 2 1 +pinseq=6 +T 400 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 400 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 1000 2300 1000 2000 1 0 0 +{ +T 1050 2100 5 8 1 1 0 0 1 +pinnumber=25 +T 1050 2100 5 8 0 1 0 2 1 +pinseq=25 +T 1000 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 1000 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 1600 2300 1600 2000 1 0 0 +{ +T 1650 2100 5 8 1 1 0 0 1 +pinnumber=52 +T 1650 2100 5 8 0 1 0 2 1 +pinseq=52 +T 1600 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 1600 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 2200 2300 2200 2000 1 0 0 +{ +T 2250 2100 5 8 1 1 0 0 1 +pinnumber=53 +T 2250 2100 5 8 0 1 0 2 1 +pinseq=53 +T 2200 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 2200 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 2800 2300 2800 2000 1 0 0 +{ +T 2850 2100 5 8 1 1 0 0 1 +pinnumber=75 +T 2850 2100 5 8 0 1 0 2 1 +pinseq=75 +T 2800 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 2800 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 3400 2300 3400 2000 1 0 0 +{ +T 3450 2100 5 8 1 1 0 0 1 +pinnumber=93 +T 3450 2100 5 8 0 1 0 2 1 +pinseq=93 +T 3400 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 3400 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 4000 2300 4000 2000 1 0 0 +{ +T 4050 2100 5 8 1 1 0 0 1 +pinnumber=123 +T 4050 2100 5 8 0 1 0 2 1 +pinseq=123 +T 4000 1950 9 8 1 1 0 5 1 +pinlabel=VCCint +T 4000 1800 5 8 0 1 0 5 1 +pintype=pwr +} +P 4600 2300 4600 2000 1 0 0 +{ +T 4650 2100 5 8 1 1 0 0 1 +pinnumber=5 +T 4650 2100 5 8 0 1 0 2 1 +pinseq=5 +T 4600 1950 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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/HDSL-xfmr-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,88 @@ +v 20040111 1 +L 500 1100 200 1100 3 0 0 0 -1 -1 +A 500 1000 100 270 180 3 0 0 0 -1 -1 +A 500 400 100 270 180 3 0 0 0 -1 -1 +A 500 200 100 270 180 3 0 0 0 -1 -1 +L 500 100 200 100 3 0 0 0 -1 -1 +L 1000 100 1300 100 3 0 0 0 -1 -1 +A 1000 200 100 90 180 3 0 0 0 -1 -1 +A 1000 400 100 90 180 3 0 0 0 -1 -1 +A 1000 1000 100 90 180 3 0 0 0 -1 -1 +L 1000 1100 1300 1100 3 0 0 0 -1 -1 +L 700 1200 700 0 3 0 0 0 -1 -1 +L 800 1200 800 0 3 0 0 0 -1 -1 +P 200 100 0 100 1 0 1 +{ +T 100 150 5 8 1 1 0 0 1 +pinnumber=5 +T 100 150 5 8 0 0 0 0 1 +pinseq=5 +T 100 150 5 8 0 1 0 0 1 +pinlabel=5 +T 100 150 5 8 0 1 0 0 1 +pintype=pas +} +P 200 700 0 700 1 0 1 +{ +T 100 750 5 8 1 1 0 0 1 +pinnumber=4 +T 100 750 5 8 0 0 0 0 1 +pinseq=4 +T 100 750 5 8 0 1 0 0 1 +pinlabel=4 +T 100 750 5 8 0 1 0 0 1 +pintype=pas +} +P 200 500 0 500 1 0 1 +{ +T 100 550 5 8 1 1 0 0 1 +pinnumber=2 +T 100 550 5 8 0 0 0 0 1 +pinseq=2 +T 100 550 5 8 0 1 0 0 1 +pinlabel=2 +T 100 550 5 8 0 1 0 0 1 +pintype=pas +} +P 200 1100 0 1100 1 0 1 +{ +T 100 1150 5 8 1 1 0 0 1 +pinnumber=1 +T 100 1150 5 8 0 0 0 0 1 +pinseq=1 +T 100 1150 5 8 0 1 0 0 1 +pinlabel=1 +T 100 1150 5 8 0 1 0 0 1 +pintype=pas +} +P 1500 100 1300 100 1 0 0 +{ +T 1400 150 5 8 1 1 0 0 1 +pinnumber=7 +T 1400 150 5 8 0 0 0 0 1 +pinseq=7 +T 1400 150 5 8 0 1 0 0 1 +pinlabel=7 +T 1400 150 5 8 0 1 0 0 1 +pintype=pas +} +P 1500 1100 1300 1100 1 0 0 +{ +T 1400 1150 5 8 1 1 0 0 1 +pinnumber=9 +T 1400 1150 5 8 0 0 0 0 1 +pinseq=9 +T 1400 1150 5 8 0 1 0 0 1 +pinlabel=9 +T 1400 1150 5 8 0 1 0 0 1 +pintype=pas +} +T 300 1300 8 10 1 1 0 0 1 +refdes=T? +T 300 1300 8 10 0 0 0 0 1 +device=TRANSFORMER +A 500 800 100 270 180 3 0 0 0 -1 -1 +A 1000 800 100 90 180 3 0 0 0 -1 -1 +A 1000 600 100 90 180 3 0 0 0 -1 -1 +L 500 500 200 500 3 0 0 0 -1 -1 +L 500 700 200 700 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/HM628512-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,369 @@ +v 20040111 1 +T 2400 9700 8 10 1 1 0 6 1 +refdes=U? +T 400 9650 9 9 1 0 0 0 1 +HM628512 +T 400 9850 5 10 0 0 0 0 1 +device=HM628512 +T 400 10050 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 10250 5 10 0 0 0 0 1 +description=512Kx8 static RAM +T 400 10450 5 10 0 0 0 0 1 +numslots=0 +P 1400 9900 1400 9600 1 0 0 +{ +T 1450 9700 5 8 1 1 0 0 1 +pinnumber=32 +T 1450 9700 5 8 0 1 0 2 1 +pinseq=32 +T 1400 9550 9 8 1 1 0 5 1 +pinlabel=VCC +T 1400 9400 5 8 0 1 0 5 1 +pintype=pwr +} +P 2700 9200 2400 9200 1 0 0 +{ +T 2500 9250 5 8 1 1 0 0 1 +pinnumber=13 +T 2500 9150 5 8 0 1 0 2 1 +pinseq=13 +T 2350 9200 9 8 1 1 0 6 1 +pinlabel=DQ0 +T 2350 9200 5 8 0 1 0 8 1 +pintype=tri +} +P 2700 8800 2400 8800 1 0 0 +{ +T 2500 8850 5 8 1 1 0 0 1 +pinnumber=14 +T 2500 8750 5 8 0 1 0 2 1 +pinseq=14 +T 2350 8800 9 8 1 1 0 6 1 +pinlabel=DQ1 +T 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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/MAX232-com-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,65 @@ +B 300 0 2800 3300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +% left side pins +P 0 2900 300 2900 1 0 0 +{ +attr pinname=C1pos +T 350 2900 9 8 1 1 0 0 1 +pinlabel=C1+ +T 200 2950 5 8 1 1 0 6 1 +pinnumber=1 +} +P 0 2000 300 2000 1 0 0 +{ +attr pinname=C1neg +T 350 2000 9 8 1 1 0 0 1 +pinlabel=C1- +T 200 2050 5 8 1 1 0 6 1 +pinnumber=3 +} +P 0 1600 300 1600 1 0 0 +{ +attr pinname=C2pos +T 350 1600 9 8 1 1 0 0 1 +pinlabel=C2+ +T 200 1650 5 8 1 1 0 6 1 +pinnumber=4 +} +P 0 700 300 700 1 0 0 +{ +attr pinname=C2neg +T 350 700 9 8 1 1 0 0 1 +pinlabel=C2- +T 200 750 5 8 1 1 0 6 1 +pinnumber=5 +} +% right side pins +P 3100 2900 3400 2900 1 0 1 +{ +T 3050 2900 9 8 1 1 0 6 1 +pinname=Vcc +T 3200 2950 5 8 1 1 0 0 1 +pinnumber=16 +} +P 3100 2400 3400 2400 1 0 1 +{ +attr pinname=Vpos +T 3050 2400 9 8 1 1 0 6 1 +pinlabel=V+ +T 3200 2450 5 8 1 1 0 0 1 +pinnumber=2 +} +P 3100 1800 3400 1800 1 0 1 +{ +attr pinname=Vneg +T 3050 1800 9 8 1 1 0 6 1 +pinlabel=V- +T 3200 1850 5 8 1 1 0 0 1 +pinnumber=6 +} +P 3100 200 3400 200 1 0 1 +{ +T 3050 200 9 8 1 1 0 6 1 +pinname=GND +T 3200 250 5 8 1 1 0 0 1 +pinnumber=15 +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/MAX232.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +#pin name #pin number +C1pos 1 +Vpos 2 +C1neg 3 +C2pos 4 +C2neg 5 +Vneg 6 +Drvr_Out:2 7 +Rcvr_In:2 8 +Rcvr_Out:2 9 +Drvr_In:2 10 +Drvr_In:1 11 +Rcvr_Out:1 12 +Rcvr_In:1 13 +Drvr_Out:1 14 +GND 15 +Vcc 16
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/MC68302_PGA-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,778 @@ +v 20040111 1 +T 3300 16700 8 10 1 1 0 6 1 +refdes=U? +T 500 16650 9 10 1 0 0 0 1 +MC68302 +T 500 16850 5 10 0 0 0 0 1 +device=MC68302 +T 500 17050 5 10 0 0 0 0 1 +footprint=PGA132 +T 500 17250 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 500 17450 5 10 0 0 0 0 1 +documentation= +T 500 17650 5 10 0 0 0 0 1 +description=MC68302 IMP, M68K bus (1 of 3) +T 500 17850 5 10 0 0 0 0 1 +numslots=0 +T 500 18050 5 10 0 0 0 0 1 +comment=pinseq numbers are PQFP package pins +P 200 16200 500 16200 1 0 0 +{ +T 400 16250 5 8 1 1 0 6 1 +pinnumber=G1 +T 400 16150 5 8 0 1 0 8 1 +pinseq=1 +T 550 16200 9 8 1 1 0 0 1 +pinlabel=A1 +T 550 16200 5 8 0 1 0 2 1 +pintype=tri +} +P 200 15800 500 15800 1 0 0 +{ +T 400 15850 5 8 1 1 0 6 1 +pinnumber=G3 +T 400 15750 5 8 0 1 0 8 1 +pinseq=2 +T 550 15800 9 8 1 1 0 0 1 +pinlabel=A2 +T 550 15800 5 8 0 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+pinlabel=D6 +T 450 3200 5 8 0 1 0 2 1 +pintype=in +} +P 3500 3200 3200 3200 1 0 0 +{ +T 3300 3250 5 8 1 1 0 0 1 +pinnumber=26 +T 3300 3150 5 8 0 1 0 2 1 +pinseq=26 +T 3150 3200 9 8 1 1 0 6 1 +pinlabel=D6 +T 3150 3200 5 8 0 1 0 8 1 +pintype=in +} +P 100 2800 400 2800 1 0 0 +{ +T 300 2850 5 8 1 1 0 6 1 +pinnumber=27 +T 300 2750 5 8 0 1 0 8 1 +pinseq=27 +T 450 2800 9 8 1 1 0 0 1 +pinlabel=D5 +T 450 2800 5 8 0 1 0 2 1 +pintype=in +} +P 3500 2800 3200 2800 1 0 0 +{ +T 3300 2850 5 8 1 1 0 0 1 +pinnumber=28 +T 3300 2750 5 8 0 1 0 2 1 +pinseq=28 +T 3150 2800 9 8 1 1 0 6 1 +pinlabel=D5 +T 3150 2800 5 8 0 1 0 8 1 +pintype=in +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=29 +T 300 2350 5 8 0 1 0 8 1 +pinseq=29 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=D4 +T 450 2400 5 8 0 1 0 2 1 +pintype=in +} +P 3500 2400 3200 2400 1 0 0 +{ +T 3300 2450 5 8 1 1 0 0 1 +pinnumber=30 +T 3300 2350 5 8 0 1 0 2 1 +pinseq=30 +T 3150 2400 9 8 1 1 0 6 1 +pinlabel=D4 +T 3150 2400 5 8 0 1 0 8 1 +pintype=in +} +P 100 2000 400 2000 1 0 0 +{ +T 300 2050 5 8 1 1 0 6 1 +pinnumber=31 +T 300 1950 5 8 0 1 0 8 1 +pinseq=31 +T 450 2000 9 8 1 1 0 0 1 +pinlabel=D3 +T 450 2000 5 8 0 1 0 2 1 +pintype=in +} +P 3500 2000 3200 2000 1 0 0 +{ +T 3300 2050 5 8 1 1 0 0 1 +pinnumber=32 +T 3300 1950 5 8 0 1 0 2 1 +pinseq=32 +T 3150 2000 9 8 1 1 0 6 1 +pinlabel=D3 +T 3150 2000 5 8 0 1 0 8 1 +pintype=in +} +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=33 +T 300 1550 5 8 0 1 0 8 1 +pinseq=33 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=D2 +T 450 1600 5 8 0 1 0 2 1 +pintype=in +} +P 3500 1600 3200 1600 1 0 0 +{ +T 3300 1650 5 8 1 1 0 0 1 +pinnumber=34 +T 3300 1550 5 8 0 1 0 2 1 +pinseq=34 +T 3150 1600 9 8 1 1 0 6 1 +pinlabel=D2 +T 3150 1600 5 8 0 1 0 8 1 +pintype=in +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=35 +T 300 1150 5 8 0 1 0 8 1 +pinseq=35 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=D1 +T 450 1200 5 8 0 1 0 2 1 +pintype=in +} +P 3500 1200 3200 1200 1 0 0 +{ +T 3300 1250 5 8 1 1 0 0 1 +pinnumber=36 +T 3300 1150 5 8 0 1 0 2 1 +pinseq=36 +T 3150 1200 9 8 1 1 0 6 1 +pinlabel=D1 +T 3150 1200 5 8 0 1 0 8 1 +pintype=in +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=37 +T 300 750 5 8 0 1 0 8 1 +pinseq=37 +T 450 800 9 8 1 1 0 0 1 +pinlabel=D0 +T 450 800 5 8 0 1 0 2 1 +pintype=in +} +P 3500 800 3200 800 1 0 0 +{ +T 3300 850 5 8 1 1 0 0 1 +pinnumber=38 +T 3300 750 5 8 0 1 0 2 1 +pinseq=38 +T 3150 800 9 8 1 1 0 6 1 +pinlabel=D0 +T 3150 800 5 8 0 1 0 8 1 +pintype=in +} +P 1000 100 1000 400 1 0 0 +{ +T 1050 200 5 8 1 1 0 0 1 +pinnumber=39 +T 1050 200 5 8 0 1 0 2 1 +pinseq=39 +T 1000 450 9 8 1 1 0 3 1 +pinlabel=GND +T 1000 600 5 8 0 1 0 3 1 +pintype=pas +} +P 1400 100 1400 400 1 0 0 +{ +T 1450 200 5 8 1 1 0 0 1 +pinnumber=40 +T 1450 200 5 8 0 1 0 2 1 +pinseq=40 +T 1400 450 9 8 1 1 0 3 1 +pinlabel=GND +T 1400 600 5 8 0 1 0 3 1 +pintype=pas +} +P 1800 100 1800 400 1 0 0 +{ +T 1850 200 5 8 1 1 0 0 1 +pinnumber=41 +T 1850 200 5 8 0 1 0 2 1 +pinseq=41 +T 1800 450 9 8 1 1 0 3 1 +pinlabel=GND +T 1800 600 5 8 0 1 0 3 1 +pintype=pas +} +P 2200 100 2200 400 1 0 0 +{ +T 2250 200 5 8 1 1 0 0 1 +pinnumber=42 +T 2250 200 5 8 0 1 0 2 1 +pinseq=42 +T 2200 450 9 8 1 1 0 3 1 +pinlabel=GND +T 2200 600 5 8 0 1 0 3 1 +pintype=pas +} +P 2600 100 2600 400 1 0 0 +{ +T 2650 200 5 8 1 1 0 0 1 +pinnumber=43 +T 2650 200 5 8 0 1 0 2 1 +pinseq=43 +T 2600 450 9 8 1 1 0 3 1 +pinlabel=GND +T 2600 600 5 8 0 1 0 3 1 +pintype=pas +} +B 400 400 2800 8000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 950 4400 9 10 1 0 90 3 1 +EVEN POD +T 2800 4400 9 10 1 0 90 3 1 +ODD POD +T 3200 8500 8 10 1 1 0 6 1 +refdes=J? +T 400 8500 5 10 1 1 0 0 1 +device=MICTOR38 +T 400 8900 5 10 0 0 0 0 1 +footprint=AMP_MICTOR38 +T 400 9100 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 9300 5 10 0 0 0 0 1 +documentation= +T 400 9500 5 10 0 0 0 0 1 +description=MICTOR38 connector, logic analyser hook-up +T 400 9700 5 10 0 0 0 0 1 +numslots=0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/MICTOR38-1.trg Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,94 @@ +# This is the template file for creating symbols with tragesym +# every line starting with '#' is a comment line. + +[options] +# rotate_labels rotates the pintext of top and bottom pins +# wordswap swaps labels if the pin is on the right side an looks like this: +# "PB1 (CLK)" +wordswap=yes +rotate_labels=no +sort_labels=no +generate_pinseq=yes +sym_width=2800 +pinwidthvertikal=400 +pinwidthhorizontal=400 + +[geda_attr] +# name will be printed in the top of the symbol +# if you have a device with slots, you'll have to use slot= and slotdef= +# use comment= if there are special information you want to add +version=20030525 +name=MICTOR38 +device=MICTOR38 +refdes=J? +footprint=AMP_MICTOR38 +description=MICTOR38 connector, logic analyser hook-up +documentation= +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +numslots=0 +#slot=1 +#slotdef=1: +#slotdef=2: +#slotdef=3: +#slotdef=4: +#comment= +#comment= + +[pins] +# tabseparated list of pin descriptions +# pinnr is the physical number of the pin +# seq is the pinseq= attribute, leave it blank if it doesn't matter +# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr) +# style can be (line,dot,clk,dotclk,none). none if only want to add a net +# posit. can be (l,r,t,b) or empty for nets +# net specifies the name of the Vcc or GND name +# label represents the pinlabel. +# negation lines can be added with _Q_ +# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences +#----------------------------------------------------- +#pinnr seq type style posit. net label +#----------------------------------------------------- +1 pas line l NC +2 pas line r NC +3 pas line l NC +4 pas line r NC +5 clk clk l CLK +6 clk clk r CLK +7 in line l D15 +8 in line r D15 +9 in line l D14 +10 in line r D14 +11 in line l D13 +12 in line r D13 +13 in line l D12 +14 in line r D12 +15 in line l D11 +16 in line r D11 +17 in line l D10 +18 in line r D10 +19 in line l D9 +20 in line r D9 +21 in line l D8 +22 in line r D8 +23 in line l D7 +24 in line r D7 +25 in line l D6 +26 in line r D6 +27 in line l D5 +28 in line r D5 +29 in line l D4 +30 in line r D4 +31 in line l D3 +32 in line r D3 +33 in line l D2 +34 in line r D2 +35 in line l D1 +36 in line r D1 +37 in line l D0 +38 in line r D0 + +39 pas line b GND +40 pas line b GND +41 pas line b GND +42 pas line b GND +43 pas line b GND
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/PI90LV179.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,9 @@ +#pin name pin number +Vcc 1 +Rcvr_Out 2 +Drvr_In 3 +GND 4 +Drvr_Out_P 5 +Drvr_Out_N 6 +Rcvr_In_N 7 +Rcvr_In_P 8
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/RS8973-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,306 @@ +v 20040111 1 +T 3200 10600 8 10 1 1 0 6 1 +refdes=U? +T 400 10550 9 10 1 0 0 0 1 +RS8973 +T 400 10750 5 10 0 0 0 0 1 +device=RS8973 +T 400 10950 5 10 0 0 0 0 1 +footprint=QFP100_R +T 400 11150 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 11350 5 10 0 0 0 0 1 +documentation= +T 400 11550 5 10 0 0 0 0 1 +description=RS8973 bitpump, MCI (1 of 5) +T 400 11750 5 10 0 0 0 0 1 +numslots=0 +P 100 10100 400 10100 1 0 0 +{ +T 300 10150 5 8 1 1 0 6 1 +pinnumber=19 +T 300 10050 5 8 0 1 0 8 1 +pinseq=19 +T 450 10100 9 8 1 1 0 0 1 +pinlabel=MOTEL +T 450 10100 5 8 0 1 0 2 1 +pintype=in +} +L 706 10224 1002 10224 3 0 0 0 -1 -1 +P 100 9700 400 9700 1 0 0 +{ +T 300 9750 5 8 1 1 0 6 1 +pinnumber=5 +T 300 9650 5 8 0 1 0 8 1 +pinseq=5 +T 450 9700 9 8 1 1 0 0 1 +pinlabel=ALE +T 450 9700 5 8 0 1 0 2 1 +pintype=in +} +P 100 9300 400 9300 1 0 0 +{ +T 300 9350 5 8 1 1 0 6 1 +pinnumber=2 +T 300 9250 5 8 0 1 0 8 1 +pinseq=2 +T 450 9300 9 8 1 1 0 0 1 +pinlabel=CS +T 450 9300 5 8 0 1 0 2 1 +pintype=in +} +L 450 9424 662 9424 3 0 0 0 -1 -1 +P 100 8900 400 8900 1 0 0 +{ +T 300 8950 5 8 1 1 0 6 1 +pinnumber=3 +T 300 8850 5 8 0 1 0 8 1 +pinseq=3 +T 450 8900 9 8 1 1 0 0 1 +pinlabel=RD/DS +T 450 8900 5 8 0 1 0 2 1 +pintype=in +} +L 450 9024 658 9024 3 0 0 0 -1 -1 +L 730 9024 934 9024 3 0 0 0 -1 -1 +P 100 8500 400 8500 1 0 0 +{ +T 300 8550 5 8 1 1 0 6 1 +pinnumber=4 +T 300 8450 5 8 0 1 0 8 1 +pinseq=4 +T 450 8500 9 8 1 1 0 0 1 +pinlabel=WR/R/W +T 450 8500 5 8 0 1 0 2 1 +pintype=in +} +L 450 8624 702 8624 3 0 0 0 -1 -1 +L 950 8624 1098 8624 3 0 0 0 -1 -1 +P 100 7700 400 7700 1 0 0 +{ +T 300 7750 5 8 1 1 0 6 1 +pinnumber=8 +T 300 7650 5 8 0 1 0 8 1 +pinseq=8 +T 450 7700 9 8 1 1 0 0 1 +pinlabel=AD0 +T 450 7700 5 8 0 1 0 2 1 +pintype=tri +} +P 100 7300 400 7300 1 0 0 +{ +T 300 7350 5 8 1 1 0 6 1 +pinnumber=9 +T 300 7250 5 8 0 1 0 8 1 +pinseq=9 +T 450 7300 9 8 1 1 0 0 1 +pinlabel=AD1 +T 450 7300 5 8 0 1 0 2 1 +pintype=tri +} +P 100 6900 400 6900 1 0 0 +{ +T 300 6950 5 8 1 1 0 6 1 +pinnumber=10 +T 300 6850 5 8 0 1 0 8 1 +pinseq=10 +T 450 6900 9 8 1 1 0 0 1 +pinlabel=AD2 +T 450 6900 5 8 0 1 0 2 1 +pintype=tri +} +P 100 6500 400 6500 1 0 0 +{ +T 300 6550 5 8 1 1 0 6 1 +pinnumber=11 +T 300 6450 5 8 0 1 0 8 1 +pinseq=11 +T 450 6500 9 8 1 1 0 0 1 +pinlabel=AD3 +T 450 6500 5 8 0 1 0 2 1 +pintype=tri +} +P 100 6100 400 6100 1 0 0 +{ +T 300 6150 5 8 1 1 0 6 1 +pinnumber=12 +T 300 6050 5 8 0 1 0 8 1 +pinseq=12 +T 450 6100 9 8 1 1 0 0 1 +pinlabel=AD4 +T 450 6100 5 8 0 1 0 2 1 +pintype=tri +} +P 100 5700 400 5700 1 0 0 +{ +T 300 5750 5 8 1 1 0 6 1 +pinnumber=13 +T 300 5650 5 8 0 1 0 8 1 +pinseq=13 +T 450 5700 9 8 1 1 0 0 1 +pinlabel=AD5 +T 450 5700 5 8 0 1 0 2 1 +pintype=tri +} +P 100 5300 400 5300 1 0 0 +{ +T 300 5350 5 8 1 1 0 6 1 +pinnumber=14 +T 300 5250 5 8 0 1 0 8 1 +pinseq=14 +T 450 5300 9 8 1 1 0 0 1 +pinlabel=AD6 +T 450 5300 5 8 0 1 0 2 1 +pintype=tri +} +P 100 4900 400 4900 1 0 0 +{ +T 300 4950 5 8 1 1 0 6 1 +pinnumber=18 +T 300 4850 5 8 0 1 0 8 1 +pinseq=18 +T 450 4900 9 8 1 1 0 0 1 +pinlabel=AD7 +T 450 4900 5 8 0 1 0 2 1 +pintype=tri +} +P 100 4100 400 4100 1 0 0 +{ +T 300 4150 5 8 1 1 0 6 1 +pinnumber=28 +T 300 4050 5 8 0 1 0 8 1 +pinseq=28 +T 450 4100 9 8 1 1 0 0 1 +pinlabel=ADDR0 +T 450 4100 5 8 0 1 0 2 1 +pintype=in +} +P 100 3700 400 3700 1 0 0 +{ +T 300 3750 5 8 1 1 0 6 1 +pinnumber=27 +T 300 3650 5 8 0 1 0 8 1 +pinseq=27 +T 450 3700 9 8 1 1 0 0 1 +pinlabel=ADDR1 +T 450 3700 5 8 0 1 0 2 1 +pintype=in +} +P 100 3300 400 3300 1 0 0 +{ +T 300 3350 5 8 1 1 0 6 1 +pinnumber=26 +T 300 3250 5 8 0 1 0 8 1 +pinseq=26 +T 450 3300 9 8 1 1 0 0 1 +pinlabel=ADDR2 +T 450 3300 5 8 0 1 0 2 1 +pintype=in +} +P 100 2900 400 2900 1 0 0 +{ +T 300 2950 5 8 1 1 0 6 1 +pinnumber=25 +T 300 2850 5 8 0 1 0 8 1 +pinseq=25 +T 450 2900 9 8 1 1 0 0 1 +pinlabel=ADDR3 +T 450 2900 5 8 0 1 0 2 1 +pintype=in +} +P 100 2500 400 2500 1 0 0 +{ +T 300 2550 5 8 1 1 0 6 1 +pinnumber=24 +T 300 2450 5 8 0 1 0 8 1 +pinseq=24 +T 450 2500 9 8 1 1 0 0 1 +pinlabel=ADDR4 +T 450 2500 5 8 0 1 0 2 1 +pintype=in +} +P 100 2100 400 2100 1 0 0 +{ +T 300 2150 5 8 1 1 0 6 1 +pinnumber=23 +T 300 2050 5 8 0 1 0 8 1 +pinseq=23 +T 450 2100 9 8 1 1 0 0 1 +pinlabel=ADDR5 +T 450 2100 5 8 0 1 0 2 1 +pintype=in +} +P 100 1700 400 1700 1 0 0 +{ +T 300 1750 5 8 1 1 0 6 1 +pinnumber=22 +T 300 1650 5 8 0 1 0 8 1 +pinseq=22 +T 450 1700 9 8 1 1 0 0 1 +pinlabel=ADDR6 +T 450 1700 5 8 0 1 0 2 1 +pintype=in +} +P 100 1300 400 1300 1 0 0 +{ +T 300 1350 5 8 1 1 0 6 1 +pinnumber=21 +T 300 1250 5 8 0 1 0 8 1 +pinseq=21 +T 450 1300 9 8 1 1 0 0 1 +pinlabel=ADDR7 +T 450 1300 5 8 0 1 0 2 1 +pintype=in +} +P 100 500 400 500 1 0 0 +{ +T 300 550 5 8 1 1 0 6 1 +pinnumber=20 +T 300 450 5 8 0 1 0 8 1 +pinseq=20 +T 450 500 9 8 1 1 0 0 1 +pinlabel=MUXED +T 450 500 5 8 0 1 0 2 1 +pintype=in +} +P 3500 10100 3200 10100 1 0 0 +{ +T 3300 10150 5 8 1 1 0 0 1 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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/RS8973-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,169 @@ +v 20040111 1 +T 3200 4100 8 10 1 1 0 6 1 +refdes=U? +T 400 4050 9 10 1 0 0 0 1 +RS8973 +T 400 4250 5 10 0 0 0 0 1 +device=RS8973 +T 400 4450 5 10 0 0 0 0 1 +footprint=QFP100_R +T 400 4650 5 10 0 0 0 0 1 +author=Michael Sokolov <msokolov@ivan.Harhan.ORG> +T 400 4850 5 10 0 0 0 0 1 +documentation= +T 400 5050 5 10 0 0 0 0 1 +description=RS8973 bitpump, data path (2 of 5) +T 400 5250 5 10 0 0 0 0 1 +numslots=0 +P 100 3600 400 3600 1 0 0 +{ +T 300 3650 5 8 1 1 0 6 1 +pinnumber=86 +T 300 3550 5 8 0 1 0 8 1 +pinseq=86 +T 450 3600 9 8 1 1 0 0 1 +pinlabel=TQ0 +T 450 3600 5 8 0 1 0 2 1 +pintype=in +} +P 100 3200 400 3200 1 0 0 +{ +T 300 3250 5 8 1 1 0 6 1 +pinnumber=85 +T 300 3150 5 8 0 1 0 8 1 +pinseq=85 +T 450 3200 9 8 1 1 0 0 1 +pinlabel=TQ1/TDAT +T 450 3200 5 8 0 1 0 2 1 +pintype=in +} +P 100 2400 400 2400 1 0 0 +{ +T 300 2450 5 8 1 1 0 6 1 +pinnumber=89 +T 300 2350 5 8 0 1 0 8 1 +pinseq=89 +T 450 2400 9 8 1 1 0 0 1 +pinlabel=RQ0/BCLK +T 450 2400 5 8 0 1 0 2 1 +pintype=out +} +P 100 2000 400 2000 1 0 0 +{ +T 300 2050 5 8 1 1 0 6 1 +pinnumber=88 +T 300 1950 5 8 0 1 0 8 1 +pinseq=88 +T 450 2000 9 8 1 1 0 0 1 +pinlabel=RQ1/RDAT +T 450 2000 5 8 0 1 0 2 1 +pintype=out +} +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=87 +T 300 1550 5 8 0 1 0 8 1 +pinseq=87 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=QCLK +T 450 1600 5 8 0 1 0 2 1 +pintype=out +} +P 100 800 400 800 1 0 0 +{ +T 300 850 5 8 1 1 0 6 1 +pinnumber=91 +T 300 750 5 8 0 1 0 8 1 +pinseq=91 +T 525 800 9 8 1 1 0 0 1 +pinlabel=TBCLK +T 525 800 5 8 0 1 0 2 1 +pintype=clk +} +L 500 800 400 875 3 0 0 0 -1 -1 +L 500 800 400 725 3 0 0 0 -1 -1 +P 100 400 400 400 1 0 0 +{ +T 300 450 5 8 1 1 0 6 1 +pinnumber=90 +T 300 350 5 8 0 1 0 8 1 +pinseq=90 +T 525 400 9 8 1 1 0 0 1 +pinlabel=RBCLK +T 525 400 5 8 0 1 0 2 1 +pintype=clk +} +L 500 400 400 475 3 0 0 0 -1 -1 +L 500 400 400 325 3 0 0 0 -1 -1 +P 3500 3600 3200 3600 1 0 0 +{ +T 3300 3650 5 8 1 1 0 0 1 +pinnumber=71 +T 3300 3550 5 8 0 1 0 2 1 +pinseq=71 +T 3150 3600 9 8 1 1 0 6 1 +pinlabel=TXP +T 3150 3600 5 8 0 1 0 8 1 +pintype=out +} +P 3500 3200 3200 3200 1 0 0 +{ +T 3300 3250 5 8 1 1 0 0 1 +pinnumber=74 +T 3300 3150 5 8 0 1 0 2 1 +pinseq=74 +T 3150 3200 9 8 1 1 0 6 1 +pinlabel=TXN +T 3150 3200 5 8 0 1 0 8 1 +pintype=out +} +P 3500 2400 3200 2400 1 0 0 +{ +T 3300 2450 5 8 1 1 0 0 1 +pinnumber=77 +T 3300 2350 5 8 0 1 0 2 1 +pinseq=77 +T 3150 2400 9 8 1 1 0 6 1 +pinlabel=RXP +T 3150 2400 5 8 0 1 0 8 1 +pintype=in +} +P 3500 2000 3200 2000 1 0 0 +{ +T 3300 2050 5 8 1 1 0 0 1 +pinnumber=78 +T 3300 1950 5 8 0 1 0 2 1 +pinseq=78 +T 3150 2000 9 8 1 1 0 6 1 +pinlabel=RXN +T 3150 2000 5 8 0 1 0 8 1 +pintype=in +} +P 3500 1200 3200 1200 1 0 0 +{ +T 3300 1250 5 8 1 1 0 0 1 +pinnumber=79 +T 3300 1150 5 8 0 1 0 2 1 +pinseq=79 +T 3150 1200 9 8 1 1 0 6 1 +pinlabel=RXBP +T 3150 1200 5 8 0 1 0 8 1 +pintype=in +} +P 3500 800 3200 800 1 0 0 +{ +T 3300 850 5 8 1 1 0 0 1 +pinnumber=80 +T 3300 750 5 8 0 1 0 2 1 +pinseq=80 +T 3150 800 9 8 1 1 0 6 1 +pinlabel=RXBN +T 3150 800 5 8 0 1 0 8 1 +pintype=in +} +B 400 0 2800 4000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1200 3700 9 10 1 0 0 0 1 +DATA PATH +T 1500 3400 9 10 1 0 0 0 1 +2 OF 5
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/SN75LBC784-com.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,89 @@ +P 0 1900 300 1900 1 0 0 +{ +T 200 1950 5 8 1 1 0 6 1 +pinnumber=3 +T 200 1850 5 8 0 1 0 8 1 +pinseq=3 +T 350 1900 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 1900 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 1500 300 1500 1 0 0 +{ +T 200 1550 5 8 1 1 0 6 1 +pinnumber=6 +T 200 1450 5 8 0 1 0 8 1 +pinseq=6 +T 350 1500 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 1500 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 1100 300 1100 1 0 0 +{ +T 200 1150 5 8 1 1 0 6 1 +pinnumber=25 +T 200 1050 5 8 0 1 0 8 1 +pinseq=25 +T 350 1100 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 1100 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 700 300 700 1 0 0 +{ +T 200 750 5 8 1 1 0 6 1 +pinnumber=28 +T 200 650 5 8 0 1 0 8 1 +pinseq=28 +T 350 700 9 8 1 1 0 0 1 +pinlabel=BIAS +T 350 700 5 8 0 1 0 2 1 +pintype=pwr +} +P 3400 700 3100 700 1 0 0 +{ +T 3200 750 5 8 1 1 0 0 1 +pinnumber=22 +T 3200 650 5 8 0 1 0 2 1 +pinseq=22 +T 3050 700 9 8 1 1 0 6 1 +pinname=Rws +T 3050 700 5 8 0 1 0 8 1 +pintype=pas +} +P 1700 2600 1700 2300 1 0 0 +{ +T 1750 2400 5 8 1 1 0 0 1 +pinnumber=21 +T 1750 2400 5 8 0 1 0 2 1 +pinseq=21 +T 1700 2250 9 8 1 1 0 5 1 +pinname=Vdd +T 1700 2100 5 8 0 1 0 5 1 +pintype=pwr +} +P 1000 0 1000 300 1 0 0 +{ +T 1050 100 5 8 1 1 0 0 1 +pinnumber=8 +T 1050 100 5 8 0 1 0 2 1 +pinseq=8 +T 1000 350 9 8 1 1 0 3 1 +pinname=GND +T 1000 500 5 8 0 1 0 3 1 +pintype=pwr +} +P 1700 0 1700 300 1 0 0 +{ +T 1750 100 5 8 1 1 0 0 1 +pinnumber=7 +T 1750 100 5 8 0 1 0 2 1 +pinseq=7 +T 1700 350 9 8 1 1 0 3 1 +pinname=Vss +T 1700 500 5 8 0 1 0 3 1 +pintype=pwr +} +B 300 300 2800 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/SN75LBC784.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,29 @@ +#pin name pin number +Drvr_In:3 1 +Rcvr_Out:3 2 +BIAS1 3 +Drvr_In:4 4 +Rcvr_Out:4 5 +BIAS2 6 +Vss 7 +GND 8 +Rcvr_In_N:4 9 +Drvr_Out:4 10 +Rcvr_In_N:3 11 +Drvr_Out:3 12 +Rcvr_In_P:3 13 +Rcvr_In_P:4 14 +Rcvr_In_P:1 15 +Rcvr_In_P:2 16 +Rcvr_In_N:2 17 +Drvr_Out:2 18 +Rcvr_In_N:1 19 +Drvr_Out:1 20 +Vdd 21 +Rws 22 +Drvr_In:1 23 +Rcvr_Out:1 24 +BIAS3 25 +Drvr_In:2 26 +Rcvr_Out:2 27 +BIAS4 28
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/TRS3386E-com.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,85 @@ +B 300 0 2800 3300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +% left side pins +P 0 2900 300 2900 1 0 0 +{ +attr pinname=C1pos +T 350 2900 9 8 1 1 0 0 1 +pinlabel=C1+ +T 200 2950 5 8 1 1 0 6 1 +pinnumber=1 +} +P 0 2000 300 2000 1 0 0 +{ +attr pinname=C1neg +T 350 2000 9 8 1 1 0 0 1 +pinlabel=C1- +T 200 2050 5 8 1 1 0 6 1 +pinnumber=3 +} +P 0 1600 300 1600 1 0 0 +{ +attr pinname=C2pos +T 350 1600 9 8 1 1 0 0 1 +pinlabel=C2+ +T 200 1650 5 8 1 1 0 6 1 +pinnumber=4 +} +P 0 700 300 700 1 0 0 +{ +attr pinname=C2neg +T 350 700 9 8 1 1 0 0 1 +pinlabel=C2- +T 200 750 5 8 1 1 0 6 1 +pinnumber=5 +} +% right side pins +P 3100 2900 3400 2900 1 0 1 +{ +T 3050 2900 9 8 1 1 0 6 1 +pinname=Vcc +T 3200 2950 5 8 1 1 0 0 1 +pinnumber=19 +} +P 3100 2400 3400 2400 1 0 1 +{ +attr pinname=Vpos +T 3050 2400 9 8 1 1 0 6 1 +pinlabel=V+ +T 3200 2450 5 8 1 1 0 0 1 +pinnumber=2 +} +P 3100 1800 3400 1800 1 0 1 +{ +attr pinname=Vneg +T 3050 1800 9 8 1 1 0 6 1 +pinlabel=V- +T 3200 1850 5 8 1 1 0 0 1 +pinnumber=6 +} +P 3100 1000 3400 1000 1 0 1 +{ +T 3050 1000 9 8 1 1 0 6 1 +pinname=Vl +T 3200 1050 5 8 1 1 0 0 1 +pinnumber=12 +} +P 3100 600 3400 600 1 0 1 +{ +T 3050 600 9 8 1 1 0 6 1 +pinname=PWRDOWN +T 3200 650 5 8 1 1 0 0 1 +pinnumber=20 +} +% overbar +PS { + defaultlinewidth setlinewidth + 3050 724 moveto + (PWRDOWN) stringwidth pop neg 0 rlineto stroke +} +P 3100 200 3400 200 1 0 1 +{ +T 3050 200 9 8 1 1 0 6 1 +pinname=GND +T 3200 250 5 8 1 1 0 0 1 +pinnumber=18 +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/TRS3386E.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,21 @@ +#pin name #pin number +C1pos 1 +Vpos 2 +C1neg 3 +C2pos 4 +C2neg 5 +Vneg 6 +Drvr_In:1 7 +Drvr_In:2 8 +Drvr_In:3 9 +Rcvr_Out:2 10 +Rcvr_Out:1 11 +Vl 12 +Rcvr_In:2 13 +Rcvr_In:1 14 +Drvr_Out:3 15 +Drvr_Out:2 16 +Drvr_Out:1 17 +GND 18 +Vcc 19 +PWRDOWN 20
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/Vio-rail.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 200 0 200 200 1 0 0 +{ +attr forcenet=Vio +} +L 50 200 350 200 3 0 0 0 -1 -1 +T 200 250 9 8 1 0 0 3 1 +Vio
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/agnd-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +P 100 100 100 300 1 0 1 +{ +attr forcenet=GND +} +L 0 100 200 100 3 0 0 0 -1 -1 +L 0 100 100 0 3 0 0 0 -1 -1 +L 200 100 100 0 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/btb100-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,501 @@ +B 300 0 800 20000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 0 19800 300 19800 1 0 0 +{ +T 225 19850 5 8 1 1 0 6 1 +pinnumber=1 +} +P 1100 19800 1400 19800 1 0 1 +{ +T 1175 19850 5 8 1 1 0 0 1 +pinnumber=2 +} +P 0 19400 300 19400 1 0 0 +{ +T 225 19450 5 8 1 1 0 6 1 +pinnumber=3 +} +P 1100 19400 1400 19400 1 0 1 +{ +T 1175 19450 5 8 1 1 0 0 1 +pinnumber=4 +} +P 0 19000 300 19000 1 0 0 +{ +T 225 19050 5 8 1 1 0 6 1 +pinnumber=5 +} +P 1100 19000 1400 19000 1 0 1 +{ +T 1175 19050 5 8 1 1 0 0 1 +pinnumber=6 +} +P 0 18600 300 18600 1 0 0 +{ +T 225 18650 5 8 1 1 0 6 1 +pinnumber=7 +} +P 1100 18600 1400 18600 1 0 1 +{ +T 1175 18650 5 8 1 1 0 0 1 +pinnumber=8 +} +P 0 18200 300 18200 1 0 0 +{ +T 225 18250 5 8 1 1 0 6 1 +pinnumber=9 +} +P 1100 18200 1400 18200 1 0 1 +{ +T 1175 18250 5 8 1 1 0 0 1 +pinnumber=10 +} +P 0 17800 300 17800 1 0 0 +{ +T 225 17850 5 8 1 1 0 6 1 +pinnumber=11 +} +P 1100 17800 1400 17800 1 0 1 +{ +T 1175 17850 5 8 1 1 0 0 1 +pinnumber=12 +} +P 0 17400 300 17400 1 0 0 +{ +T 225 17450 5 8 1 1 0 6 1 +pinnumber=13 +} +P 1100 17400 1400 17400 1 0 1 +{ +T 1175 17450 5 8 1 1 0 0 1 +pinnumber=14 +} +P 0 17000 300 17000 1 0 0 +{ +T 225 17050 5 8 1 1 0 6 1 +pinnumber=15 +} +P 1100 17000 1400 17000 1 0 1 +{ +T 1175 17050 5 8 1 1 0 0 1 +pinnumber=16 +} +P 0 16600 300 16600 1 0 0 +{ +T 225 16650 5 8 1 1 0 6 1 +pinnumber=17 +} +P 1100 16600 1400 16600 1 0 1 +{ +T 1175 16650 5 8 1 1 0 0 1 +pinnumber=18 +} +P 0 16200 300 16200 1 0 0 +{ +T 225 16250 5 8 1 1 0 6 1 +pinnumber=19 +} +P 1100 16200 1400 16200 1 0 1 +{ +T 1175 16250 5 8 1 1 0 0 1 +pinnumber=20 +} +P 0 15800 300 15800 1 0 0 +{ +T 225 15850 5 8 1 1 0 6 1 +pinnumber=21 +} +P 1100 15800 1400 15800 1 0 1 +{ +T 1175 15850 5 8 1 1 0 0 1 +pinnumber=22 +} +P 0 15400 300 15400 1 0 0 +{ +T 225 15450 5 8 1 1 0 6 1 +pinnumber=23 +} +P 1100 15400 1400 15400 1 0 1 +{ +T 1175 15450 5 8 1 1 0 0 1 +pinnumber=24 +} +P 0 15000 300 15000 1 0 0 +{ +T 225 15050 5 8 1 1 0 6 1 +pinnumber=25 +} +P 1100 15000 1400 15000 1 0 1 +{ +T 1175 15050 5 8 1 1 0 0 1 +pinnumber=26 +} +P 0 14600 300 14600 1 0 0 +{ +T 225 14650 5 8 1 1 0 6 1 +pinnumber=27 +} +P 1100 14600 1400 14600 1 0 1 +{ +T 1175 14650 5 8 1 1 0 0 1 +pinnumber=28 +} +P 0 14200 300 14200 1 0 0 +{ +T 225 14250 5 8 1 1 0 6 1 +pinnumber=29 +} +P 1100 14200 1400 14200 1 0 1 +{ +T 1175 14250 5 8 1 1 0 0 1 +pinnumber=30 +} +P 0 13800 300 13800 1 0 0 +{ +T 225 13850 5 8 1 1 0 6 1 +pinnumber=31 +} +P 1100 13800 1400 13800 1 0 1 +{ +T 1175 13850 5 8 1 1 0 0 1 +pinnumber=32 +} +P 0 13400 300 13400 1 0 0 +{ +T 225 13450 5 8 1 1 0 6 1 +pinnumber=33 +} +P 1100 13400 1400 13400 1 0 1 +{ +T 1175 13450 5 8 1 1 0 0 1 +pinnumber=34 +} +P 0 13000 300 13000 1 0 0 +{ +T 225 13050 5 8 1 1 0 6 1 +pinnumber=35 +} +P 1100 13000 1400 13000 1 0 1 +{ +T 1175 13050 5 8 1 1 0 0 1 +pinnumber=36 +} +P 0 12600 300 12600 1 0 0 +{ +T 225 12650 5 8 1 1 0 6 1 +pinnumber=37 +} +P 1100 12600 1400 12600 1 0 1 +{ +T 1175 12650 5 8 1 1 0 0 1 +pinnumber=38 +} +P 0 12200 300 12200 1 0 0 +{ +T 225 12250 5 8 1 1 0 6 1 +pinnumber=39 +} +P 1100 12200 1400 12200 1 0 1 +{ +T 1175 12250 5 8 1 1 0 0 1 +pinnumber=40 +} +P 0 11800 300 11800 1 0 0 +{ +T 225 11850 5 8 1 1 0 6 1 +pinnumber=41 +} +P 1100 11800 1400 11800 1 0 1 +{ +T 1175 11850 5 8 1 1 0 0 1 +pinnumber=42 +} +P 0 11400 300 11400 1 0 0 +{ +T 225 11450 5 8 1 1 0 6 1 +pinnumber=43 +} +P 1100 11400 1400 11400 1 0 1 +{ +T 1175 11450 5 8 1 1 0 0 1 +pinnumber=44 +} +P 0 11000 300 11000 1 0 0 +{ +T 225 11050 5 8 1 1 0 6 1 +pinnumber=45 +} +P 1100 11000 1400 11000 1 0 1 +{ +T 1175 11050 5 8 1 1 0 0 1 +pinnumber=46 +} +P 0 10600 300 10600 1 0 0 +{ +T 225 10650 5 8 1 1 0 6 1 +pinnumber=47 +} +P 1100 10600 1400 10600 1 0 1 +{ +T 1175 10650 5 8 1 1 0 0 1 +pinnumber=48 +} +P 0 10200 300 10200 1 0 0 +{ +T 225 10250 5 8 1 1 0 6 1 +pinnumber=49 +} +P 1100 10200 1400 10200 1 0 1 +{ +T 1175 10250 5 8 1 1 0 0 1 +pinnumber=50 +} +P 0 9800 300 9800 1 0 0 +{ +T 225 9850 5 8 1 1 0 6 1 +pinnumber=51 +} +P 1100 9800 1400 9800 1 0 1 +{ +T 1175 9850 5 8 1 1 0 0 1 +pinnumber=52 +} +P 0 9400 300 9400 1 0 0 +{ +T 225 9450 5 8 1 1 0 6 1 +pinnumber=53 +} +P 1100 9400 1400 9400 1 0 1 +{ +T 1175 9450 5 8 1 1 0 0 1 +pinnumber=54 +} +P 0 9000 300 9000 1 0 0 +{ +T 225 9050 5 8 1 1 0 6 1 +pinnumber=55 +} +P 1100 9000 1400 9000 1 0 1 +{ +T 1175 9050 5 8 1 1 0 0 1 +pinnumber=56 +} +P 0 8600 300 8600 1 0 0 +{ +T 225 8650 5 8 1 1 0 6 1 +pinnumber=57 +} +P 1100 8600 1400 8600 1 0 1 +{ +T 1175 8650 5 8 1 1 0 0 1 +pinnumber=58 +} +P 0 8200 300 8200 1 0 0 +{ +T 225 8250 5 8 1 1 0 6 1 +pinnumber=59 +} +P 1100 8200 1400 8200 1 0 1 +{ +T 1175 8250 5 8 1 1 0 0 1 +pinnumber=60 +} +P 0 7800 300 7800 1 0 0 +{ +T 225 7850 5 8 1 1 0 6 1 +pinnumber=61 +} +P 1100 7800 1400 7800 1 0 1 +{ +T 1175 7850 5 8 1 1 0 0 1 +pinnumber=62 +} +P 0 7400 300 7400 1 0 0 +{ +T 225 7450 5 8 1 1 0 6 1 +pinnumber=63 +} +P 1100 7400 1400 7400 1 0 1 +{ +T 1175 7450 5 8 1 1 0 0 1 +pinnumber=64 +} +P 0 7000 300 7000 1 0 0 +{ +T 225 7050 5 8 1 1 0 6 1 +pinnumber=65 +} +P 1100 7000 1400 7000 1 0 1 +{ +T 1175 7050 5 8 1 1 0 0 1 +pinnumber=66 +} +P 0 6600 300 6600 1 0 0 +{ +T 225 6650 5 8 1 1 0 6 1 +pinnumber=67 +} +P 1100 6600 1400 6600 1 0 1 +{ +T 1175 6650 5 8 1 1 0 0 1 +pinnumber=68 +} +P 0 6200 300 6200 1 0 0 +{ +T 225 6250 5 8 1 1 0 6 1 +pinnumber=69 +} +P 1100 6200 1400 6200 1 0 1 +{ +T 1175 6250 5 8 1 1 0 0 1 +pinnumber=70 +} +P 0 5800 300 5800 1 0 0 +{ +T 225 5850 5 8 1 1 0 6 1 +pinnumber=71 +} +P 1100 5800 1400 5800 1 0 1 +{ +T 1175 5850 5 8 1 1 0 0 1 +pinnumber=72 +} +P 0 5400 300 5400 1 0 0 +{ +T 225 5450 5 8 1 1 0 6 1 +pinnumber=73 +} +P 1100 5400 1400 5400 1 0 1 +{ +T 1175 5450 5 8 1 1 0 0 1 +pinnumber=74 +} +P 0 5000 300 5000 1 0 0 +{ +T 225 5050 5 8 1 1 0 6 1 +pinnumber=75 +} +P 1100 5000 1400 5000 1 0 1 +{ +T 1175 5050 5 8 1 1 0 0 1 +pinnumber=76 +} +P 0 4600 300 4600 1 0 0 +{ +T 225 4650 5 8 1 1 0 6 1 +pinnumber=77 +} +P 1100 4600 1400 4600 1 0 1 +{ +T 1175 4650 5 8 1 1 0 0 1 +pinnumber=78 +} +P 0 4200 300 4200 1 0 0 +{ +T 225 4250 5 8 1 1 0 6 1 +pinnumber=79 +} +P 1100 4200 1400 4200 1 0 1 +{ +T 1175 4250 5 8 1 1 0 0 1 +pinnumber=80 +} +P 0 3800 300 3800 1 0 0 +{ +T 225 3850 5 8 1 1 0 6 1 +pinnumber=81 +} +P 1100 3800 1400 3800 1 0 1 +{ +T 1175 3850 5 8 1 1 0 0 1 +pinnumber=82 +} +P 0 3400 300 3400 1 0 0 +{ +T 225 3450 5 8 1 1 0 6 1 +pinnumber=83 +} +P 1100 3400 1400 3400 1 0 1 +{ +T 1175 3450 5 8 1 1 0 0 1 +pinnumber=84 +} +P 0 3000 300 3000 1 0 0 +{ +T 225 3050 5 8 1 1 0 6 1 +pinnumber=85 +} +P 1100 3000 1400 3000 1 0 1 +{ +T 1175 3050 5 8 1 1 0 0 1 +pinnumber=86 +} +P 0 2600 300 2600 1 0 0 +{ +T 225 2650 5 8 1 1 0 6 1 +pinnumber=87 +} +P 1100 2600 1400 2600 1 0 1 +{ +T 1175 2650 5 8 1 1 0 0 1 +pinnumber=88 +} +P 0 2200 300 2200 1 0 0 +{ +T 225 2250 5 8 1 1 0 6 1 +pinnumber=89 +} +P 1100 2200 1400 2200 1 0 1 +{ +T 1175 2250 5 8 1 1 0 0 1 +pinnumber=90 +} +P 0 1800 300 1800 1 0 0 +{ +T 225 1850 5 8 1 1 0 6 1 +pinnumber=91 +} +P 1100 1800 1400 1800 1 0 1 +{ +T 1175 1850 5 8 1 1 0 0 1 +pinnumber=92 +} +P 0 1400 300 1400 1 0 0 +{ +T 225 1450 5 8 1 1 0 6 1 +pinnumber=93 +} +P 1100 1400 1400 1400 1 0 1 +{ +T 1175 1450 5 8 1 1 0 0 1 +pinnumber=94 +} +P 0 1000 300 1000 1 0 0 +{ +T 225 1050 5 8 1 1 0 6 1 +pinnumber=95 +} +P 1100 1000 1400 1000 1 0 1 +{ +T 1175 1050 5 8 1 1 0 0 1 +pinnumber=96 +} +P 0 600 300 600 1 0 0 +{ +T 225 650 5 8 1 1 0 6 1 +pinnumber=97 +} +P 1100 600 1400 600 1 0 1 +{ +T 1175 650 5 8 1 1 0 0 1 +pinnumber=98 +} +P 0 200 300 200 1 0 0 +{ +T 225 250 5 8 1 1 0 6 1 +pinnumber=99 +} +P 1100 200 1400 200 1 0 1 +{ +T 1175 250 5 8 1 1 0 0 1 +pinnumber=100 +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/busripper-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +v 20031231 1 +T 0 400 5 8 0 0 0 0 1 +device=none +P 0 0 100 100 1 0 0 +{ +T 0 500 5 8 0 0 0 0 1 +pinseq=1 +T 0 600 5 8 0 0 0 0 1 +pinnumber=1 +T 0 700 5 8 0 0 0 0 1 +pintype=pas +T 0 800 5 8 0 0 0 0 1 +pinlabel=netside +} +T 0 300 5 8 0 0 0 0 1 +graphical=1 +L 200 200 100 100 10 30 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/busripper-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,18 @@ +v 20031231 1 +T 0 400 5 8 0 0 0 0 1 +device=none +P 0 0 0 100 1 0 0 +{ +T 0 500 5 8 0 0 0 0 1 +pinseq=1 +T 0 600 5 8 0 0 0 0 1 +pinnumber=1 +T 0 700 5 8 0 0 0 0 1 +pintype=pas +T 0 800 5 8 0 0 0 0 1 +pinlabel=netside +} +T 0 300 5 8 0 0 0 0 1 +graphical=1 +L 0 100 100 200 3 0 0 0 -1 -1 +L 0 100 -100 200 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/canosc-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,24 @@ +B 0 0 900 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1200 100 900 100 1 0 0 +{ +T 950 150 5 10 1 1 0 0 1 +pinnumber=%d +T 575 50 5 8 1 1 0 0 1 +pinname=OUT +} +P 100 900 100 600 1 0 0 +{ +T 200 700 5 10 1 1 0 0 1 +pinnumber=%d +T 50 450 5 8 1 1 0 0 1 +pinname=Vcc +} +% Blemish: GND pin not represented graphically in this symbol +% Be sure to use PinToNet to connect it +L 75 175 225 175 3 0 0 0 -1 -1 +L 225 175 225 400 3 0 0 0 -1 -1 +L 225 400 400 400 3 0 0 0 -1 -1 +L 400 400 400 175 3 0 0 0 -1 -1 +L 400 175 575 175 3 0 0 0 -1 -1 +L 575 175 575 400 3 0 0 0 -1 -1 +L 575 400 725 400 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/canosc.std.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,6 @@ +# Standard pinout for can oscillators + +#pin name pin number +GND 2 +OUT 3 +Vcc 4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/capacitor-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,37 @@ +v 20050820 1 +P 0 200 200 200 1 0 0 +{ +T 150 250 5 8 0 1 0 6 1 +pinnumber=1 +T 150 150 5 8 0 1 0 8 1 +pinseq=1 +T 200 200 9 8 0 1 0 0 1 +pinlabel=1 +T 200 200 5 8 0 1 0 2 1 +pintype=pas +} +P 900 200 700 200 1 0 0 +{ +T 750 250 5 8 0 1 0 0 1 +pinnumber=2 +T 750 150 5 8 0 1 0 2 1 +pinseq=2 +T 700 200 9 8 0 1 0 6 1 +pinlabel=2 +T 700 200 5 8 0 1 0 8 1 +pintype=pas +} +L 400 400 400 0 3 0 0 0 -1 -1 +L 500 400 500 0 3 0 0 0 -1 -1 +L 700 200 500 200 3 0 0 0 -1 -1 +L 400 200 200 200 3 0 0 0 -1 -1 +T 200 700 5 10 0 0 0 0 1 +device=CAPACITOR +T 200 500 8 10 1 1 0 0 1 +refdes=C? +T 200 1300 5 10 0 0 0 0 1 +description=capacitor +T 200 1100 5 10 0 0 0 0 1 +numslots=0 +T 200 900 5 10 0 0 0 0 1 +symversion=0.1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/capacitor-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,39 @@ +v 20050820 1 +P 0 200 200 200 1 0 0 +{ +T 150 250 5 8 1 1 0 6 1 +pinnumber=1 +T 200 150 5 8 0 1 0 8 1 +pinseq=1 +T 250 200 9 8 0 1 0 0 1 +pinlabel=+ +T 250 200 5 8 0 1 0 2 1 +pintype=pas +} +P 900 200 700 200 1 0 0 +{ +T 750 250 5 8 1 1 0 0 1 +pinnumber=2 +T 700 150 5 8 0 1 0 2 1 +pinseq=2 +T 650 200 9 8 0 1 0 6 1 +pinlabel=- +T 650 200 5 8 0 1 0 8 1 +pintype=pas +} +L 400 400 400 0 3 0 0 0 -1 -1 +L 700 200 500 200 3 0 0 0 -1 -1 +L 400 200 200 200 3 0 0 0 -1 -1 +T 200 700 5 10 0 0 0 0 1 +device=POLARIZED_CAPACITOR +A 1200 200 700 165 30 3 0 0 0 -1 -1 +L 289 400 289 300 3 0 0 0 -1 -1 +L 340 349 240 349 3 0 0 0 -1 -1 +T 200 500 8 10 1 1 0 0 1 +refdes=C? +T 200 1300 5 10 0 0 0 0 1 +description=polarized capacitor +T 200 1100 5 10 0 0 0 0 1 +numslots=0 +T 200 900 5 10 0 0 0 0 1 +symversion=0.1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/coil-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,36 @@ +v 20050820 1 +P 200 0 0 0 1 0 1 +{ +T 150 50 5 8 0 1 0 6 1 +pinnumber=1 +T 150 -50 5 8 0 1 0 8 1 +pinseq=1 +T 250 0 9 8 0 1 0 0 1 +pinlabel=1 +T 250 0 5 8 0 1 0 2 1 +pintype=pas +} +P 800 0 1000 0 1 0 1 +{ +T 850 50 5 8 0 1 0 0 1 +pinnumber=2 +T 850 -50 5 8 0 1 0 2 1 +pinseq=2 +T 750 0 9 8 0 1 0 6 1 +pinlabel=2 +T 750 0 5 8 0 1 0 8 1 +pintype=pas +} +A 300 0 100 0 180 3 0 0 0 -1 -1 +A 500 0 100 0 180 3 0 0 0 -1 -1 +A 700 0 100 0 180 3 0 0 0 -1 -1 +T 200 400 5 10 0 0 0 0 1 +device=COIL +T 200 200 8 10 1 1 0 0 1 +refdes=L? +T 200 1000 5 10 0 0 0 0 1 +description=incuctor +T 200 800 5 10 0 0 0 0 1 +numslots=0 +T 200 600 5 10 0 0 0 0 1 +symversion=0.1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/connector20-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,250 @@ +v 20031231 1 +T 100 6200 8 10 1 1 0 0 1 +refdes=J? +T 700 6500 8 10 0 0 0 0 1 +device=CONNECTOR_20 +T 700 6300 8 10 0 0 0 0 1 +pins=20 +T 700 6100 8 10 0 0 0 0 1 +class=IO +P 1400 5900 1700 5900 1 0 1 +{ +T 300 5900 5 8 1 1 0 0 1 +pinnumber=1 +T 300 5900 5 8 0 0 0 0 1 +pinseq=1 +T 300 5900 5 8 0 1 0 0 1 +pinlabel=1 +T 300 5900 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 5600 1700 5600 1 0 1 +{ +T 300 5600 5 8 1 1 0 0 1 +pinnumber=2 +T 300 5600 5 8 0 0 0 0 1 +pinseq=2 +T 300 5600 5 8 0 1 0 0 1 +pinlabel=2 +T 300 5600 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 5300 1700 5300 1 0 1 +{ +T 300 5300 5 8 1 1 0 0 1 +pinnumber=3 +T 300 5300 5 8 0 0 0 0 1 +pinseq=3 +T 300 5300 5 8 0 1 0 0 1 +pinlabel=3 +T 300 5300 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 5000 1700 5000 1 0 1 +{ +T 300 5000 5 8 1 1 0 0 1 +pinnumber=4 +T 300 5000 5 8 0 0 0 0 1 +pinseq=4 +T 300 5000 5 8 0 1 0 0 1 +pinlabel=4 +T 300 5000 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 4700 1700 4700 1 0 1 +{ +T 300 4700 5 8 1 1 0 0 1 +pinnumber=5 +T 300 4700 5 8 0 0 0 0 1 +pinseq=5 +T 300 4700 5 8 0 1 0 0 1 +pinlabel=5 +T 300 4700 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 4400 1700 4400 1 0 1 +{ +T 300 4400 5 8 1 1 0 0 1 +pinnumber=6 +T 300 4400 5 8 0 0 0 0 1 +pinseq=6 +T 300 4400 5 8 0 1 0 0 1 +pinlabel=6 +T 300 4400 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 4100 1700 4100 1 0 1 +{ +T 300 4100 5 8 1 1 0 0 1 +pinnumber=7 +T 300 4100 5 8 0 0 0 0 1 +pinseq=7 +T 300 4100 5 8 0 1 0 0 1 +pinlabel=7 +T 300 4100 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 3800 1700 3800 1 0 1 +{ +T 300 3800 5 8 1 1 0 0 1 +pinnumber=8 +T 300 3800 5 8 0 0 0 0 1 +pinseq=8 +T 300 3800 5 8 0 1 0 0 1 +pinlabel=8 +T 300 3800 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 3500 1700 3500 1 0 1 +{ +T 300 3500 5 8 1 1 0 0 1 +pinnumber=9 +T 300 3500 5 8 0 0 0 0 1 +pinseq=9 +T 300 3500 5 8 0 1 0 0 1 +pinlabel=9 +T 300 3500 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 3200 1700 3200 1 0 1 +{ +T 300 3200 5 8 1 1 0 0 1 +pinnumber=10 +T 300 3200 5 8 0 0 0 0 1 +pinseq=10 +T 300 3200 5 8 0 1 0 0 1 +pinlabel=10 +T 300 3200 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 2900 1700 2900 1 0 1 +{ +T 300 2900 5 8 1 1 0 0 1 +pinnumber=11 +T 300 2900 5 8 0 0 0 0 1 +pinseq=11 +T 300 2900 5 8 0 1 0 0 1 +pinlabel=11 +T 300 2900 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 2600 1700 2600 1 0 1 +{ +T 300 2600 5 8 1 1 0 0 1 +pinnumber=12 +T 300 2600 5 8 0 0 0 0 1 +pinseq=12 +T 300 2600 5 8 0 1 0 0 1 +pinlabel=12 +T 300 2600 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 2300 1700 2300 1 0 1 +{ +T 300 2300 5 8 1 1 0 0 1 +pinnumber=13 +T 300 2300 5 8 0 0 0 0 1 +pinseq=13 +T 300 2300 5 8 0 1 0 0 1 +pinlabel=13 +T 300 2300 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 2000 1700 2000 1 0 1 +{ +T 300 2000 5 8 1 1 0 0 1 +pinnumber=14 +T 300 2000 5 8 0 0 0 0 1 +pinseq=14 +T 300 2000 5 8 0 1 0 0 1 +pinlabel=14 +T 300 2000 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 1700 1700 1700 1 0 1 +{ +T 300 1700 5 8 1 1 0 0 1 +pinnumber=15 +T 300 1700 5 8 0 0 0 0 1 +pinseq=15 +T 300 1700 5 8 0 1 0 0 1 +pinlabel=15 +T 300 1700 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 1400 1700 1400 1 0 1 +{ +T 300 1400 5 8 1 1 0 0 1 +pinnumber=16 +T 300 1400 5 8 0 0 0 0 1 +pinseq=16 +T 300 1400 5 8 0 1 0 0 1 +pinlabel=16 +T 300 1400 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 1100 1700 1100 1 0 1 +{ +T 300 1100 5 8 1 1 0 0 1 +pinnumber=17 +T 300 1100 5 8 0 0 0 0 1 +pinseq=17 +T 300 1100 5 8 0 1 0 0 1 +pinlabel=17 +T 300 1100 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 800 1700 800 1 0 1 +{ +T 300 800 5 8 1 1 0 0 1 +pinnumber=18 +T 300 800 5 8 0 0 0 0 1 +pinseq=18 +T 300 800 5 8 0 1 0 0 1 +pinlabel=18 +T 300 800 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 500 1700 500 1 0 1 +{ +T 300 500 5 8 1 1 0 0 1 +pinnumber=19 +T 300 500 5 8 0 0 0 0 1 +pinseq=19 +T 300 500 5 8 0 1 0 0 1 +pinlabel=19 +T 300 500 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 200 1700 200 1 0 1 +{ +T 300 200 5 8 1 1 0 0 1 +pinnumber=20 +T 300 200 5 8 0 0 0 0 1 +pinseq=20 +T 300 200 5 8 0 1 0 0 1 +pinlabel=20 +T 300 200 5 8 0 1 0 0 1 +pintype=pas +} +B 0 0 500 6100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 1400 5900 500 5900 3 0 0 0 -1 -1 +L 1400 5600 500 5600 3 0 0 0 -1 -1 +L 1400 5300 500 5300 3 0 0 0 -1 -1 +L 1400 5000 500 5000 3 0 0 0 -1 -1 +L 1400 4700 500 4700 3 0 0 0 -1 -1 +L 1400 4400 500 4400 3 0 0 0 -1 -1 +L 1400 4100 500 4100 3 0 0 0 -1 -1 +L 1400 3800 500 3800 3 0 0 0 -1 -1 +L 1400 3500 500 3500 3 0 0 0 -1 -1 +L 1400 3200 500 3200 3 0 0 0 -1 -1 +L 1400 2900 500 2900 3 0 0 0 -1 -1 +L 1400 2600 500 2600 3 0 0 0 -1 -1 +L 1400 2300 500 2300 3 0 0 0 -1 -1 +L 1400 2000 500 2000 3 0 0 0 -1 -1 +L 1400 1700 500 1700 3 0 0 0 -1 -1 +L 1400 1400 500 1400 3 0 0 0 -1 -1 +L 1400 1100 500 1100 3 0 0 0 -1 -1 +L 1400 800 500 800 3 0 0 0 -1 -1 +L 1400 500 500 500 3 0 0 0 -1 -1 +L 1400 200 500 200 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/connector20-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,254 @@ +v 20041228 1 +T 800 8600 8 10 1 1 0 6 1 +refdes=CONN? +T 400 8550 5 10 0 0 0 0 1 +device=CONNECTOR_20 +T 400 8750 5 10 0 0 0 0 1 +footprint=SIP20N +T 400 8950 5 10 0 0 0 0 1 +author=Leon Kos +T 400 9150 5 10 0 0 0 0 1 +description=generic connector +T 400 9350 5 10 0 0 0 0 1 +numslots=0 +P 100 8100 300 8100 1 0 0 +{ +T 300 8150 5 8 0 1 0 6 1 +pinnumber=1 +T 300 8050 5 8 0 1 0 8 1 +pinseq=1 +T 450 8100 9 8 1 1 0 0 1 +pinlabel=1 +T 450 8100 5 8 0 1 0 2 1 +pintype=pas +} +V 350 8100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 7700 300 7700 1 0 0 +{ +T 300 7750 5 8 0 1 0 6 1 +pinnumber=2 +T 300 7650 5 8 0 1 0 8 1 +pinseq=2 +T 450 7700 9 8 1 1 0 0 1 +pinlabel=2 +T 450 7700 5 8 0 1 0 2 1 +pintype=pas +} +V 350 7700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 7300 300 7300 1 0 0 +{ +T 300 7350 5 8 0 1 0 6 1 +pinnumber=3 +T 300 7250 5 8 0 1 0 8 1 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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/connector4-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,58 @@ +v 20031231 1 +P 1400 500 1700 500 1 0 1 +{ +T 250 450 5 8 1 1 0 0 1 +pinnumber=3 +T 250 450 5 8 0 0 0 0 1 +pinseq=3 +T 250 450 5 8 0 1 0 0 1 +pinlabel=3 +T 250 450 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 800 1700 800 1 0 1 +{ +T 250 750 5 8 1 1 0 0 1 +pinnumber=2 +T 250 750 5 8 0 0 0 0 1 +pinseq=2 +T 250 750 5 8 0 1 0 0 1 +pinlabel=2 +T 250 750 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 200 1700 200 1 0 1 +{ +T 250 150 5 8 1 1 0 0 1 +pinnumber=4 +T 250 150 5 8 0 0 0 0 1 +pinseq=4 +T 250 150 5 8 0 1 0 0 1 +pinlabel=4 +T 250 150 5 8 0 1 0 0 1 +pintype=pas +} +L 1400 800 500 800 3 0 0 0 -1 -1 +L 1400 500 500 500 3 0 0 0 -1 -1 +L 1400 200 500 200 3 0 0 0 -1 -1 +T 1800 900 5 10 0 0 0 0 1 +device=CONNECTOR_4 +P 1400 1100 1700 1100 1 0 1 +{ +T 250 1050 5 8 1 1 0 0 1 +pinnumber=1 +T 250 1050 5 8 0 0 0 0 1 +pinseq=1 +T 250 1050 5 8 0 1 0 0 1 +pinlabel=1 +T 250 1050 5 8 0 1 0 0 1 +pintype=pas +} +L 1400 1100 500 1100 3 0 0 0 -1 -1 +B 0 0 500 1300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 0 1400 8 10 1 1 0 0 1 +refdes=CONN? +T 1800 1100 5 10 0 0 0 0 1 +class=IO +T 1800 1300 5 10 0 0 0 0 1 +pins=4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/connector6-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,78 @@ +v 20031231 1 +P 1400 1400 1700 1400 1 0 1 +{ +T 250 1350 5 8 1 1 0 0 1 +pinnumber=2 +T 250 1350 5 8 0 0 0 0 1 +pinseq=2 +T 250 1350 5 8 0 1 0 0 1 +pinlabel=2 +T 250 1350 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 800 1700 800 1 0 1 +{ +T 250 750 5 8 1 1 0 0 1 +pinnumber=4 +T 250 750 5 8 0 0 0 0 1 +pinseq=4 +T 250 750 5 8 0 1 0 0 1 +pinlabel=4 +T 250 750 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 200 1700 200 1 0 1 +{ +T 250 150 5 8 1 1 0 0 1 +pinnumber=6 +T 250 150 5 8 0 0 0 0 1 +pinseq=6 +T 250 150 5 8 0 1 0 0 1 +pinlabel=6 +T 250 150 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 1700 1700 1700 1 0 1 +{ +T 250 1650 5 8 1 1 0 0 1 +pinnumber=1 +T 250 1650 5 8 0 0 0 0 1 +pinseq=1 +T 250 1650 5 8 0 1 0 0 1 +pinlabel=1 +T 250 1650 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 1100 1700 1100 1 0 1 +{ +T 250 1050 5 8 1 1 0 0 1 +pinnumber=3 +T 250 1050 5 8 0 0 0 0 1 +pinseq=3 +T 250 1050 5 8 0 1 0 0 1 +pinlabel=3 +T 250 1050 5 8 0 1 0 0 1 +pintype=pas +} +P 1400 500 1700 500 1 0 1 +{ +T 250 450 5 8 1 1 0 0 1 +pinnumber=5 +T 250 450 5 8 0 0 0 0 1 +pinseq=5 +T 250 450 5 8 0 1 0 0 1 +pinlabel=5 +T 250 450 5 8 0 1 0 0 1 +pintype=pas +} +L 1400 1700 500 1700 3 0 0 0 -1 -1 +L 1400 1400 500 1400 3 0 0 0 -1 -1 +L 1400 1100 500 1100 3 0 0 0 -1 -1 +L 1400 800 500 800 3 0 0 0 -1 -1 +L 1400 500 500 500 3 0 0 0 -1 -1 +L 1400 200 500 200 3 0 0 0 -1 -1 +B 0 0 500 1900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1800 1800 5 10 0 0 0 0 1 +device=CONNECTOR_6 +T 100 2000 8 10 1 1 0 0 1 +refdes=CONN?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/crystal-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,36 @@ +v 20050820 1 +P 0 100 200 100 1 0 0 +{ +T 150 150 5 8 0 1 0 6 1 +pinnumber=1 +T 150 50 5 8 0 1 0 8 1 +pinseq=1 +T 250 100 9 8 0 1 0 0 1 +pinlabel=1 +T 250 100 5 8 0 1 0 2 1 +pintype=pas +} +P 500 100 700 100 1 0 1 +{ +T 550 150 5 8 0 1 0 0 1 +pinnumber=2 +T 550 50 5 8 0 1 0 2 1 +pinseq=2 +T 450 100 9 8 0 1 0 6 1 +pinlabel=2 +T 450 100 5 8 0 1 0 8 1 +pintype=pas +} +B 250 0 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 200 500 5 10 0 0 0 0 1 +device=CRYSTAL +L 200 240 200 -40 3 0 0 0 -1 -1 +L 500 240 500 -40 3 0 0 0 -1 -1 +T 200 300 8 10 1 1 0 0 1 +refdes=U? +T 200 1100 5 10 0 0 0 0 1 +description=crystal +T 200 900 5 10 0 0 0 0 1 +numslots=0 +T 200 700 5 10 0 0 0 0 1 +symversion=0.1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/diffdrvr-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,22 @@ +L 400 1000 400 200 3 0 0 0 -1 -1 +L 400 200 1000 600 3 0 0 0 -1 -1 +L 1000 600 400 1000 3 0 0 0 -1 -1 +V 750 400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 600 400 600 1 0 0 +{ +T 200 650 5 8 1 1 0 0 1 +pinnumber=%d +attr pinname=Drvr_In +} +P 1200 800 700 800 1 0 0 +{ +T 1050 850 5 8 1 1 0 0 1 +pinnumber=%d +attr pinname=Drvr_Out_P +} +P 1200 400 800 400 1 0 0 +{ +T 1050 450 5 8 1 1 0 0 1 +pinnumber=%d +attr pinname=Drvr_Out_N +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/diffrcvr-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,27 @@ +L 200 1000 200 200 3 0 0 0 -1 -1 +L 200 1000 800 600 3 0 0 0 -1 -1 +L 800 600 200 200 3 0 0 0 -1 -1 +L 300 450 300 350 3 0 0 0 -1 -1 +L 250 400 350 400 3 0 0 0 -1 -1 +L 250 800 350 800 3 0 0 0 -1 -1 +P 0 400 200 400 1 0 0 +{ +T 0 450 5 10 1 1 0 0 1 +pinnumber=%d +T 0 450 5 10 0 0 0 0 1 +pinname=Rcvr_In_P +} +P 0 800 200 800 1 0 0 +{ +T 0 850 5 10 1 1 0 0 1 +pinnumber=%d +T 0 850 5 10 0 0 0 0 1 +pinname=Rcvr_In_N +} +P 800 600 1000 600 1 0 1 +{ +T 800 650 5 10 1 1 0 0 1 +pinnumber=%d +T 800 650 5 10 0 0 0 0 1 +pinname=Rcvr_Out +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/diffrcvr-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,27 @@ +L 200 1000 200 200 3 0 0 0 -1 -1 +L 200 1000 800 600 3 0 0 0 -1 -1 +L 800 600 200 200 3 0 0 0 -1 -1 +L 250 400 350 400 3 0 0 0 -1 -1 +L 300 850 300 750 3 0 0 0 -1 -1 +L 250 800 350 800 3 0 0 0 -1 -1 +P 0 400 200 400 1 0 0 +{ +T 0 450 5 10 1 1 0 0 1 +pinnumber=%d +T 0 450 5 10 0 0 0 0 1 +pinname=Rcvr_In_N +} +P 0 800 200 800 1 0 0 +{ +T 0 850 5 10 1 1 0 0 1 +pinnumber=%d +T 0 850 5 10 0 0 0 0 1 +pinname=Rcvr_In_P +} +P 800 600 1000 600 1 0 1 +{ +T 800 650 5 10 1 1 0 0 1 +pinnumber=%d +T 800 650 5 10 0 0 0 0 1 +pinname=Rcvr_Out +}
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+pinnumber=83 +} +P 1100 3400 1400 3400 1 0 1 +{ +T 1250 3450 5 8 1 1 0 0 1 +pinnumber=84 +} +L 300 3200 1100 3200 3 0 0 0 -1 -1 +P 0 3000 300 3000 1 0 0 +{ +T 150 3050 5 8 1 1 0 0 1 +pinnumber=85 +} +P 1100 3000 1400 3000 1 0 1 +{ +T 1250 3050 5 8 1 1 0 0 1 +pinnumber=86 +} +L 300 2800 1100 2800 3 0 0 0 -1 -1 +P 0 2600 300 2600 1 0 0 +{ +T 150 2650 5 8 1 1 0 0 1 +pinnumber=87 +} +P 1100 2600 1400 2600 1 0 1 +{ +T 1250 2650 5 8 1 1 0 0 1 +pinnumber=88 +} +L 300 2400 1100 2400 3 0 0 0 -1 -1 +P 0 2200 300 2200 1 0 0 +{ +T 150 2250 5 8 1 1 0 0 1 +pinnumber=89 +} +P 1100 2200 1400 2200 1 0 1 +{ +T 1250 2250 5 8 1 1 0 0 1 +pinnumber=90 +} +L 300 2000 1100 2000 3 0 0 0 -1 -1 +P 0 1800 300 1800 1 0 0 +{ +T 150 1850 5 8 1 1 0 0 1 +pinnumber=91 +} +P 1100 1800 1400 1800 1 0 1 +{ +T 1250 1850 5 8 1 1 0 0 1 +pinnumber=92 +} +L 300 1600 1100 1600 3 0 0 0 -1 -1 +P 0 1400 300 1400 1 0 0 +{ +T 150 1450 5 8 1 1 0 0 1 +pinnumber=93 +} +P 1100 1400 1400 1400 1 0 1 +{ +T 1250 1450 5 8 1 1 0 0 1 +pinnumber=94 +} +L 300 1200 1100 1200 3 0 0 0 -1 -1 +P 0 1000 300 1000 1 0 0 +{ +T 150 1050 5 8 1 1 0 0 1 +pinnumber=95 +} +P 1100 1000 1400 1000 1 0 1 +{ +T 1250 1050 5 8 1 1 0 0 1 +pinnumber=96 +} +L 300 800 1100 800 3 0 0 0 -1 -1 +P 0 600 300 600 1 0 0 +{ +T 150 650 5 8 1 1 0 0 1 +pinnumber=97 +} +P 1100 600 1400 600 1 0 1 +{ +T 1250 650 5 8 1 1 0 0 1 +pinnumber=98 +} +L 300 400 1100 400 3 0 0 0 -1 -1 +P 0 200 300 200 1 0 0 +{ +T 150 250 5 8 1 1 0 0 1 +pinnumber=99 +} +P 1100 200 1400 200 1 0 1 +{ +T 1250 250 5 8 1 1 0 0 1 +pinnumber=100 +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/header2-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,12 @@ +B 0 300 800 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 400 700 400 300 3 0 0 0 -1 -1 +P 200 0 200 300 1 0 0 +{ +T 200 500 5 8 1 1 0 4 1 +pinnumber=1 +} +P 600 0 600 300 1 0 0 +{ +T 600 500 5 8 1 1 0 4 1 +pinnumber=2 +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/interpage_bidir-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,20 @@ +v 20031231 1 +P 0 200 300 200 1 0 0 +{ +T 100 400 5 10 0 0 0 0 1 +pinnumber=1 +T 100 400 5 10 0 0 0 0 1 +pinseq=1 +} +L 300 200 500 0 3 0 0 0 -1 -1 +L 500 0 1100 0 3 0 0 0 -1 -1 +L 1300 200 1100 400 3 0 0 0 -1 -1 +L 1100 400 500 400 3 0 0 0 -1 -1 +T 300 600 5 10 0 0 0 0 1 +device=interpage_bidir +T 300 800 5 10 0 0 0 0 1 +graphical=1 +L 500 400 300 200 3 0 0 0 -1 -1 +L 1100 0 1300 200 3 0 0 0 -1 -1 +T 1500 200 5 10 1 1 0 0 1 +pages=?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/interpage_from-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,19 @@ +v 20031231 1 +P 0 200 300 200 1 0 0 +{ +T 100 400 5 10 0 0 0 0 1 +pinnumber=1 +T 100 400 5 10 0 0 0 0 1 +pinseq=1 +} +L 300 200 500 0 3 0 0 0 -1 -1 +L 500 0 1100 0 3 0 0 0 -1 -1 +L 1100 0 1100 400 3 0 0 0 -1 -1 +L 1100 400 500 400 3 0 0 0 -1 -1 +T 300 600 5 10 0 0 0 0 1 +device=interpage_from +T 300 800 5 10 0 0 0 0 1 +graphical=1 +L 500 400 300 200 3 0 0 0 -1 -1 +T 1300 200 5 10 1 1 0 0 1 +pages=?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/interpage_to-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,19 @@ +v 20031231 1 +P 0 200 300 200 1 0 0 +{ +T 100 400 5 10 0 0 0 0 1 +pinnumber=1 +T 100 400 5 10 0 0 0 0 1 +pinseq=1 +} +L 300 0 900 0 3 0 0 0 -1 -1 +L 900 0 1100 200 3 0 0 0 -1 -1 +L 1100 200 900 400 3 0 0 0 -1 -1 +L 900 400 300 400 3 0 0 0 -1 -1 +T 300 600 5 10 0 0 0 0 1 +device=interpage_to +T 300 800 5 10 0 0 0 0 1 +graphical=1 +L 300 400 300 0 3 0 0 0 -1 -1 +T 1300 200 5 10 1 1 0 0 1 +pages=?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/jumper-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,30 @@ +v 20031231 1 +P 100 1000 100 800 1 0 0 +{ +T 150 850 5 8 1 1 0 0 1 +pinnumber=2 +T 150 850 5 8 0 0 0 0 1 +pinseq=2 +T 150 850 5 8 0 1 0 0 1 +pinlabel=2 +T 150 850 5 8 0 1 0 0 1 +pintype=pas +} +P 100 0 100 200 1 0 0 +{ +T 150 50 5 8 1 1 0 0 1 +pinnumber=1 +T 150 50 5 8 0 0 0 0 1 +pinseq=1 +T 150 50 5 8 0 1 0 0 1 +pinlabel=1 +T 150 50 5 8 0 1 0 0 1 +pintype=pas +} +V 100 700 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 100 300 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 0 200 200 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 300 500 5 8 0 0 0 0 1 +device=JUMPER +T 300 500 8 10 1 1 0 0 1 +refdes=J?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/jumper-3pin.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,44 @@ +v 20040111 1 +P 100 1000 100 750 1 0 0 +{ +T 150 850 5 8 1 1 0 0 1 +pinnumber=3 +T 150 850 5 8 0 0 0 0 1 +pinseq=3 +T 150 850 5 8 0 1 0 0 1 +pinlabel=3 +T 150 850 5 8 0 1 0 0 1 +pintype=pas +} +P 400 500 150 500 1 0 0 +{ +T 250 550 5 8 1 1 0 0 1 +pinnumber=2 +T 250 550 5 8 0 0 0 0 1 +pinseq=2 +T 250 550 5 8 0 1 0 0 1 +pinlabel=2 +T 250 550 5 8 0 1 0 0 1 +pintype=pas +} +P 100 0 100 250 1 0 0 +{ +T 150 50 5 8 1 1 0 0 1 +pinnumber=1 +T 150 50 5 8 0 0 0 0 1 +pinseq=1 +T 150 50 5 8 0 1 0 0 1 +pinlabel=1 +T 150 50 5 8 0 1 0 0 1 +pintype=pas +} +V 100 700 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 100 500 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +V 100 300 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +B 0 200 200 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 250 300 5 8 0 0 0 0 1 +device=JUMPER +T 250 500 5 8 0 0 0 0 1 +footprint=JUMPER3 +T 250 700 8 10 1 1 0 0 1 +refdes=J?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/led-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,28 @@ +L 600 0 600 400 3 0 0 0 -1 -1 +L 600 0 300 200 3 0 0 0 -1 -1 +L 300 200 600 400 3 0 0 0 -1 -1 +L 300 0 300 400 3 0 0 0 -1 -1 +P 0 200 200 200 1 0 0 +{ +T 150 300 5 8 1 1 0 0 1 +pinnumber=%d +T 800 650 9 8 0 1 180 0 1 +pinname=C +} +P 900 200 700 200 1 0 0 +{ +T 650 300 5 8 1 1 0 0 1 +pinnumber=%d +T 1400 150 9 8 0 1 180 0 1 +pinname=A +} +L 200 200 300 200 3 0 0 0 -1 -1 +L 600 200 700 200 3 0 0 0 -1 -1 +T 450 550 8 10 1 1 0 0 1 +refdes=D? +L 500 400 400 500 3 0 0 0 -1 -1 +L 400 400 300 500 3 0 0 0 -1 -1 +L 300 500 325 450 3 0 0 0 -1 -1 +L 300 500 350 475 3 0 0 0 -1 -1 +L 400 500 425 450 3 0 0 0 -1 -1 +L 400 500 450 475 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/mkheader.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,64 @@ +/* + * This program generates a uschem (subset of gschem) symbol + * for a dual-row header. Can also be used for board-to-board connectors. + */ + +#include <stdio.h> +#include <strings.h> +#include <ctype.h> + +int npins, btb; +int pinlength = 300, vstep = 400, boxwidth = 800; +int textoff_x = 75, textoff_y = 50; +int curpin, ycoord; + +doit() +{ + ycoord = npins / 2 * vstep; + printf("B %d 0 %d %d 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1\n", pinlength, + boxwidth, ycoord); + if (!btb) + printf("L %d %d %d 0 3 0 0 0 -1 -1\n", + pinlength + boxwidth / 2, ycoord, + pinlength + boxwidth / 2); + for (curpin = 1; curpin <= npins; ) { + ycoord -= vstep / 2; + printf("P 0 %d %d %d 1 0 0\n{\n", ycoord, pinlength, ycoord); + printf("T %d %d 5 8 1 1 0 6 1\n", pinlength - textoff_x, + ycoord + textoff_y); + printf("pinnumber=%d\n}\n", curpin++); + printf("P %d %d %d %d 1 0 1\n{\n", pinlength + boxwidth, ycoord, + pinlength * 2 + boxwidth, ycoord); + printf("T %d %d 5 8 1 1 0 0 1\n", + pinlength + boxwidth + textoff_x, ycoord + textoff_y); + printf("pinnumber=%d\n}\n", curpin); + ycoord -= vstep / 2; + if (!btb && curpin < npins) + printf("L %d %d %d %d 3 0 0 0 -1 -1\n", pinlength, + ycoord, pinlength + boxwidth, ycoord); + curpin++; + } +} + +main(argc, argv) + char **argv; +{ + char **ap; + + ap = argv + 1; + if (*ap && !strcmp(*ap, "-b")) { + ap++; + btb = 1; + } + if (!*ap || !isdigit(**ap)) { + fprintf(stderr, "usage: %s [-b] npins\n", argv[0]); + exit(1); + } + npins = atoi(*ap); + if (npins < 2 || npins & 1) { + fprintf(stderr, "%s: invalid npins argument\n", argv[0]); + exit(1); + } + doit(); + exit(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/modjack-6.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,90 @@ +v 20040111 1 +B 0 0 600 1400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 900 1200 600 1200 1 0 0 +{ +T 700 1250 5 8 1 1 0 0 1 +pinnumber=1 +T 700 1250 5 8 0 1 0 0 1 +pinseq=1 +T 700 1250 5 8 0 1 0 6 1 +pinlabel=I0 +T 700 1250 5 8 0 1 0 8 1 +pintype=in +} +V 400 1200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 1200 600 1200 3 0 0 0 -1 -1 +P 900 1000 600 1000 1 0 0 +{ +T 700 1050 5 8 1 1 0 0 1 +pinnumber=2 +T 700 1050 5 8 0 1 0 0 1 +pinseq=2 +T 700 1050 5 8 0 1 0 6 1 +pinlabel=I1 +T 700 1050 5 8 0 1 0 8 1 +pintype=in +} +V 200 1000 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 1000 600 1000 3 0 0 0 -1 -1 +P 900 800 600 800 1 0 0 +{ +T 700 850 5 8 1 1 0 0 1 +pinnumber=3 +T 700 850 5 8 0 1 0 0 1 +pinseq=3 +T 700 850 5 8 0 1 0 6 1 +pinlabel=I2 +T 700 850 5 8 0 1 0 8 1 +pintype=in +} +V 400 800 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 800 600 800 3 0 0 0 -1 -1 +P 900 600 600 600 1 0 0 +{ +T 700 650 5 8 1 1 0 0 1 +pinnumber=4 +T 700 650 5 8 0 1 0 0 1 +pinseq=4 +T 700 650 5 8 0 1 0 6 1 +pinlabel=I3 +T 700 650 5 8 0 1 0 8 1 +pintype=in +} +V 200 600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 600 600 600 3 0 0 0 -1 -1 +P 900 400 600 400 1 0 0 +{ +T 700 450 5 8 1 1 0 0 1 +pinnumber=5 +T 700 450 5 8 0 1 0 0 1 +pinseq=5 +T 700 450 5 8 0 1 0 6 1 +pinlabel=I4 +T 700 450 5 8 0 1 0 8 1 +pintype=in +} +V 400 400 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 400 600 400 3 0 0 0 -1 -1 +P 900 200 600 200 1 0 0 +{ +T 700 250 5 8 1 1 0 0 1 +pinnumber=6 +T 700 250 5 8 0 1 0 0 1 +pinseq=6 +T 700 250 5 8 0 1 0 6 1 +pinlabel=I5 +T 700 250 5 8 0 1 0 8 1 +pintype=in +} +V 200 200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 200 600 200 3 0 0 0 -1 -1 +T 0 1700 9 10 1 1 0 0 1 +device=MODJACK +T 0 2300 5 10 0 0 0 0 1 +footprint=RJ12 +T 0 2100 5 10 0 0 0 0 1 +description=6-position modular jack +T 0 1500 8 10 1 1 0 0 1 +refdes=J? +T 0 2700 5 10 0 0 0 0 1 +numslots=0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/modjack-8.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,116 @@ +v 20031231 1 +B 0 0 600 1800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 900 1600 600 1600 1 0 0 +{ +T 700 1650 5 8 1 1 0 0 1 +pinnumber=1 +T 700 1650 5 8 0 1 0 0 1 +pinseq=1 +T 700 1650 5 8 0 1 0 6 1 +pinlabel=I0 +T 700 1650 5 8 0 1 0 8 1 +pintype=in +} +V 400 1600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 1600 600 1600 3 0 0 0 -1 -1 +P 900 1400 600 1400 1 0 0 +{ +T 700 1450 5 8 1 1 0 0 1 +pinnumber=2 +T 700 1450 5 8 0 1 0 0 1 +pinseq=2 +T 700 1450 5 8 0 1 0 6 1 +pinlabel=I1 +T 700 1450 5 8 0 1 0 8 1 +pintype=in +} +V 200 1400 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 1400 600 1400 3 0 0 0 -1 -1 +P 900 1200 600 1200 1 0 0 +{ +T 700 1250 5 8 1 1 0 0 1 +pinnumber=3 +T 700 1250 5 8 0 1 0 0 1 +pinseq=3 +T 700 1250 5 8 0 1 0 6 1 +pinlabel=I2 +T 700 1250 5 8 0 1 0 8 1 +pintype=in +} +V 400 1200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 1200 600 1200 3 0 0 0 -1 -1 +P 900 1000 600 1000 1 0 0 +{ +T 700 1050 5 8 1 1 0 0 1 +pinnumber=4 +T 700 1050 5 8 0 1 0 0 1 +pinseq=4 +T 700 1050 5 8 0 1 0 6 1 +pinlabel=I3 +T 700 1050 5 8 0 1 0 8 1 +pintype=in +} +V 200 1000 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 1000 600 1000 3 0 0 0 -1 -1 +P 900 800 600 800 1 0 0 +{ +T 700 850 5 8 1 1 0 0 1 +pinnumber=5 +T 700 850 5 8 0 1 0 0 1 +pinseq=5 +T 700 850 5 8 0 1 0 6 1 +pinlabel=I4 +T 700 850 5 8 0 1 0 8 1 +pintype=in +} +V 400 800 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 800 600 800 3 0 0 0 -1 -1 +P 900 600 600 600 1 0 0 +{ +T 700 650 5 8 1 1 0 0 1 +pinnumber=6 +T 700 650 5 8 0 1 0 0 1 +pinseq=6 +T 700 650 5 8 0 1 0 6 1 +pinlabel=I5 +T 700 650 5 8 0 1 0 8 1 +pintype=in +} +V 200 600 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 600 600 600 3 0 0 0 -1 -1 +P 900 400 600 400 1 0 0 +{ +T 700 450 5 8 1 1 0 0 1 +pinnumber=7 +T 700 450 5 8 0 1 0 0 1 +pinseq=7 +T 700 450 5 8 0 1 0 6 1 +pinlabel=I6 +T 700 450 5 8 0 1 0 8 1 +pintype=in +} +V 400 400 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 450 400 600 400 3 0 0 0 -1 -1 +P 900 200 600 200 1 0 0 +{ +T 700 250 5 8 1 1 0 0 1 +pinnumber=8 +T 700 250 5 8 0 1 0 0 1 +pinseq=8 +T 700 250 5 8 0 1 0 6 1 +pinlabel=I7 +T 700 250 5 8 0 1 0 8 1 +pintype=in +} +V 200 200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 250 200 600 200 3 0 0 0 -1 -1 +T 0 2100 9 10 1 1 0 0 1 +device=MODJACK +T 0 2700 5 10 0 0 0 0 1 +footprint=RJ45 +T 0 2500 5 10 0 0 0 0 1 +description=8-position modular jack +T 0 1900 8 10 1 1 0 0 1 +refdes=J? +T 0 3100 5 10 0 0 0 0 1 +numslots=0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/resistor-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,38 @@ +v 20031231 1 +L 600 200 500 0 3 0 0 0 -1 -1 +L 500 0 400 200 3 0 0 0 -1 -1 +L 400 200 300 0 3 0 0 0 -1 -1 +L 300 0 200 200 3 0 0 0 -1 -1 +T 300 400 5 10 0 0 0 0 1 +device=RESISTOR +L 600 200 700 0 3 0 0 0 -1 -1 +L 700 0 750 100 3 0 0 0 -1 -1 +P 900 100 750 100 1 0 0 +{ +T 800 150 5 8 0 1 0 0 1 +pinnumber=2 +T 800 150 5 8 0 0 0 0 1 +pinseq=2 +T 800 150 5 8 0 1 0 0 1 +pinlabel=2 +T 800 150 5 8 0 1 0 0 1 +pintype=pas +} +P 0 100 152 100 1 0 0 +{ +T 100 150 5 8 0 1 0 0 1 +pinnumber=1 +T 100 150 5 8 0 0 0 0 1 +pinseq=1 +T 100 150 5 8 0 1 0 0 1 +pinlabel=1 +T 100 150 5 8 0 1 0 0 1 +pintype=pas +} +L 201 200 150 100 3 0 0 0 -1 -1 +T 200 300 8 10 1 1 0 0 1 +refdes=R? +T 0 0 8 10 0 1 0 0 1 +pins=2 +T 0 0 8 10 0 1 0 0 1 +class=DISCRETE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/resistor-2-slotted.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +P 900 100 750 100 1 0 0 +{ +T 800 150 5 8 1 1 0 0 1 +pinnumber=%d +attr pinname=side2 +} +P 0 100 152 100 1 0 0 +{ +T 100 150 5 8 1 1 0 6 1 +pinnumber=%d +attr pinname=side1 +} +B 150 0 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 350 5 10 0 0 0 0 1 +device=RESISTOR +T 200 300 8 10 1 1 0 0 1 +refdes=R?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/resistor-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,28 @@ +v 20031231 1 +P 900 100 750 100 1 0 0 +{ +T 800 150 5 8 0 1 0 0 1 +pinnumber=2 +T 800 150 5 8 0 0 0 0 1 +pinseq=2 +T 800 150 5 8 0 1 0 0 1 +pinlabel=2 +T 800 150 5 8 0 1 0 0 1 +pintype=pas +} +P 0 100 152 100 1 0 0 +{ +T 100 150 5 8 0 1 0 0 1 +pinnumber=1 +T 100 150 5 8 0 0 0 0 1 +pinseq=1 +T 100 150 5 8 0 1 0 0 1 +pinlabel=1 +T 100 150 5 8 0 1 0 0 1 +pintype=pas +} +B 150 0 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 350 5 10 0 0 0 0 1 +device=RESISTOR +T 200 300 8 10 1 1 0 0 1 +refdes=R?
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/resistornetwork-13.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,200 @@ +v 20040111 1 +P 0 200 300 200 1 0 0 +{ +T 100 250 5 8 1 1 0 0 1 +pinnumber=1 +T 100 250 5 8 0 0 0 0 1 +pinseq=1 +T 100 250 5 8 0 1 0 0 1 +pinlabel=1 +T 100 250 5 8 0 1 0 0 1 +pintype=pas +} +B 450 100 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1700 350 5 10 0 0 0 0 1 +device=RESISTOR_NETWORK +T 1400 5000 8 10 1 1 0 0 1 +refdes=RN? +L 300 200 450 200 3 0 0 0 -1 -1 +L 1050 200 1200 200 3 0 0 0 -1 -1 +B 450 500 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 600 450 600 3 0 0 0 -1 -1 +L 1050 600 1200 600 3 0 0 0 -1 -1 +P 0 600 300 600 1 0 0 +{ +T 100 650 5 8 1 1 0 0 1 +pinnumber=2 +T 100 650 5 8 0 0 0 0 1 +pinseq=2 +T 100 650 5 8 0 1 0 0 1 +pinlabel=2 +T 100 650 5 8 0 1 0 0 1 +pintype=pas +} +B 450 900 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 1000 450 1000 3 0 0 0 -1 -1 +L 1050 1000 1200 1000 3 0 0 0 -1 -1 +P 0 1000 300 1000 1 0 0 +{ +T 100 1050 5 8 1 1 0 0 1 +pinnumber=3 +T 100 1050 5 8 0 0 0 0 1 +pinseq=3 +T 100 1050 5 8 0 1 0 0 1 +pinlabel=3 +T 100 1050 5 8 0 1 0 0 1 +pintype=pas +} +B 450 1300 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 1400 450 1400 3 0 0 0 -1 -1 +L 1050 1400 1200 1400 3 0 0 0 -1 -1 +P 0 1400 300 1400 1 0 0 +{ +T 100 1450 5 8 1 1 0 0 1 +pinnumber=4 +T 100 1450 5 8 0 0 0 0 1 +pinseq=4 +T 100 1450 5 8 0 1 0 0 1 +pinlabel=4 +T 100 1450 5 8 0 1 0 0 1 +pintype=pas +} +B 450 1700 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 1800 450 1800 3 0 0 0 -1 -1 +L 1050 1800 1200 1800 3 0 0 0 -1 -1 +P 0 1800 300 1800 1 0 0 +{ +T 100 1850 5 8 1 1 0 0 1 +pinnumber=5 +T 100 1850 5 8 0 0 0 0 1 +pinseq=5 +T 100 1850 5 8 0 1 0 0 1 +pinlabel=5 +T 100 1850 5 8 0 1 0 0 1 +pintype=pas +} +B 450 2100 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 2200 450 2200 3 0 0 0 -1 -1 +L 1050 2200 1200 2200 3 0 0 0 -1 -1 +P 0 2200 300 2200 1 0 0 +{ +T 100 2250 5 8 1 1 0 0 1 +pinnumber=6 +T 100 2250 5 8 0 0 0 0 1 +pinseq=6 +T 100 2250 5 8 0 1 0 0 1 +pinlabel=6 +T 100 2250 5 8 0 1 0 0 1 +pintype=pas +} +B 450 2500 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 2600 450 2600 3 0 0 0 -1 -1 +L 1050 2600 1200 2600 3 0 0 0 -1 -1 +P 0 2600 300 2600 1 0 0 +{ +T 100 2650 5 8 1 1 0 0 1 +pinnumber=7 +T 100 2650 5 8 0 0 0 0 1 +pinseq=7 +T 100 2650 5 8 0 1 0 0 1 +pinlabel=7 +T 100 2650 5 8 0 1 0 0 1 +pintype=pas +} +B 450 2900 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 3000 450 3000 3 0 0 0 -1 -1 +L 1050 3000 1200 3000 3 0 0 0 -1 -1 +P 0 3000 300 3000 1 0 0 +{ +T 100 3050 5 8 1 1 0 0 1 +pinnumber=8 +T 100 3050 5 8 0 0 0 0 1 +pinseq=8 +T 100 3050 5 8 0 1 0 0 1 +pinlabel=8 +T 100 3050 5 8 0 1 0 0 1 +pintype=pas +} +B 450 3300 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 3400 450 3400 3 0 0 0 -1 -1 +L 1050 3400 1200 3400 3 0 0 0 -1 -1 +P 0 3400 300 3400 1 0 0 +{ +T 100 3450 5 8 1 1 0 0 1 +pinnumber=9 +T 100 3450 5 8 0 0 0 0 1 +pinseq=9 +T 100 3450 5 8 0 1 0 0 1 +pinlabel=9 +T 100 3450 5 8 0 1 0 0 1 +pintype=pas +} +B 450 3700 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 3800 450 3800 3 0 0 0 -1 -1 +L 1050 3800 1200 3800 3 0 0 0 -1 -1 +P 0 3800 300 3800 1 0 0 +{ +T 100 3850 5 8 1 1 0 0 1 +pinnumber=10 +T 100 3850 5 8 0 0 0 0 1 +pinseq=10 +T 100 3850 5 8 0 1 0 0 1 +pinlabel=10 +T 100 3850 5 8 0 1 0 0 1 +pintype=pas +} +B 450 4100 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 4200 450 4200 3 0 0 0 -1 -1 +L 1050 4200 1200 4200 3 0 0 0 -1 -1 +P 0 4200 300 4200 1 0 0 +{ +T 100 4250 5 8 1 1 0 0 1 +pinnumber=11 +T 100 4250 5 8 0 0 0 0 1 +pinseq=11 +T 100 4250 5 8 0 1 0 0 1 +pinlabel=11 +T 100 4250 5 8 0 1 0 0 1 +pintype=pas +} +B 450 4500 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 4600 450 4600 3 0 0 0 -1 -1 +L 1050 4600 1200 4600 3 0 0 0 -1 -1 +P 0 4600 300 4600 1 0 0 +{ +T 100 4650 5 8 1 1 0 0 1 +pinnumber=12 +T 100 4650 5 8 0 0 0 0 1 +pinseq=12 +T 100 4650 5 8 0 1 0 0 1 +pinlabel=12 +T 100 4650 5 8 0 1 0 0 1 +pintype=pas +} +B 450 4900 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 5000 450 5000 3 0 0 0 -1 -1 +L 1050 5000 1200 5000 3 0 0 0 -1 -1 +P 0 5000 300 5000 1 0 0 +{ +T 100 5050 5 8 1 1 0 0 1 +pinnumber=13 +T 100 5050 5 8 0 0 0 0 1 +pinseq=13 +T 100 5050 5 8 0 1 0 0 1 +pinlabel=13 +T 100 5050 5 8 0 1 0 0 1 +pintype=pas +} +L 1200 200 1200 5200 3 0 0 0 -1 -1 +B 300 0 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1200 5200 1200 5500 1 0 1 +{ +T 1300 5300 5 8 1 1 0 0 1 +pinnumber=14 +T 1300 5300 5 8 0 1 0 0 1 +pinseq=14 +T 1300 5300 5 8 0 1 0 0 1 +pinlabel=14 +T 1300 5300 5 8 0 1 0 0 1 +pintype=pas +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/rpack4.pinout Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,9 @@ +#pin name pin number +side1:1 1 +side1:2 2 +side1:3 3 +side1:4 4 +side2:4 5 +side2:3 6 +side2:2 7 +side2:1 8
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/sidactor-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,33 @@ +v 20040111 1 +L 100 600 500 600 3 0 0 0 -1 -1 +T 0 1800 5 10 0 0 0 0 1 +device=SIDACTOR +L 100 900 500 900 3 0 0 0 -1 -1 +P 300 0 300 200 1 0 0 +{ +T 250 100 5 8 0 1 90 0 1 +pinnumber=1 +T 250 100 5 8 0 0 90 0 1 +pinseq=1 +T 250 100 5 8 0 1 90 0 1 +pinlabel=1 +T 250 100 5 8 0 1 90 0 1 +pintype=pas +} +P 300 1200 300 1000 1 0 0 +{ +T 250 1000 5 8 0 1 90 0 1 +pinnumber=2 +T 250 1000 5 8 0 0 90 0 1 +pinseq=2 +T 250 1000 5 8 0 1 90 0 1 +pinlabel=2 +T 250 1000 5 8 0 1 90 0 1 +pintype=pas +} +L 300 1000 300 900 3 0 0 0 -1 -1 +L 300 300 300 200 3 0 0 0 -1 -1 +T 600 600 8 10 1 1 0 0 1 +refdes=S? +L 100 300 500 300 3 0 0 0 -1 -1 +L 500 900 100 300 3 0 0 0 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/sidactor-2.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,50 @@ +v 20040111 1 +L 100 600 500 600 3 0 0 0 -1 -1 +T 0 1800 5 10 0 0 0 0 1 +device=SIDACTOR +L 100 900 500 900 3 0 0 0 -1 -1 +P 300 0 300 200 1 0 0 +{ +T 200 150 5 8 1 1 180 0 1 +pinnumber=3 +T 250 100 5 8 0 0 90 0 1 +pinseq=3 +T 250 100 5 8 0 1 90 0 1 +pinlabel=3 +T 250 100 5 8 0 1 90 0 1 +pintype=pas +} +L 300 300 300 200 3 0 0 0 -1 -1 +T 600 1800 8 10 1 1 0 0 1 +refdes=S? +L 100 300 500 300 3 0 0 0 -1 -1 +L 500 900 100 300 3 0 0 0 -1 -1 +L 100 1800 500 1800 3 0 0 0 -1 -1 +L 100 2100 500 2100 3 0 0 0 -1 -1 +P 300 2400 300 2200 1 0 0 +{ +T 200 2250 5 8 1 1 180 0 1 +pinnumber=1 +T 250 2200 5 8 0 0 90 0 1 +pinseq=1 +T 250 2200 5 8 0 1 90 0 1 +pinlabel=1 +T 250 2200 5 8 0 1 90 0 1 +pintype=pas +} +L 300 2200 300 2100 3 0 0 0 -1 -1 +L 100 1500 500 1500 3 0 0 0 -1 -1 +L 500 2100 100 1500 3 0 0 0 -1 -1 +L 300 1500 300 900 3 0 0 0 -1 -1 +L 300 1200 600 1200 3 0 0 0 -1 -1 +P 800 1200 600 1200 1 0 0 +{ +T 700 1250 5 8 1 1 0 0 1 +pinnumber=2 +T 700 1250 5 8 0 1 0 0 1 +pinseq=2 +T 700 1250 5 8 0 1 0 0 1 +pinlabel=2 +T 700 1250 5 8 0 1 0 0 1 +pintype=pas +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/sidactor-3.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,56 @@ +v 20040111 1 +L 100 600 500 600 3 0 0 0 -1 -1 +T 0 1800 5 10 0 0 0 0 1 +device=SIDACTOR +L 100 900 500 900 3 0 0 0 -1 -1 +P 300 0 300 200 1 0 0 +{ +T 150 50 5 8 1 1 0 0 1 +pinnumber=3 +T 250 100 5 8 0 0 90 0 1 +pinseq=3 +T 250 100 5 8 0 1 90 0 1 +pinlabel=3 +T 250 100 5 8 0 1 90 0 1 +pintype=pas +} +L 300 300 300 200 3 0 0 0 -1 -1 +T 1500 2250 8 10 1 1 0 6 1 +refdes=S? +L 100 300 500 300 3 0 0 0 -1 -1 +L 500 900 100 300 3 0 0 0 -1 -1 +L 100 1800 500 1800 3 0 0 0 -1 -1 +L 100 2100 500 2100 3 0 0 0 -1 -1 +P 300 2400 300 2200 1 0 0 +{ +T 150 2250 5 8 1 1 0 0 1 +pinnumber=1 +T 250 2200 5 8 0 0 90 0 1 +pinseq=1 +T 250 2200 5 8 0 1 90 0 1 +pinlabel=1 +T 250 2200 5 8 0 1 90 0 1 +pintype=pas +} +L 300 2200 300 2100 3 0 0 0 -1 -1 +L 100 1500 500 1500 3 0 0 0 -1 -1 +L 500 2100 100 1500 3 0 0 0 -1 -1 +L 300 1500 300 900 3 0 0 0 -1 -1 +P 1700 1200 1500 1200 1 0 0 +{ +T 1600 1250 5 8 1 1 0 0 1 +pinnumber=2 +T 1600 1250 5 8 0 1 0 0 1 +pinseq=2 +T 1600 1250 5 8 0 1 0 0 1 +pinlabel=2 +T 1600 1250 5 8 0 1 0 0 1 +pintype=pas +} +L 1100 1000 1100 1400 3 0 0 0 -1 -1 +L 800 1000 800 1400 3 0 0 0 -1 -1 +L 1400 1200 1500 1200 3 0 0 0 -1 -1 +L 1400 1000 1400 1400 3 0 0 0 -1 -1 +L 800 1400 1400 1000 3 0 0 0 -1 -1 +L 300 1200 800 1200 3 0 0 0 -1 -1 +B 0 200 1500 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ifctf-part-lib/uschem-symbols/testpt-1.sym Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,24 @@ +v 20031231 1 +P 100 0 100 200 1 0 0 +{ +T 300 0 5 10 0 0 0 0 1 +pinseq=1 +T 300 200 5 10 0 0 0 0 1 +pinnumber=1 +T 100 0 5 10 0 1 0 0 1 +pintype=io +T 100 0 5 10 0 1 0 0 1 +pinlabel=1 +} +L 0 300 100 200 3 0 0 0 -1 -1 +L 100 200 200 300 3 0 0 0 -1 -1 +L 0 300 100 400 3 0 0 0 -1 -1 +L 100 400 200 300 3 0 0 0 -1 -1 +T 100 400 8 10 1 1 0 0 1 +refdes=TP? +T 400 900 8 10 0 0 0 0 1 +device=TESTPOINT +T 400 700 8 10 0 0 0 0 1 +footprint=none +T 400 1100 8 10 0 0 0 0 1 +numslots=0
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,23 @@ +SUBDIR= libueda libuschem mclutils migration sverp uschem-netlist uschem-print \ + uschem-utils utils + +all: ${SUBDIR} + +${SUBDIR}: FRC + cd $@; make ${MFLAGS} + +mclutils: libueda +sverp: libueda +uschem-utils: libueda libuschem +uschem-print: libueda libuschem +uschem-netlist: libueda libuschem + +install: + -for i in ${SUBDIR}; do \ + (cd $$i; make ${MFLAGS} install); done + +clean: FRC + rm -f a.out core *.s *.o errs + for i in ${SUBDIR}; do (cd $$i; make ${MFLAGS} clean); done + +FRC:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/README Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,3 @@ +Read doc/overview.txt to find out what uEDA is. Read everything else under +doc/ to get a feel for it. If you still like it after reading all that, +compilation and installation should be straightforward with the Makefile.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/doc/bom_model.txt Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,131 @@ +Bill of Materials (BOM) handling in uEDA + +There are a number of reasons why one may want to have a BOM for a board design: + +* To have a list of all components outside of schematic drawing files +* To have a list of PCB land patterns for pre-layout (see prelayout.txt) +* For purchasing or other part procurement +* For handing to assemblers (those who populate the parts on the board) +* For quick reference + +Although one is often tempted to get away with keeping the "BOM" information in +his head, a formal BOM is a good thing to have. + +OK, so we are going to have a BOM. But what exactly is the BOM in precise +terms, and what is its format? uEDA provides several different facilities for +BOM handling. + +The MCL + +Whether or not you are interested in any of the other BOM formats, you have to +have the MCL. It is a critical part of the design source code in the uEDA flow +model. It's a human-created and human-edited text file described in great +detail in mcldoc.txt. + +Having a simple and intuitive text-based format, MCL can be readily viewed and +printed. As it contains the complete information about all components in the +design, i.e., all BOM information, it is in itself a type of BOM. It is in a +way "the ultimate BOM". There are, however, a few situations in which other +BOM formats are desirable. + +Procurement BOM + +You write the MCL for your design. For each component you enter all the +attributes that you may need for procurent: manufacturer, +manufacturer_part_number, vendor, vendor_part_number, etc. But now it's +actually time to order the parts. What quantity of what part numbers do you +order? All necessary information is in the MCL, but it isn't at all obvious +for filling out order forms. One really needs a distilled BOM for procurement. + +The ueda-mkbom utility generates a procurement-oriented BOM from the MCL. +First it reads the MCL and makes note of all components that have been reduced +to parts. (Components that haven't been reduced to parts are ignored, though +the user can request that a warning be issued. You need to reduce all +components to parts for this function to be useful, see mcldoc.txt for the +details.) All multiple instances of each part are tallied together. +Finally, output is emitted which is centered around parts with a quantity for +each, rather than around reference designators. (A list of refdes'ed components +using each part can optionally be emitted.) Each entry is given a heading and +usually some comment lines based on part attributes from the MCL which are +deemed relevant to the procurement BOM. See mcldoc.txt for the details. + +One can generate procurement BOMs for different population options, see below. + +The procurement BOM generated by ueda-mkbom is plain text formatted on the +assumption of 80 columns of fixed character spacing. It is thus suitable for +both online viewing and printing. + +Short BOM + +For purposes other than procurement of parts, component reference designators +do matter, and a BOM organised and sorted by the component refdes is the right +format. MCL is such a format, and oftentimes it serves quite well. + +Sometimes however, it is desirable to have a "short BOM" that is ordered by +the component refdes like the MCL, but follows a tabular format with one line +per component and with columns corresponding to a few attributes deemed most +useful. + +The ueda-shortbom utility generates such a "short BOM" with 4 columns: refdes, +manufacturer, part number and description. The manufacturer and description +columns are taken from the identically named MCL attributes; the part number +column is taken from the manufacturer_part_number= attribute if one is defined, +otherwise the device= attribute is used instead. If neither attribute is +defined, the string "unknown" is substituted. The same holds for the +manufacturer column. The description column is left blank if no description= +attribute is defined. + +The intent is that the MCL would be used directly only by the board designer +himself, who would of course be intimately familiar with the UNIX environment, +the workings of uEDA and its file formats, and the way his particular MCL is +structured, whereas the short BOM would be given to lab technicians and others +who are not UNIX-based intellectual creators. + +ueda-shortbom can generate plain text output that is directly usable for viewing +and printing in a fixed character spacing environment, but it usually ends up +needing more than 80 characters per line and thus a pain to work with. +ueda-shortbom can also produce output with columns separated by ASCII tab +characters irrespective of field widths; such output is useful for post- +processing. UNIX tbl(1) and troff(1) can be used to produce a very pretty +hard copy (PostScript) version of the short BOM. + +Assembly BOM + +An assembly BOM is exactly the same as the short BOM described above, but has +one difference: if a component is to be socketed, the information put in the +corresponding columns of the assembly BOM is that for the socket part, rather +than for the component to be pushed into the socket. The assembly BOM is thus +exactly what you need to give to those who will be stuffing parts on your board +and running it through the reflow oven. + +An assembly BOM is generated by the ueda-shortbom utility with the -a option. +Since one would need to generate different assembly BOMs for different +population options (assuming that the document is intended for those who will +follow it blindly), ueda-shortbom supports population options as well. +See the ueda-shortbom(1) man page for details. + +If your design uses no socketed parts and no population options, the short BOM +and the assembly BOM would be identical. + +Population options + +uEDA supports designs with population options, i.e., ones in which some +components may or may not be populated as a manufacturing option. They are +described in this document because the BOM is really the only part of the uEDA +flow for which population options matter. The PCB obviously has to have +footprints for all components that may ever be populated on it and the +schematics normally show the interconnections for all possible components as +well. The BOM is the only part that is made in multiple versions for different +population options. + +In order to support population options, each component in the design (i.e., in +the MCL) is assigned to a numbered population group. Population groups are +identified by integers and a component is assigned to a given population group +via the population_option= attribute in the MCL. Components without this +attribute are assigned to population group 0, the default. + +When generating a BOM for a given population option, specify the list of +population groups to be included (see ueda-mkbom(1) and ueda-shortbom(1)). +The default population option consists of population group 0, i.e., running +ueda-mkbom or ueda-shortbom without any options counts only those components +which do not have a population_option= attribute.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/doc/mcldoc.txt Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,395 @@ +uEDA Master Component List (MCL) description + +The MCL is an essential component of the design source code in the uEDA flow. +It is a human-created and human-edited text file which lists all components on +the board being designed and all their attributes. The file must be named +"MCL" (w/o quotes) and must reside in the project directory. This document +describes the file format and everything you need to know in order to write the +MCL for your board. + +Each component on the board must have a reference designator (refdes). Valid +characters for the refdes are uppercase and lowercase letters and digits; the +first character must be an uppercase letter. Lowercase letters are allowed but +not recommended, in particular a refdes should not end in any lowercase letters +- see the description of component instances in netlisting.txt for the +explanation. + +The MCL contains a section for each component of the form: + +refdes: + attribute=value + attribute=value + ... + +Each refdes line must begin in the leftmost column without leading spaces +and end with a colon. It is followed by attribute lines defining various +attributes for the component in question; these attributes are the essence of +the information contained in the MCL. Different attributes are required by +different tools in the uEDA suite and all currently defined attributes are +listed in this document. Attributes are name=value pairs and attribute lines +in the MCL must begin with a tab or space. Both the name and the value must +be present and non-null. For most attributes it is meaningless and illegal to +have multiple attributes with the same name for the same component, but there +are a few attributes which can be given more than once for a given component. +Attribute values may contain spaces. + +Blank lines are ignored and non-processed comments may appear anywhere in the +file introduced by a '#' character. Everything between a '#' character and +the following newline is ignored. + +Here is an example component definition that can appear in the MCL: + +J1: + device=DB25F + footprint=DB25F + description=Connector, DB25F, right angle + manufacturer=AMP + manufacturer_part_number=747846-4 + +If it is desired to define multiple components with the same attributes, the +following shorthand syntax may be used: + +C43,C44,C45,C46,C47,C48,C49: + # Voltage reference capacitors for RS8973 + # schematic page 6 + value=0.22 uF + footprint=0805 + description=Ceramic chip capacitor, X7R, 0.22 uF, 0805 + manufacturer=Panasonic + manufacturer_part_number=ECJ-2VB1C224K + vendor=Digi-Key + vendor_part_number=PCC1816CT-ND + bom_comment=RoHS part, no SnPb version available + +uEDA tools generally process components in the order in which they are defined +in the MCL, thus you should list your components in the MCL in the order in +which you would like them to appear on the BOMs generated from it. In +particular, there is no collating function for the refdes string, so if you have +a collating order in mind for your reference designators, implement it in the +order in which you list them in the MCL. + +Currently defined attributes + +bom_comment= + + This attribute specifies a free-form line of text to be included in the + procurement BOM (generated by ueda-mkbom) for this part. This attribute + may be given more than once in order to include multiple comment lines. + This attribute should be used to include information in the BOM that is + not covered by any other defined attributes. + +bom_part_title= + + This attribute specifies the title line for this part in the procurement + BOM. Normally the title line is constructed from the manufacturer= and + manufacturer_part_number= attributes, but this attribute overrides it. + +description= + + This attribute gives a one line summary description of the component for + BOMs. What information should be included is subjective, but one + starting point is that uEDA-generated BOMs include the information from + the manufacturer= and manufacturer_part_number= attributes, but not from + other attributes like value= or footprint=. Thus if the value and + footprint information is desired, it should be included in the + description, but don't include the manufacturer or the part #. + +device= + + If the component has an associated alphanumeric designation that is + universally recognized and meaningful to someone looking at your design + at the high level (i.e., without getting down to part numbers), it + should be given as the device= attribute. Examples: + + device=74LS04 + device=29F010 + device=41256 + + A good general rule of thumb is that if it isn't obvious what to put in + the device= attribute, you probably shouldn't have this attribute at all + for the component rather than make something up. In particular, basic + semiconductors (diodes and transistors) and passives do not use this + attribute. + + The device= attribute is not currently used very much by uEDA tools, + but it sometimes provides a fallback for the manufacturer_part_number= + attribute if the latter isn't given. + +footprint= + + This attribute facilitates the pre-layout step of the uEDA flow. + See prelayout.txt for the details. + + A value of "none" indicates that the component has no footprint on the + PCB. I admit that the physical meaning of such a specification is a + little unclear, but ueda-getfps will skip such components without error + or warning messages. + + A value of "TBD" (to be determined) means that you realise you need a + footprint, but aren't able to name it yet. ueda-getfps recognizes this + special value and issues an appopriate warning, but doesn't try to look + for an actual footprint named "TBD". + +manufacturer= + + Should be self-explanatory. + +manufacturer_part_number= + + Should be self-explanatory. Meaningless without manufacturer= also + being specified. + +npins= + + In the uEDA model pin numbers are arbitrary alphanumeric strings in the + general case, allowing for mixed alphanumeric pin "numbers" used on PGA + and BGA packages. However, most components have simple numeric pin + numbers ranging from 1 to some N inclusive. If your component falls + into the latter category, you should define an npins=N attribute. + Having this definition makes uschem-netlist(1) run much more + efficiently, detect invalid pin numbers and produce naturally sorted + pin lists. + +part= + + See the Components vs. parts section below. + +pcbvalue= + + The PCB layout file format includes 3 ASCII strings for each element: + "description" (not really used, uEDA puts the footprint name there), + "name on the PCB" (refdes) and "value". + + The pcbvalue= attribute explicitly sets the "value" parameter in the + PCB elements generated by the ueda-getfps | ueda-runm4 pipeline (see + prelayout.txt). If the pcbvalue= attribute is not defined, ueda-getfps + tries value=, device= and manufacturer_part_number= in this order. If + none of these attributes are given, a null string is used. + +pinout= + + This attribute specifies the name of the pinout mapping file to be used + for this component. See the Pinout mapping section in netlisting.txt + for the explanation. + +population_option= + + See Population options in bom_model.txt. + + The value of this attribute is either a decimal integer identifying the + population group this component belongs to or the keyword "NO". + + population_option=NO indicates that the component is never populated at + all in any of the standard population options, e.g., a component that + is only populated for debug purposes. Such components appear in the BOM + only if -pall is given to ueda-mkbom(1) or ueda-shortbom(1). + +socket= + + If the component is to be socketed, this attribute specifies the part ID + for the socket. See the Components vs. parts section below for the + explanation of the part ID. + +source= + + This attribute indicates a source for the procurement of this part. + It may be given more than once to indicate multiple sources where parts + can be obtained. + + If one or more source= attributes are given, the vendor= and + vendor_part_number= attributes are not used. + +substitute= + + This attribute lists an "acceptable substitute" for the part specified + by the manufacturer= and manufacturer_part_number= attributes. This + attribute may be given more than once. + + Given the unfortunate reality of part availability, it is often the + case that the manufacturer= and manufacturer_part_number= attributes + specify the ideal wish list part (e.g., one with SnPb solder coating) + while substitute= attributes list what's actually obtainable (e.g., the + lead-free crap). + +value= + + This attribute is intended to hold the value of components such as + resistors and capacitors for which a numeric value is meaningful. uEDA + does not currently make any formal use of this attribute, hence there + are no formal rules currently as to units, exact syntax etc. + +vendor= + + Should be self-explanatory. Specifies the name of a vendor from whom + the part may be obtained. + +vendor_part_number= + + Should be self-explanatory. Meaningless without vendor= also being + specified. + + Unlike source=, the vendor= and vendor_part_number= attributes may not + be given more than once. If multiple sources need to be listed, the + source= attribute must be used instead. Neither vendor= nor + vendor_part_number= is used if any source= attributes are present. + +Components vs. parts + +Contrast the following alternative descriptions of the same component: + +* A 0.1 uF capacitor +* Ceramic chip capacitor, X7R, 0.1 uF, 0805 +* Panasonic ECJ-2VB1C104K + +The first description is what you would likely use in the initial design of your +circuit, the second description may appear on the list of required components +when your design is finished, and a description of the third kind can be made +about the components found on the final board when it's fully assembled. + +The uEDA MCL makes a distinction between components and parts. A component is +something that has a refdes and an associated section in the MCL; a part is +something that can appear on a procurement BOM with a quantity next to it. +uEDA also has a process of "reducing components to parts", which basically +means going from a description of the first kind above to one of the 2nd or 3rd +kind. + +Given that you are free to specify or not specify each of the defined attributes +for each component in the MCL, your initial design may be as vague or as +specific as you like. For example, you may put a capacitor on your schematic +and list it in the MCL, but not specify anything else. Or you may specify the +value while leaving the footprint undecided. Or vice-versa. Or you could +specify both the value and the desired footprint, but put no more thought as +to what kind of actual capacitor you would need. + +However, when it's time to actually build your board, you will have to pick +some specific part from the Digi-Key catalog (or substitute your favourite +component supplier), order it and populate it on the board. That will be a +specific part with a very concrete set of parametric specifications. This is +what I mean by reducing components to parts. + +The concepts just described may be self-evident, but the reason I'm spelling +them out is that uEDA has some special support for reducing components to parts. +Namely, the MCL syntax that has been described so far is not actually the whole +story. If the syntax described so far was all that's available, the process of +reducing components to parts would be very clumsy. For example, if you had +decided that your 0.1 uF bypass caps would be 0805s and that you would order +and populate Panasonic ECJ-2VB1C104K parts for them, you would have to enter +the full information about this part for every component (every refdes) in the +MCL where you had a 0.1 uF bypass capacitor. This approach would suffer from +two problems: + +* The replication of information would be very redundant and error-prone. + +* The process for generating the procurement BOM would face the problem of + how to tally all of those separately described components into a quantity of + one part. + +The uEDA solution is that in addition to components with reference designators, +the MCL file format allows for part definitions. A part definition has the +following form: + +part part-ID: + attribute=value + attribute=value + ... + +The part-ID is an arbitrary ASCII label for your part. Component definitions +can then refer to your part definition by its part-ID using this syntax: + +refdes: + part=part-ID + +Example: + +part bypasscap-0.1uF-0805: + value=0.1 uF + footprint=0805 + description=Ceramic chip capacitor, X7R, 0.1 uF, 0805 + manufacturer=Panasonic + manufacturer_part_number=ECJ-2VB1C104K + vendor=Digi-Key + vendor_part_number=PCC1812CT-ND + bom_comment=RoHS part, no SnPb version available + +C1: + # Bypass cap for U5 + part=bypasscap-0.1uF-0805 + +Most tools in the uEDA suite treat such part references as nothing more than +shorthand, in other words, the example above would be equivalent to: + +C1: + value=0.1 uF + footprint=0805 + description=Ceramic chip capacitor, X7R, 0.1 uF, 0805 + manufacturer=Panasonic + manufacturer_part_number=ECJ-2VB1C104K + vendor=Digi-Key + vendor_part_number=PCC1812CT-ND + bom_comment=RoHS part, no SnPb version available + +The one important exception is ueda-mkbom. For the procurement-oriented BOM +parts are essential, and ueda-mkbom operates only on parts, not on components. +When it reads the example above, it takes note of part bypasscap-0.1uF-0805, +counts all components that refer to it and emits it in the BOM with the counted +quantity. + +What does ueda-mkbom do when it encounters a component that has no part= +attribute? It may be either a component that hasn't been reduced to a part yet +(in which case ueda-mkbom can't do anything with it other than issue a warning +message), or a component that self-defines its part. A component is considered +to self-define a part if it has both manufacturer= and manufacturer_part_number= +attributes or a bom_part_title= attribute. Alternatively, a component may be +explicitly declared to self-define its part with a part=yes attribute (see +below). + +Every part definition (explicit or implicit in a component that self-defines +its part) that is to be usable to ueda-mkbom must have some attributes from +which ueda-mkbom can make a title for it in the BOM. ueda-mkbom considers part +attributes in this order: + +* bom_part_title= if one is given +* manufacturer= and manufacturer_part_number= if both are given +* manufacturer= and device= if both are given +* description= if one is given + +If none of the above attributes are present for a part which needs to go into +the BOM, it is an error. + +Formal definition of the part= attribute + +The part= attribute may appear only in component definitions and not in part +definitions. The value of the part= attribute may be one of the following: + +* The keyword "none". This specification indicates that the component has no + associated part and that this lack of a part is not an error. Note that it's + possible to have a component which has no part but still has a footprint. + An example would be a test point or an antenna made from the copper etch on + the PCB. + +* The keyword "yes". This specification indicates that this component + self-defines its part, i.e., that the MCL section being parsed is both a + component definition and a part definition. + +* A part-ID defined by a part definition earlier in the MCL file. + +* A refdes of another component which appears earlier in the MCL file and self- + defines its part. + +Note that no forward references are allowed. + +Component definitions which refer to a part definition may override some of the +attributes in the latter, as long as such an override is physically meaningful. +(Overriding the value of a Panasonic ECJ-2VB1C104K cap to something other than +0.1 uF is not.) The population_option= attribute is normally set at the +component level rather than the part level, but other attributes may also be +overridden sometimes. For example, a dual position resistor (DPR) may be made +by taking a standard SMT resistor part (which would contain a footprint= +attribute for its normal two-pad footprint) and overriding its footprint to +a DPR footprint with 3 pads. + +Socket parts + +If a component is to be socketed, the socket part should have its own part +definition with a part-ID assigned and should be referenced via the socket= +attribute.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/doc/netlisting.txt Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,256 @@ +How uEDA tracks electrical interconnect (netlist) information + +Whereas the MCL (see mcldoc.txt) is the authoritative source of information +about all components making up a board design, information about the way they +are interconnected is stored in the schematic sheets (.usch files) in the +language described in uschemlang.txt. Electrical connections are declared by +way of assigning component pins to named or unnamed nets and may or may not be +represented graphically. The following two constructs in the uschem language +connect component pins to nets: + +* Net and GraphNet objects +* PinToNet decorations on component instance objects + +Whichever method is used (see uschemlang.txt for the syntax details), the +declaration of an electrical connection effectively consists of the following +3 parts: + +* Identification of the component involved; +* Identification of which pin to connect; +* The name of the net. (Net and GraphNet objects can create unnamed nets - + those connect together everything listed in the respective object, but + nothing else can connect to such nets.) + +While it's possible for the component identification to be equal to the refdes +as given in the MCL and for the pin identification to be the "raw" pin number, +uEDA provides two mechanisms that allow the interconnect information to be +entered in a slightly more high-level form: component instances and pinout +mapping. + +Component instances + +In uEDA a component instance is essentially a reference from a schematic sheet +to a component in the MCL. In a graphical schematic each component instance +would normally be represented by a graphical symbol, and all net connections +made in schematic sheets actually refer to component instances rather than to +MCL components directly. + +For trivial components like resistors and capacitors as well as some simple +ICs there is normally only one instance per component, hence the component in +the MCL and the instance in a .usch sheet are one and the same for all practical +purposes. However, for many of the more complex components it is generally +desirable to break the component up into multiple sections (which may be +identical or heterogeneous) represented separately in the schematic source code +for the design. That's what the component instances in uEDA are for. + +In the case when there are multiple component instances referring to the same +component, these instances may appear either in the same schematic sheet or in +different sheets. If a given schematic sheet contains only one instance of a +given MCL component, regardless of whether or not there are other instances for +the same component in other sheets, the instance name may be equal to the refdes +of the component - that's what happens when the user doesn't make use of the +component instance mechanism. However, if a single schematic sheet contains +more than one instance for a given component, there needs to be a way to +distinguish between them. + +When uEDA tools process a uschem sheet and match it to the MCL, the following +algorithm is used to match component instances to components: + +1. All component instance names appearing in a given schematic sheet are + required to be unique. +2. Each component instance name is stripped of any trailing lowercase letters to + obtain the corresponding refdes. +3. Each refdes is looked up in the MCL - if not found, that is an error. + +Thus if you need to put multiple instances for a given component in a single +schematic sheet, give each a unique name consisting of the refdes with a unique +all-lowercase suffix appended to it. + +Pinout mapping + +uEDA allows one to use two different alphanumeric strings to identify the +individual pins of a component: pin name and pin number. Both are arbitrary +alphanumeric strings (actually strings of any printable ASCII characters subject +only to common sense limitations); the pin number string doesn't have to be +purely numeric. (For example, PGA and BGA packages normally use alphanumeric +pin numbers.) + +Pin numbers are what appears in the final netlist output from uschem-netlist(1), +and they may also be used in the schematic source code. If the source only uses +pin numbers for a given component, then there is no need for uEDA to know the +pinout of that component. However, uEDA also allows one to specify the pinout +mapping for a component and to use pin names instead of pin numbers. + +Pinouts are specified in dedicated pinout mapping files and brought into the +design via pinout= attributes in the MCL. Pinout mapping files use a very +straightforward format: each pin mapping is given on a separate line; each such +line consists of two fields separated by tabs or spaces: the left field is the +pin name and the right field is the pin number. Comments are marked by '#'; +all blank lines and comment lines are ignored. Any additional fields past the +pin number are currently ignored as well, but this behavior should not be relied +upon; any such line-appended comments should begin with a '#' character. + +The name of the pinout mapping file specified in the pinout= attribute is only +the base filename, not a pathname. uschem-netlist and uschem-print (the only +two programs in the uEDA suite that need pinout mappings) locate pinout mapping +files using the same mechanism that is used to locate graphical symbol files - +see uschem-netlist(1) and uschem-print(1). + +In addition to making the schematic source code more readable, pinout mappings +make it easy to support components that come in several different packages with +different physical pin numbers for the same logical functions. It is no longer +necessary to create multiple versions of the same graphical symbols with +different pin numbers embedded inside or to edit pin references in Net objects; +instead all those references can now be made by the logical pin name. If a +decision is made to change to a different package with a different pinout, only +the pinout= attribute in the MCL entry for the respective component needs to be +changed - at the same time when you change the manufacturer_part_number= and +footprint= attributes. + +By the same token it is no longer necessary to create special PCB footprints +with logical pin names embedded in them where pin number strings normally go: +instead one can take the natural approach of having footprints identify pins or +pads by their physical position, having schematics and symbols refer to pins by +their logical function only and using pinout mapping files to bridge the gap. +The pinout mapping feature is one of uEDA's main advantages over gEDA. + +Slotting + +The concept of slotting (and the term) originates in gEDA, but uEDA implements +it in a very different manner. uEDA's approach to slotting combines component +instances with pinout mapping in a special way. But first, what is slotting? + +Suppose that you have a physical component (typically an IC) that consists of +multiple identical logical blocks such that each of those blocks should be +treated as a separate device in the schematic source code. 74xx logic ICs are +a classic example. When one needs to describe the use of such a component in a +design, it is normally desirable to represent each slot as its own component +instance and furthermore to do it in such a way that one doesn't have to decide +upfront which slot will be used for what, allowing slots to be reassigned with +ease. + +In uEDA this feat is accomplished by combining component instances with pinout +mapping. When each slot is declared as a component instance, all connections +to it are made by logical names only: for example, a NAND gate that is 1/4th of +a 7400 would have connections made to A, B and Y rather than to specific pin +numbers. So far, so good. But how would the tools know whether A for example +should be mapped to pin 1, 4, 9 or 12? That is where the slot= attribute comes +in. It is one of the few attributes defined in the component instance +declaration (Component object) in a schematic sheet rather than in the MCL. +When uEDA tools map a pin name to a pin number for a component instance that has +the slot= attribute defined, the value of this attribute is appended to the pin +name after a colon, e.g., if the pin name is A and slot=1, the pin name looked +up in the pinout mapping table will be A:1. The pinout for a 7400 quad NAND +gate looks like this: + +#pin name pin number +A:1 1 +B:1 2 +Y:1 3 +A:2 4 +B:2 5 +Y:2 6 +GND 7 +Y:3 8 +A:3 9 +B:3 10 +Y:4 11 +A:4 12 +B:4 13 +Vcc 14 + +Note the GND and Vcc pins which are not slotted. It is perfectly legitimate to +have some component instances which have the slot= attribute selecting one of +the logic slots, yet have other component instances referring to the same +component (e.g., for the power pins) without slotting. + +The following pinout for an SN75LBC784 EIA-423 transceiver is a more complicated +example of heterogeneous slotting: + +#pin name pin number +Drvr_In:3 1 +Rcvr_Out:3 2 +BIAS1 3 +Drvr_In:4 4 +Rcvr_Out:4 5 +BIAS2 6 +Vss 7 +GND 8 +Rcvr_In_N:4 9 +Drvr_Out:4 10 +Rcvr_In_N:3 11 +Drvr_Out:3 12 +Rcvr_In_P:3 13 +Rcvr_In_P:4 14 +Rcvr_In_P:1 15 +Rcvr_In_P:2 16 +Rcvr_In_N:2 17 +Drvr_Out:2 18 +Rcvr_In_N:1 19 +Drvr_Out:1 20 +Vdd 21 +Rws 22 +Drvr_In:1 23 +Rcvr_Out:1 24 +BIAS3 25 +Drvr_In:2 26 +Rcvr_Out:2 27 +BIAS4 28 + +This IC has 4 driver sections, 4 receiver sections and a set of common pins. +The pinout file given above allows it to be represented schematically using a +separate component instance for each driver section (with slotting), a separate +set of component instances for the receiver sections (an independent set of +slots) and one or more non-slotted component instances for the common pins. + +It is also worth noting that slot names (the value of the slot= attribute) are +not restricted to numbers only and may in fact be arbitrary ASCII strings. For +example, it would be sensible to define the pinout for a bicolor LED with slots +named "red" and "green", having complete pin names such as A:green and C:red +with connections being made to just A and C on the proper instances. + +Netlist generation + +When uschem-netlist processes a set of schematic sheets and an MCL to compile a +complete netlist, it first resolves all pin names (with or without slots) to +physical pin numbers and tracks the connection information at the component +level, i.e., the information is effectively moved up from the instance level at +which it is specified in the schematic source code to the component level. The +netlist data structures constructed by uschem-netlist maintain a hard +requirement that every physical pin of every component listed in the MCL be +either connected to exactly one net or left unconnected; thus any attempt to +connect the same physical pin to more than one net will be detected and flagged +as an error regardless of how each connection was specified in the source code. + +One may use the NoConnect decoration on a component instance object to declare +explicitly that a given pin shall be left unconnected. uschem-netlist will note +such declarations and flag an error if an attempt is made anywhere else in the +source code to connect the same physical pin to some net. + +Differences from gEDA + +The main difference between gEDA and uEDA with regard to netlisting is that in +uEDA graphical elements such as symbols and net lines do not create electrical +connections, they merely illustrate them. The uschem language (documented fully +in uschemlang.txt) is designed so that the graphical information and the +electrical interconnect information are mostly orthogonal. The electrical +interconnect information must be fully specified in the .usch files, not +inferred from symbol files, to the point that the latter files are not needed +for netlist generation and are not read by uschem-netlist at all. Thus gEDA +constructs such as auto-connected hidden power pins have no place in uEDA; the +closest one can get to that would be to insert a non-graphical component +instance with the necessary net connections into an otherwise graphical +schematic sheet. + +By a similar token the graphical symbols for power rails and such do not cause +a net to be connected to a rail, instead that connection is made by having the +proper netname set on the GraphNet object in the .usch file; the symbols merely +illustrate it graphically for those looking at the printout rather than the +source code. + +The downside with uEDA's approach is of course the very real possibility that +the netlist and the graphics will get out of sync, i.e., that the set of +electrical interconnections mentally inferred by someone looking at the +graphical schematic printout will differ from the set of interconnections +embodied in the source code processed by uEDA tools. See drc.txt for the +discussion of how uEDA addresses this problem.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/doc/overview.txt Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,117 @@ +Welcome to uEDA, an EDA suite for UNIX! +(for board level design) + +The uEDA project has been inspired by gEDA (http://geda.seul.org/) and intends +to do for the UNIX culture what gEDA has done for the GNU/Linux culture. + +First a disclaimer is in order. Different people write Free Software based on +different motivations. Like most Free Software written by Michael Sokolov, +uEDA is based on the "scratching a personal itch" development model. In other +words, I have written the software to satisfy my own internal need, and I +don't really care if you like it or not. Please keep this observation in mind +as you discover that it lacks some feature you need or want, or that its flow +is not to your liking. I have written it to satisfy *my* needs. I could have +written it for myself and never released it, but I believe in sharing and +letting others have what I have (though whether they like it or not is not my +concern). So there you have it. + +uEDA has been written by a hard-core UNIX programmer (as in real UNIX in 4 +capitals running on Big Iron, not the cheap modern crap), and is designed to +allow one to design hardware using not only a UNIX host environment, but also +the intellectual creation flow model associated with the UNIX culture, one that +revolves around the concepts of source code files, generated files and +Makefiles. I won't explain these concepts here; if they are foreign to you, +uEDA is not for you. + +Note my choice of words: "the intellectual creation flow model" of the UNIX +culture, rather than "the UNIX programming model". I fully acknowledge that +hardware engineering is very different from SW eng, and uEDA does not try to +"make hardware like software". However, the UNIX culture's intellectual +creation flow model has already been extended many times to various intellectual +products other than software. Consider for example an author writing a book in +troff. The troff source files take the place of C source code, PostScript or +other typesetter files for the print house take the place of the executable +binary, and a Makefile is used to drive the flow. The author edits the book +source files with vi and regenerates the generated files on each iteration by +running 'make'. It isn't software, but the intellectual creation flow is +virtually identical. uEDA applies the same model to hardware design. + +So what is the source code for hardware, and what is the final product that +should be generated by 'make all'? Well, the ultimate final product is the +physical board which you can hold in your hand, but the most "final" product +that can be made on a computer would be a set of gerber files for PCB +fabrication, a bill of materials (BOM) for the purchasing or other procurement +of parts, and a set of assembly instructions to be handed to the assembly line +workers who populate the parts on the board. The starting source code would +be the schematic design. + +The ultimate UNIX-model EDA suite would thus be one that can generate all final +manufacturing files from the schematic source code with a single 'make' command. +uEDA is almost there, except for the layout step. + +The problem is that even with the best EDA technology PCB layout still involves +considerable human effort, and is thus not something that can be done by a batch +program that works from stdin to stdout. Therefore, the PCB layout file is +subject to human editing and is not just an intermediate file between schematics +and gerbers like a .o file in the software compilation flow. + +The uEDA solution is to view the job of designing a board as two separate +intellectual creation jobs, each with its own UNIX-model Makefile-driven flow. +These two jobs are the design and the layout. uEDA addresses the design. The +uEDA suite does not really get involved in the layout, but is designed with the +assumption that the layout will be done with the free & open source PCB program +(http://pcb.sourceforge.net/). The two are connected by the "pre-layout" step +described in prelayout.txt. + +(Note that such separation of the design and layout jobs is additionally + supported by the fact that in many engineering companies these jobs are done + by different people.) + +In the design phase addressed by uEDA, the source code is the set of schematic +sources and the Master Component List (MCL), a human-edited text file documented +in mcldoc.txt. The products that can be generated from these sources with a +Makefile are: + +* Printable schematics (PostScript or PDF) for documentation; +* A set of "pre-layout materials" for handing to the PCB layout person; +* Bill of Materials (BOM) in different formats for part procurement, for + assembly and for quick reference. + +In the layout phase the .pcb that is both read and written by the PCB GUI is the +source code, and pcb can be invoked from the command line without the GUI to +generate gerbers, PostScript prints of the layout and other product files from +it; those generations can be codified in a Makefile, once again creating the +traditional UNIX flow. + +Design source code structure + +The source code for a board design in uEDA consists of 3 major parts: + +* Information about all components on the board; +* Electrical interconnect information: how these components are interconnected + with nets; +* Graphical information used to construct PostScript prints of the schematic + sheets. + +The core philosophy of uEDA is that these 3 kinds of information should be kept +as orthogonal as possible. Component information is stored in the Master +Component List (MCL) documented in mcldoc.txt, whereas the interconnect and +graphical schematic information is stored in the schematic sheets (.usch files) +documented in uschemlang.txt. Although the electrical interconnect and +graphical information are stored together, the uschem language is designed to +provide a high degree of orthogonality between the two. Schematic sheets can +be either graphical or non-graphical. + +Further reading: + +bom_model.txt Describes the uEDA approach to BOM handling +drc.txt Describes the means for helping ensure a match between the + actual electrical interconnect and the graphical representation +graphsyms.txt Information about graphical symbols used on schematic sheets +mcldoc.txt Master Component List document +netlisting.txt Describes uEDA's handling of netlist information +prelayout.txt Describes what I mean by "pre-layout" +psfeatures.txt Describes the features available in the PostScript prints of + schematic sheets made with uschem-print(1) +uschemlang.txt uschem language document +*.1 Man pages for all uEDA utilities
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/doc/prelayout.txt Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,110 @@ +Pre-layout in uEDA + +If one implements the common division of labor in which the conceptual/schematic +hardware design and the PCB layout are done by different people, in what form +is the design passed from the original designer to the PCB layout contractor? + +The common input to the PCB layout step is the netlist. However, the netlist is +actually not enough. The netlist specifies all interconnections among +components in the design, but what about the components themselves? In what +form is the list of components passed from design to layout? The answer depends +on exactly how the division of labor is implemented. + +In some organisations the designer may specify standard components by value or +device nomenclature and let the PCB layout person pick the footprints. Or the +designer may specify the footprints verbally ("this resistor is an 0805, this +tantalum cap is size C, this logic IC is SMT, that one is a DIP..."), but still +leave it to the layout person to actually draw the footprints in the PCB layout +package of his/her choice. + +However, if the hardware design is being done by a non-profit organisation like +the International Free Computing Task Force (the application scenario for which +uEDA is designed), it is often the case that the conceptual/schematic hardware +designer is a volunteer whereas the PCB layout labor has to be hired for money. +In this scenario it is advantageous to save cost by having the designer do as +much pre-layout work as possible, including the scripted generation of all PCB +land patterns, leaving only the actual layout (the placement of the supplied +footprints on the PCB and trace routing) to the costly hired labor. + +An additional consideration is that in order to keep our designs strictly free +and open source from start to finish, we don't want the layout to be done in +some proprietary package and we insist instead that it be done with the free +and open source PCB program (http://pcb.sourceforge.net/). Or more precisely, +we insist on the PCB layout file format. + +These two considerations combine to suggest that we generate the PCB footprints +for all components in the design in the PCB format and hand them to whoever we +hire to do the layout. This is what is called pre-layout in uEDA. + +Whereas PCB layout is inherently a graphical/visual task and thus seriously +incompatible with the world view of the uEDA author, the footprint generation +for PCB happens to be very compatible with the UNIX culture-based text-based +scripted flow embraced by uEDA. The PCB project's original footprint library +is actually M4 code that generates footprints algorithmically on the fly! + +The pre-layout function of uEDA requires the use of the IFCTF part library. +Among other things it contains a version of the M4 footprint library from PCB +ported from GNU M4 to the original UNIX M4. The IFCTF part library is +maintained in the IFCTF CVS repository and may be checked out with: + +$ cvs -d :pserver:anoncvs@ifctfvax.Harhan.ORG:/fs1/IFCTF-cvs co ifctf-part-lib + +uEDA expects it to be installed in /usr/local/eda/ifctf-part-lib + +The pre-layout function of uEDA works as follows: + +1. Each component needs to have a footprint= attribute defined in the MCL. + It works exactly like the footprint= attribute in gEDA with the gsch2pcb + flow. + +2. To generate the PCB footprints for your design, run the following pipeline: + +ueda-getfps | ueda-runm4 > elements.pcb + +ueda-getfps(1) reads the MCL and emits a set of M4 macro calls to generate all +of the footprints, and ueda-runm4(1) runs m4(1) on the IFCTF part library. +The output of the pipeline is a concatenated set of footprints for the board +with the name field (refdes) filled in correctly in each. If the -h option is +given to ueda-getfps, the concatenated set of footprints will be preceded by a +blank PCB template (the same one provided by PCB itself when starting a new +layout) and the resulting elements.pcb will be a valid layout PCB that can be +loaded into PCB to start the layout job. + +Alternatively, ueda-cutelements(1) may be used to cut the concatenated output +from ueda-getfps | ueda-runm4 into one file per element. It should be run in +an empty directory and the files thus produced are named after the component +reference designators. + +The uEDA footprint generation mechanism is designed so that the generation of +all footprints at once concatenated into a single PCB file is native whereas +producing single elements is secondary because the way PCB's M4 library is +designed makes this approach much more efficient, especially when using the +original UNIX M4 rather than GNU M4. + +File elements + +In addition to the M4-based original PCB footprint library which has been +incorporated into the IFCTF part library, there are other popular footprint +libraries which are simple collections of pregenerated elements, one per file. +They are called file element libraries, and there is a very popular and very +useful one maintained by John Luciani. + +uEDA supports file element libraries in addition to the main M4-based IFCTF +part library, but the process always goes through M4. + +ueda-getfps(1) normally generates a make_footprint() M4 macro call for every +component. This macro looks for the requested footprint in the M4 library and +if none is found, invokes the ueda-instfileelem(1) utility to try to find it in +the file element libraries and instantiate it from there. +See the ueda-instfileelem(1) man page for how to locate the file element +libraries. + +Some file element libraries (particularly John Luciani's) use footprint names +which would confuse M4. To get around this problem, the footprint= attribute +in the MCL may be specified as follows: + + footprint=file:Long-weird_footprint-name + +This syntax tells ueda-getfps(1) to generate a make_footprint_file() M4 macro +call instead of make_footprint(). The former invokes ueda-instfileelem(1) +immediately without trying to look in the M4 library first.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/doc/uschemlang.txt Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,132 @@ +uschem language for schematic sheets + +uschem is the component of uEDA that deals with the graphical or non-graphical +schematic sheets as opposed to the MCL. These schematic sheets are ASCII text +files (conventional suffix is .usch, although it isn't hard-coded into any uEDA +tools) in a special language defined in this document. + +At the high level each schematic sheet may be either graphical or non-graphical +and consists of a set of objects that embody electrical and/or graphical +information. Component objects (component instances) provide a link between the +schematic sheet and the MCL, Net and GraphNet objects declare electrical +interconnections (see netlisting.txt), GraphBlock objects serve as containers +for purely graphical elements, and a few other object types will be explained in +detail later. Most object types accept decorations, which are the uschem +syntactic term for information elements that are not objects in themselves, but +are attached to a particular object. + +At the low level the uschem syntax is based on the same principle as C and many +other languages used in the UNIX world: the source file is treated as consisting +of tokens which are either self-delimiting or delimited by white space; with a +few exceptions all white space (spaces, tabs and newlines) is treated the same, +i.e., line boundaries have no special significance to the parser. The tokens +which make up the language consist of: + +* ASCII characters (),;={} are self-delimiting tokens. + +* A quoted string (enclosed in double quotes '"') is a quoted-string token. + To include a '"' character in a quoted string, escape it as '\"'; to include + a backslash '\', escape it as '\\'. + +* The following tokens are delimited by white space, by any of the self- + delimiting tokens listed above, or by '%' comments (see below): + + + Keywords + + Numbers (decimal integers) + + Any other strings (unquoted-string tokens) + +Wherever the syntax calls for a string giving some user data, either a quoted or +an unquoted string may be given; quoted strings are required only if they +contain special characters. Keywords and numbers must not be quoted. + +Comments + +The uschem language supports two kinds of comments. The first kind are +PostScript-style comments. These comments are introduced by a '%' character and +continue to the end of the line (one of the few places in the uschem language +where newlines differ from other white space). This comment style is very +convenient, but they suffer from one serious problem: if a schematic sheet is +processed by a program that parses the original, does some transformations to +it, and writes out a new .usch file (uschem-rewrite(1) or the future graphical +schematic editor), PostScript-style comments will be lost because they are not +structured and thus cannot survive the parsing process. + +The other kind of comments are structured comments. These take the form of +Comment objects or Comment decorations on other objects; the body of the comment +takes the form of a string token (usually quoted). Because they take their +proper place in the uschem language of objects and decorations, such structured +comments can survive processing by tools that manipulate schematic sheets at +that level. + +Graphics model + +The graphical aspects of uschem schematics have been borrowed heavily from +gschem, the schematic capture tool from the gEDA project - the latter is the +closest thing to a mainstream EDA package that has ever been used by the author +of uEDA. All geometric dimensions for graphical elements on schematic sheets as +well as the dimensions of the sheets themselves are given in gschem units, and +most of the commonly used graphics primitives have also been copied from gschem. +Users wanting to make use of the graphical features of uschem need to be +familiar with gschem as these gschem-derived graphical features won't be +described here in detail. + +There is, however, one major difference between the graphics models of gschem +and uschem. gschem is a GUI application and its graphics primitives are +intended primarily for on-screen display and editing; gschem supports PostScript +output as an afterthought. uschem on the other hand is designed with the +philosophy that PostScript is the canonical and authoritative representation of +a graphical schematic sheet; whatever form is used to represent graphical +elements in the source code, the assumption is that they are all ultimately +destined to become PostScript. + +Graphical elements emitted into the PostScript output by uschem-print(1) come +from the following sources: + +* GraphBlock structures (objects or decorations) which are containers for purely + graphical elements in schematic sheets; + +* Graphical symbols pulled from the library to represent component instances as + well as for other purposes - see graphsyms.txt; + +* Text emitted by DisplayAttr and DisplayNetName decorations; + +* Lines drawn for GraphNet, NetLine and BusSeg objects. + +GraphBlock structures may be of two forms: GraphBlockG and GraphBlockPS. The +former contain gschem code, the latter contain PostScript code. PostScript is +the native form; gschem code is printed by turning it into PostScript, hence +GraphBlockPS can do everything that GraphBlockG can plus much more. GraphBlockG +should be considered a backward compatibility feature. A similar situation +exists with graphical symbols as described more fully in graphsyms.txt. + +See psfeatures.txt for the information you need to know in order to write +PostScript code for inclusion into GraphBlockPS structures or symbols. + +Coordinate system + +As already noted earlier, all graphical coordinates are given in gschem units. +Analogously to both gschem and PostScript default the origin of the coordinate +system is in the lower left corner; x coordinates increase to the right and y +coordinates increase upward. There is, however, one subtle difference between +gschem and uschem coordinate systems. In gschem schematic sheets the absolute +coordinates are essentially arbitrary and one needs to use a special titleblock +"component" to set the overall dimensions of the drawing sheet; the coordinates +that really matter then need to be calculated relative to the arbitrary ones of +that titleblock component. uschem has done away with such silliness and every +graphical schematic sheet in the uschem language begins with an explicit size +declaration. + +The sheet size declaration given at the beginning of a uschem sheet sets the +effective limits for the coordinate system, but it does not cause any border or +title block to be drawn. If such features are desired (they normally are), they +need to be embodied in a GraphBlock object. + +One gschem misfeature that has unfortunately been retained in uschem is the +fictitious nature of the drawing sizes. Using gschem and following the size +conventions set for its standard symbol library, one has to declare the drawing +as having size D (use title-D.sym) in order to make it reasonable for printing +in size B; this situation unfortunately remains in uschem. The sheet size +declaration merely establishes the size of the in-sheet coordinate system in the +fake gschem units, whereas the actual print size is given on the command line to +uschem-print(1). uschem's PostScript prolog code calculates and effects the +necessary scaling.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,14 @@ +CFLAGS= -O +LIBOBJS=filesearch.o hashmcl.o mclacc.o pinouts.o popopt.o readmcl.o util.o \ + xga.o + +all: libueda.a + +libueda.a: ${LIBOBJS} + ar rcu $@ ${LIBOBJS} + ranlib $@ + +clean: + rm -f *.[ao] a.out core errs + +install:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/filesearch.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,87 @@ +/* + * These routines implement searching for symbol and pinout files. + */ + +#include <sys/param.h> +#include <ctype.h> +#include <stdio.h> +#include <strings.h> + +extern char *copystr(); + +#define MAXDIRS 15 +static char *dirlist[MAXDIRS+1]; +static int ndirs; + +/* This var is global so that interested parties can grab and copy it */ +char sought_libfile_fullpath[MAXPATHLEN]; + +add_symfile_dir(dir) + char *dir; +{ + if (ndirs >= MAXDIRS) { + fprintf(stderr, + "Too many symbol file search directories specified\n"); + exit(1); + } + dirlist[ndirs++] = dir; +} + +set_default_sympath() +{ + register FILE *f; + char line[MAXPATHLEN]; + register char *cp, *np; + int lineno; + + if (ndirs) + return; + f = fopen("sympath", "r"); + if (!f) + return; + for (lineno = 1; fgets(line, sizeof line, f); lineno++) { + for (cp = line; isspace(*cp); cp++) + ; + if (*cp == '\0' || *cp == '#') + continue; + if (!isgraph(*cp)) { +inv: fprintf(stderr, + "sympath: line %d: invalid syntax (one directory per line expected)\n", + lineno); + exit(1); + } + for (np = cp; isgraph(*cp); cp++) + ; + if (isspace(*cp)) + *cp++ = '\0'; + while (isspace(*cp)) + cp++; + if (*cp) + goto inv; + if (ndirs >= MAXDIRS) { + fprintf(stderr, + "sympath: too many symbol file search directories specified\n"); + exit(1); + } + dirlist[ndirs++] = copystr(np); + } + fclose(f); +} + +FILE * +find_symlib_file(basename, suffix) + char *basename, *suffix; +{ + register int i; + register FILE *f; + + for (i = 0; dirlist[i]; i++) { + sprintf(sought_libfile_fullpath, "%s/%s", dirlist[i], basename); + if (suffix) + strcat(sought_libfile_fullpath, suffix); + f = fopen(sought_libfile_fullpath, "r"); + if (f) + return(f); + } + return(NULL); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/hashmcl.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,90 @@ +/* + * MCL hash table logic + * + * This module implements construction and use of a hash table indexing + * the MCL components by refdes. It facilitates checking the MCL for + * duplicate refdes errors and fast component lookups. + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "mcl.h" + +extern struct component components[]; +extern int ncomponents; + +#define HASH_SIZE 1103 + +static struct component *mclhashtab[HASH_SIZE]; + +static int +hash_refdes(str) + char *str; +{ + register u_long accum; + register char *cp; + register int c; + + for (cp = str, accum = 0; c = *cp; cp++) { + accum <<= 4; + accum |= c & 0x0F; + } + return(accum % HASH_SIZE); +} + +hash_MCL() +{ + register struct component *comp, *hc, **hcp; + int i; + int errflag = 0, errstat = 0; + + for (comp = components, i = 0; i < ncomponents; comp++, i++) { + hcp = mclhashtab + hash_refdes(comp->name); + for (; hc = *hcp; hcp = &hc->nextinhash) + if (!strcmp(comp->name, hc->name)) { + fprintf(stderr, + "%s: duplicate refdes in the MCL\n", + comp->name); + errflag = 1; + break; + } + if (errflag) { + errflag = 0; + errstat = -1; + } else + *hcp = comp; + } + if (errstat) + exit(1); +} + +report_mclhash_quality() +{ + int maxchain; + register int hb, curchain; + register struct component *comp; + + for (hb = 0, maxchain = 0; hb < HASH_SIZE; hb++) { + for (comp = mclhashtab[hb], curchain = 0; comp; + comp = comp->nextinhash) + curchain++; + if (curchain > maxchain) + maxchain = curchain; + } + printf("Total components: %d\n", ncomponents); + printf("Longest hash chain: %d\n", maxchain); +} + +struct component * +find_comp_by_refdes(refdes) + register char *refdes; +{ + register struct component *comp; + + for (comp = mclhashtab[hash_refdes(refdes)]; comp; + comp = comp->nextinhash) + if (!strcmp(comp->name, refdes)) + return(comp); + return(NULL); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/mcl.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,15 @@ +/* Definitions for the data structures derived from the MCL */ + +struct attrib { + char *name; + char *value; +}; + +struct component { + char *name; /* refdes or partdef */ + struct attrib *attrs; + int nattrs; + struct component *partdef; + struct pinout_def *pinout; + struct component *nextinhash; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/mclacc.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,60 @@ +/* + * These are the libueda routines for accessing the parsed MCL. + */ + +#include <stdio.h> +#include <strings.h> +#include "mcl.h" + +extern struct component components[], partdefs[]; +extern int ncomponents, npartdefs; + +struct component * +find_partdef_by_name(partname) + register char *partname; +{ + register struct component *part; + register int i; + + for (part = partdefs, i = 0; i < npartdefs; part++, i++) + if (!strcmp(part->name, partname)) + return(part); + return(NULL); +} + +char * +get_comp_attr(comp, attrname) + struct component *comp; + char *attrname; +{ + register struct attrib *attr; + register int i; + + for (; comp; comp = comp->partdef) { + attr = comp->attrs; + for (i = 0; i < comp->nattrs; attr++, i++) + if (!strcmp(attr->name, attrname)) + return(attr->value); + if (comp->partdef == comp) + break; + } + return(NULL); +} + +char * +get_comp_multiattr(comp, attrname, cntp) + struct component *comp; + char *attrname; + int *cntp; +{ + register struct attrib *attrs; + register int i; + + attrs = comp->attrs; + for (i = *cntp; i < comp->nattrs; i++) + if (!strcmp(attrs[i].name, attrname)) { + *cntp = i + 1; + return(attrs[i].value); + } + return(NULL); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/pinouts.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,153 @@ +/* + * Pinout handling functions + */ + +#include <ctype.h> +#include <stdio.h> +#include <strings.h> +#include "mcl.h" +#include "pinouts.h" + +extern char *malloc(); +extern char *copystr(); + +extern struct component components[]; +extern int ncomponents; + +extern char *get_comp_attr(); +extern FILE *find_symlib_file(); +extern char sought_libfile_fullpath[]; + +struct pinout_def * +read_pinout_file(filename) + char *filename; +{ + FILE *f; + char line[1024]; + int lineno; + struct pinout_def *head, **tailp; + register struct pinout_def *pin; + register char *cp; + char *pinname, *pinnumber; + + f = find_symlib_file(filename, NULL); + if (!f) { + fprintf(stderr, "Cannot find pinout file %s\n", filename); + exit(1); + } + + head = NULL; + tailp = &head; + for (lineno = 1; fgets(line, sizeof line, f); lineno++) { + for (cp = line; isspace(*cp); cp++) + ; + if (*cp == '\0' || *cp == '#') + continue; + if (!isgraph(*cp)) { +syntaxerr: fprintf(stderr, "%s: line %d: syntax error\n", + sought_libfile_fullpath, lineno); + exit(1); + } + for (pinname = cp; isgraph(*cp); cp++) + ; + if (!isspace(*cp)) + goto syntaxerr; + *cp++ = '\0'; + while (isspace(*cp)) + cp++; + if (!isgraph(*cp) || *cp == '#') + goto syntaxerr; + for (pinnumber = cp; isgraph(*cp); cp++) + ; + if (isspace(*cp)) + *cp++ = '\0'; + else if (*cp) + goto syntaxerr; + pin = (struct pinout_def *) malloc(sizeof(struct pinout_def)); + if (!pin) { + perror("malloc"); + exit(1); + } + pin->pinname = copystr(pinname); + pin->pinnumber = copystr(pinnumber); + pin->next = NULL; + *tailp = pin; + tailp = &pin->next; + } + fclose(f); + + if (!head) { + fprintf(stderr, "%s: empty pinout file\n", + sought_libfile_fullpath); + exit(1); + } + return(head); +} + +/* + * We implement an optimisation: when we read all pinouts into core in + * read_pinouts(), we cache them by name so that we don't have to re-read + * and re-parse the same pinout files multiple times for multiple components. + * The caching array is local to read_pinouts() and limited by MAX_PINOUTS. + * If that limit is exceeded, caching will stop but we'll continue reading + * pinouts, i.e., only the optimisation will be lost. + */ + +#define MAX_PINOUTS 128 + +read_pinouts() +{ + char *pinout_file_names[MAX_PINOUTS]; + struct pinout_def *parsed_pinouts[MAX_PINOUTS]; + int cached_pinouts, i; + register struct component *comp; + register char *pinout_file; + register struct pinout_def *parsed_pinout; + register int j; + + for (cached_pinouts = i = 0, comp = components; i < ncomponents; + comp++, i++) { + pinout_file = get_comp_attr(comp, "pinout"); + if (!pinout_file) + continue; + for (j = 0; j < cached_pinouts; j++) + if (!strcmp(pinout_file_names[j], pinout_file)) { + comp->pinout = parsed_pinouts[j]; + continue; + } + parsed_pinout = read_pinout_file(pinout_file); + comp->pinout = parsed_pinout; + if (cached_pinouts < MAX_PINOUTS) { + pinout_file_names[cached_pinouts] = pinout_file; + parsed_pinouts[cached_pinouts] = parsed_pinout; + cached_pinouts++; + } + } + return(0); +} + +char * +pinname_to_pinnumber(comp, pinname, slot) + struct component *comp; + char *pinname, *slot; +{ + char strbuf[512]; + register char *searchkey; + register struct pinout_def *pin; + + pin = comp->pinout; + if (!pin) { + fprintf(stderr, "%s has no pinout\n", comp->name); + return(NULL); + } + if (slot) { + sprintf(strbuf, "%s:%s", pinname, slot); + searchkey = strbuf; + } else + searchkey = pinname; + for (; pin; pin = pin->next) + if (!strcmp(pin->pinname, searchkey)) + return(pin->pinnumber); + fprintf(stderr, "%s: no pin named %s\n", comp->name, searchkey); + return(NULL); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/pinouts.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,7 @@ +/* Pinout data structure */ + +struct pinout_def { + char *pinname; + char *pinnumber; + struct pinout_def *next; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/popopt.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,68 @@ +/* + * These are the libueda routines for handling population options. + */ + +#include <stdio.h> +#include <ctype.h> +#include <strings.h> +#include "mcl.h" + +extern char *get_comp_attr(); + +#define MAX_POPOPT_LIST 10 +static int popopt_list[MAX_POPOPT_LIST], npopopt = 1; +static int all_popopt; + +set_popopt_list(arg) + char *arg; +{ + register char *cp, *np; + register int i; + + if (!strcmp(arg, "all")) { + all_popopt = 1; + return; + } + for (cp = arg, i = 0; *cp; ) { + if (*cp == ',') { + cp++; + continue; + } + if (!isdigit(*cp)) { + fprintf(stderr, + "%s: invalid population option specification\n", + arg); + exit(1); + } + for (np = cp; isdigit(*cp); cp++) + ; + if (i >= MAX_POPOPT_LIST) { + fprintf(stderr, + "%s: too many population options listed\n", + arg); + exit(1); + } + popopt_list[i++] = atoi(np); + } + npopopt = i; +} + +check_component_popopt(comp) + struct component *comp; +{ + register char *popopt_string; + register int popopt, i; + + if (all_popopt) + return(1); + popopt_string = get_comp_attr(comp, "population_option"); + if (!popopt_string) + popopt_string = "0"; + if (!strcmp(popopt_string, "NO")) + return(0); + popopt = atoi(popopt_string); + for (i = 0; i < npopopt; i++) + if (popopt_list[i] == popopt) + return(1); + return(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/readmcl.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,260 @@ +/* + * This is the MCL parser for the uEDA suite. + */ + +#include <stdio.h> +#include <ctype.h> +#include <strings.h> +#include "mcl.h" + +extern char *copystr(); + +#define MAX_COMPS 1024 +#define MAX_PARTDEFS 128 +#define MAX_ATTRS 2048 +#define MAX_REFDES_ON_LINE 16 + +char *MCLfile = "MCL"; + +/* the following vars capture the distilled output of the parser */ +struct component components[MAX_COMPS], partdefs[MAX_PARTDEFS]; +int ncomponents, npartdefs; +static struct attrib attrs[MAX_ATTRS]; +static int nattrs; + +/* the following static vars are used only in the reading & parsing process */ +static FILE *mclf; +static char line[1024]; /* size arbitrary, sizeof used in the code */ +static int lineno; + +static struct component *curcomp; +static char *curcomp_refdes[MAX_REFDES_ON_LINE]; +static int curcomp_nrefdes; + +read_MCL() +{ + register char *cp, *name, *value; + + mclf = fopen(MCLfile, "r"); + if (!mclf) { + perror(MCLfile); + exit(1); + } + + for (lineno = 0, curcomp = NULL; getline(); ) { + /* ignore blank lines and comments */ + if (line[0] == '\0' || line[0] == '#') + continue; + if (!strncmp(line, "part", 4) && isspace(line[4])) { + finish_component(); + setup_partdef(line + 5); + } else if (!isspace(line[0])) { /* refdes */ + finish_component(); + parse_refdes_list(); + if (ncomponents >= MAX_COMPS) { + fprintf(stderr, + "%s: line %d: too many components\n", + MCLfile, lineno); + exit(1); + } + curcomp = components + ncomponents; + curcomp->name = curcomp_refdes[0]; + curcomp->attrs = attrs + nattrs; + curcomp->nattrs = 0; + ncomponents++; + } else { /* attribute */ + for (cp = line; isspace(*cp); cp++) + ; + name = cp; + cp = index(cp, '='); + if (!cp) { +invattr: fprintf(stderr, + "%s: line %d: invalid attribute line\n", + MCLfile, lineno); + exit(1); + } + *cp = '\0'; + value = cp + 1; + if (name[0] == '\0') + goto invattr; + if (!curcomp) { + fprintf(stderr, + "%s: line %d: attribute listed without a component\n", + MCLfile, lineno); + exit(1); + } + if (value[0] == '\0') { + fprintf(stderr, + "%s: line %d: attribute must have a value\n", + MCLfile, lineno); + exit(1); + } + if (nattrs >= MAX_ATTRS) { + fprintf(stderr, + "%s: line %d: too many attributes\n", + MCLfile, lineno); + exit(1); + } + attrs[nattrs].name = copystr(name); + attrs[nattrs].value = copystr(value); + nattrs++; + curcomp->nattrs++; + if (!strcmp(name, "part")) + handle_part_ref(value); + } + } + fclose(mclf); + finish_component(); +} + +static +setup_partdef(np) + register char *np; +{ + register char *cp; + + while (isspace(*np)) + np++; + cp = index(np, ':'); + if (!cp || cp == np || cp[1]) { + fprintf(stderr, "%s: line %d: invalid part definition\n", + MCLfile, lineno); + exit(1); + } + *cp = '\0'; + if (npartdefs >= MAX_PARTDEFS) { + fprintf(stderr, "%s: line %d: too many part definitions\n", + MCLfile, lineno); + exit(1); + } + curcomp = partdefs + npartdefs; + curcomp->name = copystr(np); + curcomp->attrs = attrs + nattrs; + curcomp->nattrs = 0; + npartdefs++; + curcomp_nrefdes = 0; +} + +static +parse_refdes_list() +{ + int i; + register char *cp, *np; + register int c; + + for (cp = line, i = 0; ; ) { + if (!isupper(*cp)) { +inv: fprintf(stderr, "%s: line %d: invalid refdes line\n", + MCLfile, lineno); + exit(1); + } + for (np = cp; isalnum(*cp); cp++) + ; + c = *cp; + if (c != ':' && c != ',') + goto inv; + *cp++ = '\0'; + curcomp_refdes[i++] = copystr(np); + if (c == ':') + break; + } + curcomp_nrefdes = i; + if (*cp) + goto inv; +} + +static +finish_component() +{ + extern char *get_comp_attr(); + + if (curcomp_nrefdes == 0) + return; /* nothing to do for part defs */ + if (!curcomp->partdef && + (get_comp_attr(curcomp, "manufacturer") && + get_comp_attr(curcomp, "manufacturer_part_number") || + get_comp_attr(curcomp, "bom_part_title"))) + curcomp->partdef = curcomp; /* self-defines part */ + if (curcomp_nrefdes > 1) + clone_component(); +} + +static +clone_component() +{ + register int i; + register struct component *newcomp; + + for (i = 1; i < curcomp_nrefdes; i++) { + if (ncomponents >= MAX_COMPS) { + fprintf(stderr, "%s: %s: too many components\n", + MCLfile, curcomp_refdes[i]); + exit(1); + } + newcomp = components + ncomponents; + bcopy(curcomp, newcomp, sizeof(struct component)); + newcomp->name = curcomp_refdes[i]; + ncomponents++; + } +} + +static +handle_part_ref(partname) + char *partname; +{ + register struct component *part; + register int i; + + if (curcomp_nrefdes == 0) { + fprintf(stderr, + "%s: line %d: can't use a part reference in a part definition!\n", + MCLfile, lineno); + exit(1); + } + if (!strcmp(partname, "none")) { + curcomp->partdef = NULL; + return; + } + if (!strcmp(partname, "yes")) { + curcomp->partdef = curcomp; /* self-defines the part */ + return; + } + for (part = partdefs, i = 0; i < npartdefs; part++, i++) + if (!strcmp(part->name, partname)) { +gotit: curcomp->partdef = part; + return; + } + /* can also refer to a previous component that self-defines a part */ + for (part = components, i = 0; i < ncomponents-1; part++, i++) + if (!strcmp(part->name, partname)) { + if (part->partdef == part) + goto gotit; + else { + fprintf(stderr, +"%s: line %d: can't use %s as a part because it doesn't define a part\n", + MCLfile, lineno, partname); + exit(1); + } + } + fprintf(stderr, "%s: line %d: part %s not defined\n", MCLfile, lineno, + partname); + exit(1); +} + +static +getline() +{ + register char *cp; + + if (fgets(line, sizeof line, mclf) == NULL) + return(0); + lineno++; + /* strip trailing comments and whitespace */ + cp = index(line, '#'); + if (!cp) + cp = index(line, '\0'); + while (cp > line && isspace(cp[-1])) + cp--; + *cp = '\0'; + return(1); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/util.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,37 @@ +/* + * Miscellaneous utility functions for libueda + */ + +#include <ctype.h> +#include <strings.h> + +extern char *malloc(); + +char * +copystr(src) + register char *src; +{ + register char *buf; + + buf = malloc(strlen(src) + 1); + if (!buf) { + perror("malloc"); + exit(1); + } + strcpy(buf, src); + return(buf); +} + +string_is_valid_decnum(str) + char *str; +{ + register char *cp = str; + + if (*cp == '-') + cp++; + if (!isdigit(*cp)) + return(0); + while (isdigit(*cp)) + cp++; + return(*cp == '\0'); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/xga.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,302 @@ +/* + * This module contains the function that implements the reading of PGA/BGA + * package description files and some related functions. + */ + +#include <ctype.h> +#include <stdio.h> +#include <strings.h> +#include "xga.h" + +extern char *malloc(); +extern char *copystr(); + +extern FILE *find_symlib_file(); +extern char sought_libfile_fullpath[]; + +parse_xga_pinnumber(desc, pinstr, parsed) + register struct grid_pkg_desc *desc; + register char *pinstr; + struct xga_parsed_pinnum *parsed; +{ + char *rowfind; + int col; + + if (!isupper(pinstr[0]) || !isdigit(pinstr[1])) + return(-1); + rowfind = index(desc->row_letters, pinstr[0]); + if (!rowfind) + return(-1); + if (!string_is_valid_decnum(pinstr + 1)) + return(-1); + col = atoi(pinstr + 1); + if (col < 1 || col > desc->ncolumns) + return(-1); + parsed->row_0based = rowfind - desc->row_letters; + parsed->col_0based = col - 1; + return(0); +} + +static void +check_complete(desc) + register struct grid_pkg_desc *desc; +{ + register char *array; + + if (desc->holes_array) /* already allocated */ + return; + if (!desc->nrows || !desc->ncolumns) /* not specified yet */ + return; + /* allocate it! */ + array = malloc(desc->nrows * desc->ncolumns); + if (!array) { + perror("malloc"); + exit(1); + } + desc->holes_array = array; + bzero(array, desc->nrows * desc->ncolumns); +} + +static void +validate_rows_arg(arg, filename, lineno) + char *arg, *filename; + int lineno; +{ + register char *cp; + register int c, prev; + + prev = 0; + for (cp = arg; c = *cp++; prev = c) { + if (c < 'A' || c > 'Z') { + fprintf(stderr, + "%s line %d: rows setting: only uppercase letters are allowed\n", + filename, lineno); + exit(1); + } + if (c <= prev) { + fprintf(stderr, + "%s line %d: rows setting: letters must be increasing\n", + filename, lineno); + exit(1); + } + } +} + +static void +handle_rows_line(desc, arg, filename, lineno) + struct grid_pkg_desc *desc; + char *arg, *filename; + int lineno; +{ + register char *cp, *np; + + if (desc->row_letters) { + fprintf(stderr, "%s line %d: duplicate rows setting\n", + filename, lineno); + exit(1); + } + for (cp = arg; isspace(*cp); cp++) + ; + if (*cp == '\0' || *cp == '#') { + fprintf(stderr, "%s line %d: rows setting has no argument\n", + filename, lineno); + exit(1); + } + for (np = cp; *cp && !isspace(*cp); cp++) + ; + if (*cp) + *cp++ = '\0'; + validate_rows_arg(np, filename, lineno); + desc->row_letters = copystr(np); + desc->nrows = strlen(np); + check_complete(desc); +} + +static void +handle_columns_line(desc, arg, filename, lineno) + struct grid_pkg_desc *desc; + char *arg, *filename; + int lineno; +{ + register char *cp, *np; + + if (desc->ncolumns) { + fprintf(stderr, "%s line %d: duplicate columns setting\n", + filename, lineno); + exit(1); + } + for (cp = arg; isspace(*cp); cp++) + ; + if (*cp == '\0' || *cp == '#') { + fprintf(stderr, "%s line %d: columns setting has no argument\n", + filename, lineno); + exit(1); + } + for (np = cp; *cp && !isspace(*cp); cp++) + ; + if (*cp) + *cp++ = '\0'; + if (!string_is_valid_decnum(np)) { + fprintf(stderr, + "%s line %d: columns setting must be a number\n", + filename, lineno); + exit(1); + } + desc->ncolumns = atoi(np); + if (desc->ncolumns < 1) { + fprintf(stderr, "%s line %d: columns number must be positive\n", + filename, lineno); + exit(1); + } + check_complete(desc); +} + +static void +handle_hole_spec(desc, arg, filename, lineno) + register struct grid_pkg_desc *desc; + char *arg, *filename; + int lineno; +{ + char *arg2; + struct xga_parsed_pinnum start_parsed, end_parsed; + register int r, c; + + arg2 = index(arg, '-'); + if (arg2) + *arg2++ = '\0'; + else + arg2 = arg; + if (parse_xga_pinnumber(desc, arg, &start_parsed) < 0) { + fprintf(stderr, + "%s line %d: \"%s\" is not a valid pin position for this package\n", + filename, lineno, arg); + exit(1); + } + if (parse_xga_pinnumber(desc, arg2, &end_parsed) < 0) { + fprintf(stderr, + "%s line %d: \"%s\" is not a valid pin position for this package\n", + filename, lineno, arg2); + exit(1); + } + if (start_parsed.row_0based == end_parsed.row_0based) { + r = start_parsed.row_0based; + if (start_parsed.col_0based > end_parsed.col_0based) { +error_reversed: fprintf(stderr, + "%s line %d: hole ranges need to be increasing\n", + filename, lineno); + exit(1); + } + for (c = start_parsed.col_0based; c <= end_parsed.col_0based; + c++) + desc->holes_array[r * desc->ncolumns + c] = 1; + } else if (start_parsed.col_0based == end_parsed.col_0based) { + c = start_parsed.col_0based; + if (start_parsed.row_0based > end_parsed.row_0based) + goto error_reversed; + for (r = start_parsed.row_0based; r <= end_parsed.row_0based; + r++) + desc->holes_array[r * desc->ncolumns + c] = 1; + } else { + fprintf(stderr, + "%s line %d: hole ranges must be horizontal or vertical\n", + filename, lineno); + exit(1); + } +} + +static void +handle_hole_line(desc, arg, filename, lineno) + struct grid_pkg_desc *desc; + char *arg, *filename; + int lineno; +{ + register char *cp, *np; + + if (!desc->holes_array) { + fprintf(stderr, + "%s line %d: rows and columns must be defined before holes\n", + filename, lineno); + exit(1); + } + for (cp = arg; ; ) { + while (isspace(*cp)) + cp++; + if (*cp == '\0' || *cp == '#') + break; + for (np = cp; *cp && !isspace(*cp); cp++) + ; + if (*cp) + *cp++ = '\0'; + handle_hole_spec(desc, np, filename, lineno); + } +} + +struct grid_pkg_desc * +read_grid_pkg_file(filename) + char *filename; +{ + FILE *f; + char linebuf[1024]; + int lineno; + register char *cp, *np; + struct grid_pkg_desc *desc; + + f = find_symlib_file(filename, NULL); + if (!f) { + fprintf(stderr, "Cannot find xGA definition file %s\n", + filename); + exit(1); + } + desc = (struct grid_pkg_desc *) malloc(sizeof(struct grid_pkg_desc)); + if (!desc) { + perror("malloc"); + exit(1); + } + bzero(desc, sizeof(struct grid_pkg_desc)); + for (lineno = 1; fgets(linebuf, sizeof linebuf, f); lineno++) { + for (cp = linebuf; isspace(*cp); cp++) + ; + if (*cp == '\0' || *cp == '#') + continue; + for (np = cp; *cp && !isspace(*cp); cp++) + ; + if (*cp) + *cp++ = '\0'; + if (!strcmp(np, "rows")) + handle_rows_line(desc, cp, sought_libfile_fullpath, + lineno); + else if (!strcmp(np, "columns")) + handle_columns_line(desc, cp, sought_libfile_fullpath, + lineno); + else if (!strcmp(np, "hole")) + handle_hole_line(desc, cp, sought_libfile_fullpath, + lineno); + else { + fprintf(stderr, + "%s line %d: setting \"%s\" not understood\n", + sought_libfile_fullpath, lineno, np); + exit(1); + } + } + fclose(f); + + if (!desc->nrows) { + fprintf(stderr, "error: %s contains no rows setting\n", + sought_libfile_fullpath); + exit(1); + } + if (!desc->ncolumns) { + fprintf(stderr, "error: %s contains no columns setting\n", + sought_libfile_fullpath); + exit(1); + } + return(desc); +} + +free_grid_pkg_desc(desc) + struct grid_pkg_desc *desc; +{ + free(desc->row_letters); + free(desc->holes_array); + free(desc); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libueda/xga.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,13 @@ +/* Data structure describing PGA/BGA packages */ + +struct grid_pkg_desc { + int nrows; + int ncolumns; + char *row_letters; + char *holes_array; +}; + +struct xga_parsed_pinnum { + int row_0based; + int col_0based; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,18 @@ +CFLAGS= -O +LIBOBJS=compinst.o graphblocks.o graphnets.o graphsym.o graphsym_load.o \ + matchtomcl.o parser_assist.o pinref.o pins.o rdschem.o rdschem_lex.o \ + rdschem_parse.o schemobj.o wrschem.o +HDRS= graphsym.h parserint.h schemstruct.h writerint.h + +all: libuschem.a + +libuschem.a: ${LIBOBJS} + ar rcu $@ ${LIBOBJS} + ranlib $@ + +${LIBOBJS}: ${HDRS} + +clean: + rm -f *.[ao] a.out core errs + +install:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/compinst.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,102 @@ +/* + * Component instance hash table logic + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "schemstruct.h" + +extern char *malloc(); + +#define HASH_SIZE 1103 + +static int +hash_instname(str) + char *str; +{ + register u_long accum; + register char *cp; + register int c; + + for (cp = str, accum = 0; c = *cp; cp++) { + accum <<= 4; + accum |= c & 0x0F; + } + return(accum % HASH_SIZE); +} + +hash_component_instances(schem) + struct schem *schem; +{ + struct schemobj **hashtab; + register struct schemobj *obj, *hc, **hcp; + int errflag = 0, errstat = 0; + + hashtab = (struct schemobj **) + malloc(sizeof(struct schemobj *) * HASH_SIZE); + if (!hashtab) { + perror("malloc"); + exit(1); + } + bzero(hashtab, sizeof(struct schemobj *) * HASH_SIZE); + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) { + if (obj->obj_type != OBJTYPE_COMPINST) + continue; + hcp = hashtab + hash_instname(obj->compobj_instname); + for (; hc = *hcp; hcp = &hc->compobj_nextinhash) + if (!strcmp(obj->compobj_instname, hc->compobj_instname)) { + fprintf(stderr, + "%s: %s: duplicate component instance name (line %d, line %d)\n", + schem->orig_filename, obj->compobj_instname, + hc->obj_lineno, obj->obj_lineno); + errflag = 1; + break; + } + if (errflag) { + errflag = 0; + errstat = -1; + } else + *hcp = obj; + } + schem->compinst_hash = hashtab; + return(errstat); +} + +report_compinst_hash_quality(schem) + struct schem *schem; +{ + struct schemobj **hashtab; + int maxchain, total; + register int hb, curchain; + register struct schemobj *obj; + + hashtab = schem->compinst_hash; + for (hb = 0, total = maxchain = 0; hb < HASH_SIZE; hb++) { + for (obj = hashtab[hb], curchain = 0; obj; + obj = obj->compobj_nextinhash) { + curchain++; + total++; + } + if (curchain > maxchain) + maxchain = curchain; + } + printf("%s: %d component instances total, longest hash chain is %d\n", + schem->orig_filename, total, maxchain); +} + +struct schemobj * +find_component_instance(schem, instname) + struct schem *schem; + register char *instname; +{ + register struct schemobj *obj; + + for (obj = schem->compinst_hash[hash_instname(instname)]; obj; + obj = obj->compobj_nextinhash) + if (!strcmp(obj->compobj_instname, instname)) + return(obj); + return(NULL); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/graphblocks.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,40 @@ +/* + * utility functions for working with graphical blocks + */ + +#include <sys/param.h> +#include <stdio.h> +#include "schemstruct.h" + +FILE * +reopen_schem_for_graphblocks(schem) + struct schem *schem; +{ + register FILE *f; + + if (!schem->has_graphblocks) + return(NULL); + f = fopen(schem->orig_filename, "r"); + if (!f) { + fprintf(stderr, "Unable to reopen %s for graphblocks: ", + schem->orig_filename); + perror(NULL); + exit(1); + } + return(f); +} + +write_graphblock_to_file(blk, inf, outf) + struct graphblock *blk; + register FILE *inf, *outf; +{ + char buf[512]; + register int cc, rem; + + fseek(inf, blk->offset, 0); + for (rem = blk->length; rem; rem -= cc) { + cc = MIN(rem, sizeof buf); + fread(buf, 1, cc, inf); + fwrite(buf, 1, cc, outf); + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/graphnets.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,365 @@ +/* + * preen_graphnets() functionality + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "schemstruct.h" +#include "graphsym.h" + +extern char *malloc(); + +extern struct graphsym_pininst *find_comp_pininst(); +extern struct graphsym_pininst *find_pin_by_coord(); + +static struct schem *schem_being_preened; +static int dowarn, docorrect, severe_err; + +static int +tjoin_hit_check(obj, tjoin) + struct schemobj *obj; + register struct netpoint *tjoin; +{ + register struct netpoint *netpt, *nextpt; + + for (netpt = obj->netobj_points; netpt && (nextpt = netpt->netpt_next); + netpt = nextpt) { + if (!netpt->netpt_coord_valid || !nextpt->netpt_coord_valid) { + fprintf(stderr, +"%s: line %d: Pin w/o coordinates impedes search for Tjoin antecedent\n", + schem_being_preened->orig_filename, + obj->obj_lineno); + severe_err = -1; + return(-1); + } + /* check for horizontal segments */ + if (netpt->netpt_y == tjoin->netpt_y && + nextpt->netpt_y == tjoin->netpt_y) { + if (tjoin->netpt_x > netpt->netpt_x && + tjoin->netpt_x < nextpt->netpt_x) + return(1); + if (tjoin->netpt_x < netpt->netpt_x && + tjoin->netpt_x > nextpt->netpt_x) + return(1); + } + /* check for vertical segments */ + if (netpt->netpt_x == tjoin->netpt_x && + nextpt->netpt_x == tjoin->netpt_x) { + if (tjoin->netpt_y > netpt->netpt_y && + tjoin->netpt_y < nextpt->netpt_y) + return(1); + if (tjoin->netpt_y < netpt->netpt_y && + tjoin->netpt_y > nextpt->netpt_y) + return(1); + } + } + return(0); +} + +static struct schemobj * +find_grouphead_tail(ghead) + register struct schemobj *ghead; +{ + register struct schemobj *obj, *next; + + for (obj = ghead; ; obj = next) { + next = obj->obj_next; + if (next->obj_type != OBJTYPE_GRAPHNET) + return(obj); + if (next->netobj_grouphead != ghead) + return(obj); + } +} + +static +preen_tjoin(obj, netpt, first, got_tjoin) + struct schemobj *obj; + register struct netpoint *netpt; + int first, *got_tjoin; +{ + register struct schem *schem; + register struct schemobj *prevobj; + struct schemobj *ghead; + register int c; + + schem = schem_being_preened; + if (first) + *got_tjoin = 1; + else if (!netpt->netpt_next) { + if (*got_tjoin) { + fprintf(stderr, + "%s: line %d: Tjoin on both ends of a GraphNet is illegal\n", + schem->orig_filename, obj->obj_lineno); + severe_err = -1; + return; + } + *got_tjoin = 1; + } else { + fprintf(stderr, + "%s: line %d: Tjoin in the middle of a GraphNet is meaningless\n", + schem->orig_filename, obj->obj_lineno); + severe_err = -1; + return; + } + for (prevobj = obj->obj_prev, c = 0; + prevobj != (struct schemobj *)schem; prevobj = prevobj->obj_prev) + if (prevobj->obj_type == OBJTYPE_GRAPHNET) { + c = tjoin_hit_check(prevobj, netpt); + if (c < 0) + return; + if (c) + break; + } + if (!c) { + fprintf(stderr, "%s: line %d: Tjoin antecedent not found\n", + schem->orig_filename, obj->obj_lineno); + severe_err = -1; + return; + } + netpt->netpt_tjoin_to = prevobj; + obj->netobj_grouphead = ghead = prevobj->netobj_grouphead; + /* netname logic */ + if (obj->netobj_netname) { + /* accumulate on the group head */ + if (!ghead->netobj_netname) + ghead->netobj_netname = obj->netobj_netname; + else if (strcmp(ghead->netobj_netname, obj->netobj_netname)) { + fprintf(stderr, + "%s: line %d: Tjoin connects two netnames: %s and %s\n", + schem->orig_filename, obj->obj_lineno, + ghead->netobj_netname, obj->netobj_netname); + severe_err = -1; + return; + } + } + /* shuffling around to bring groups together */ + prevobj = obj->obj_prev; + if (prevobj->obj_type != OBJTYPE_GRAPHNET || + prevobj->netobj_grouphead != ghead) { + prevobj = find_grouphead_tail(ghead); + schemobj_unlink(obj); + schemobj_insert_after(prevobj, obj); + } +} + +static +preen_pin(obj, netpt) + struct schemobj *obj; + register struct netpoint *netpt; +{ + register int i = 0, c; + struct graphsym_pininst *pinc, *pinn; + struct schemobj *comp; + char *soughtpin; + int bynum; + + if (netpt->netpt_coord_valid) { + i |= 2; + pinc = find_pin_by_coord(schem_being_preened, netpt->netpt_x, + netpt->netpt_y); + } + if (netpt->netpt_pin_nameref) { + i |= 1; + c = parse_pin_nameref(schem_being_preened, obj->obj_lineno, + netpt->netpt_pin_nameref, &comp, + &soughtpin, &bynum); + if (c < 0) + severe_err = -1; + } + switch (i) { + case 1: + if (dowarn) + fprintf(stderr, + "%s: line %d: Pin w/o coordinates, run uschem-rewrite -g to fix\n", + schem_being_preened->orig_filename, + obj->obj_lineno); + if (c < 0) + return; + if (!comp->compobj_isgraph) { +nograph: fprintf(stderr, + "%s: line %d: %s: GraphNet refers to a non-graphical component\n", + schem_being_preened->orig_filename, + obj->obj_lineno, netpt->netpt_pin_nameref); + severe_err = -1; + return; + } + pinn = find_comp_pininst(comp, soughtpin, bynum); + if (!pinn) { +pinnotfound: fprintf(stderr, "%s: line %d: %s: pin not found\n", + schem_being_preened->orig_filename, + obj->obj_lineno, netpt->netpt_pin_nameref); + severe_err = -1; + return; + } + /* fix it */ + netpt->netpt_x = pinn->x; + netpt->netpt_y = pinn->y; + netpt->netpt_coord_valid = 1; + return; + case 2: + if (dowarn) + fprintf(stderr, +"%s: line %d: Pin given by coordinates only, run uschem-rewrite -g to fix\n", + schem_being_preened->orig_filename, + obj->obj_lineno); + if (!pinc) { + fprintf(stderr, + "%s: line %d: no pin found at (%d,%d)\n", + schem_being_preened->orig_filename, + obj->obj_lineno, netpt->netpt_x, + netpt->netpt_y); + severe_err = -1; + return; + } + comp = pinc->compinst; + if (comp->obj_type != OBJTYPE_COMPINST) { + fprintf(stderr, + "%s: line %d: Pin refers to a non-component\n", + schem_being_preened->orig_filename, + obj->obj_lineno); + severe_err = -1; + return; + } + if (!docorrect) + return; + if (pinc->pindef->gspd_pinname) { + soughtpin = pinc->pindef->gspd_pinname; + bynum = 0; + } else if (pinc->pindef->gspd_pinnumber) { + soughtpin = pinc->pindef->gspd_pinnumber; + bynum = 1; + } else { + fprintf(stderr, + "%s: %s pin at (%d,%d) has no pinname or pinnumber attribute\n", + schem_being_preened->orig_filename, + comp->compobj_instname, netpt->netpt_x, + netpt->netpt_y); + severe_err = -1; + return; + } + netpt->netpt_pin_nameref = + malloc(strlen(comp->compobj_instname) + + strlen(soughtpin) + 2); + if (!netpt->netpt_pin_nameref) { + perror("malloc"); + exit(1); + } + sprintf(netpt->netpt_pin_nameref, "%s%c%s", + comp->compobj_instname, bynum ? '-' : '.', soughtpin); + return; + case 3: + if (!dowarn || c < 0) + return; + if (!comp->compobj_isgraph) + goto nograph; + pinn = find_comp_pininst(comp, soughtpin, bynum); + if (!pinn) + goto pinnotfound; + if (pinc != pinn) + fprintf(stderr, + "%s: line %d: Pin(%d,%d)=%s: pin name and coordinates don't match\n", + schem_being_preened->orig_filename, + obj->obj_lineno, netpt->netpt_x, netpt->netpt_y, + netpt->netpt_pin_nameref); + return; + } +} + +static +preen_pseudopin(obj, netpt) + struct schemobj *obj; + register struct netpoint *netpt; +{ + register struct graphsym_pininst *pin; + register struct schemobj *ghead; + + pin = find_pin_by_coord(schem_being_preened, netpt->netpt_x, + netpt->netpt_y); + if (!pin) { + fprintf(stderr, "%s: line %d: no pin found at (%d,%d)\n", + schem_being_preened->orig_filename, obj->obj_lineno, + netpt->netpt_x, netpt->netpt_y); + severe_err = -1; + return; + } + if (pin->compinst->obj_type != OBJTYPE_GRAPHSYM) { + fprintf(stderr, +"%s: line %d: Pseudo refers to a real component pin (use Pin instead)\n", + schem_being_preened->orig_filename, obj->obj_lineno); + severe_err = -1; + return; + } + if (!pin->pindef->gspd_forcenet) + return; + obj->netobj_forcenets++; + ghead = obj->netobj_grouphead; + if (!ghead) + ghead = obj; + if (!ghead->netobj_netname) { + if (dowarn) + fprintf(stderr, +"%s: line %d: GraphNet needs to be forced to net %s (run uschem-rewrite -g to fix)\n", + schem_being_preened->orig_filename, + obj->obj_lineno, pin->pindef->gspd_forcenet); + if (docorrect) + ghead->netobj_netname = pin->pindef->gspd_forcenet; + } else if (strcmp(ghead->netobj_netname, pin->pindef->gspd_forcenet)) { + fprintf(stderr, +"%s: line %d: Graphnet %s is forced to net %s by a special symbol connection\n", + schem_being_preened->orig_filename, obj->obj_lineno, + ghead->netobj_netname, pin->pindef->gspd_forcenet); + severe_err = -1; + } +} + +static +do_graphnet(obj, do_tjoin, do_pins) + struct schemobj *obj; +{ + register struct netpoint *netpt; + register int first; + int got_tjoin = 0; + + if (do_tjoin) + obj->netobj_grouphead = obj; /* for now at least */ + for (netpt = obj->netobj_points, first = 1; netpt; + netpt = netpt->netpt_next, first = 0) { + if (dowarn && first && !netpt->netpt_next) + fprintf(stderr, "%s: line %d: singular GraphNet\n", + schem_being_preened->orig_filename, + obj->obj_lineno); + switch (netpt->netpt_type) { + case NETPT_TYPE_TJOIN: + if (do_tjoin) + preen_tjoin(obj, netpt, first, &got_tjoin); + continue; + case NETPT_TYPE_PIN: + if (do_pins) + preen_pin(obj, netpt); + continue; + case NETPT_TYPE_PSEUDO: + if (do_pins) + preen_pseudopin(obj, netpt); + continue; + } + } +} + +preen_graphnets(schem, do_tjoin, do_pins, warn, correct) + struct schem *schem; +{ + register struct schemobj *obj, *next; + + schem_being_preened = schem; + dowarn = warn; + docorrect = correct; + severe_err = 0; + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = next) { + next = obj->obj_next; + if (obj->obj_type == OBJTYPE_GRAPHNET) + do_graphnet(obj, do_tjoin, do_pins); + } + return(severe_err); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/graphsym.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,125 @@ +/* + * Functions for working with graphical symbols + */ + +#include <sys/types.h> +#include <stdio.h> +#include <ctype.h> +#include <strings.h> +#include "schemstruct.h" +#include "graphsym.h" + +extern char *malloc(); +extern char *copystr(); + +extern FILE *find_symlib_file(); +extern char sought_libfile_fullpath[]; + +#define HASH_SIZE 1103 + +static struct graphsym *graphsym_hash[HASH_SIZE]; +int total_graphsyms; + +static int +hash_graphsym_name(str) + char *str; +{ + register u_long accum = 0; + register char *cp; + register int c, i; + + for (cp = str, i = 1; c = *cp; cp++, i++) + accum += c * i; + return(accum % HASH_SIZE); +} + +struct graphsym * +fetch_graphsym(symname) + char *symname; +{ + register struct graphsym *gs, **gsp; + FILE *f; + + for (gsp = graphsym_hash + hash_graphsym_name(symname); gs = *gsp; + gsp = &gs->gs_nextinhash) + if (!strcmp(gs->gs_name, symname)) + return(gs); + + gs = (struct graphsym *) malloc(sizeof(struct graphsym)); + bzero(gs, sizeof(struct graphsym)); + gs->gs_name = symname; + f = find_symlib_file(symname, ".sym"); + if (!f) { + fprintf(stderr, "Cannot locate graphical symbol \"%s\"\n", + symname); + exit(1); + } + gs->gs_pathname = copystr(sought_libfile_fullpath); + read_symbol_file(gs, f); + fclose(f); + + *gsp = gs; + total_graphsyms++; + return(gs); +} + +load_graphsyms(schem) + struct schem *schem; +{ + register struct schemobj *obj; + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) + switch (obj->obj_type) { + case OBJTYPE_COMPINST: + if (!obj->compobj_isgraph) + continue; + /* FALL THRU */ + case OBJTYPE_GRAPHSYM: + obj->compobj_graphsym = + fetch_graphsym(obj->compobj_graph_symname); + load_decor_graphsyms(obj); + break; + } +} + +load_decor_graphsyms(obj) + struct schemobj *obj; +{ + register struct decoration *decor; + + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) { + if (decor->decor_type != DECOR_TYPE_SYMONPIN) + continue; + decor->decorpinsym_gs = + fetch_graphsym(decor->decorpinsym_symname); + } +} + +graphsym_forall(callback) + int (*callback)(); +{ + register struct graphsym *gs, **hb; + register int i; + + for (hb = graphsym_hash, i = 0; i < HASH_SIZE; hb++, i++) + for (gs = *hb; gs; gs = gs->gs_nextinhash) + callback(gs); +} + +report_graphsym_hash_quality() +{ + register struct graphsym *gs, **hb; + register int i, curchain; + int maxchain = 0; + + for (hb = graphsym_hash, i = 0; i < HASH_SIZE; hb++, i++) { + curchain = 0; + for (gs = *hb; gs; gs = gs->gs_nextinhash) + curchain++; + if (curchain > maxchain) + maxchain = curchain; + } + printf("%d graphsyms total, longest hash chain is %d\n", + total_graphsyms, maxchain); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/graphsym.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,30 @@ +/* + * data structures for graphical symbols + */ + +struct graphsym { + char *gs_name; + char *gs_pathname; + struct graphsym_pindef *gs_pins; + int gs_npins; + int gs_varpins; + int gs_forcenets; + struct graphsym *gs_nextinhash; +}; + +struct graphsym_pindef { + int gspd_x; + int gspd_y; + char *gspd_pinname; + char *gspd_pinnumber; + char *gspd_forcenet; + struct graphsym_pindef *gspd_next; +}; + +struct graphsym_pininst { + int x; + int y; + struct schemobj *compinst; + struct graphsym_pindef *pindef; + struct graphsym_pininst *nextinhash; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/graphsym_load.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,371 @@ +/* + * The black magic of loading/prescanning gschem-based uschem symbols + */ + +#include <ctype.h> +#include <stdio.h> +#include <strings.h> +#include "graphsym.h" + +extern char *malloc(); +extern char *copystr(); + +#define MAXLINE 256 + +static struct graphsym *symstruct; +static FILE *inf; +static int lineno; +static struct graphsym_pindef **pintail; + +read_symbol_file(gs, f) + struct graphsym *gs; + FILE *f; +{ + symstruct = gs; + inf = f; + lineno = 0; + pintail = &gs->gs_pins; + mymain(); + if (!gs->gs_npins) { + fprintf(stderr, "%s: symbol has no pins (invalid)\n", + gs->gs_pathname); + exit(1); + } +} + +static +mymain() +{ + char line[MAXLINE]; + register char *cp; + register int c; + + while (getline(line)) { + if (line[0] == '%') /* PS-like comments */ + continue; + if (line[0] == '\0') /* allow blank lines too */ + continue; + if (!isalpha(line[0])) { +inv: fprintf(stderr, "%s: line %d: invalid symbol data\n", + symstruct->gs_pathname, lineno); + exit(1); + } + for (cp = line; isalpha(*cp); cp++) + ; + if (!isspace(*cp)) + goto inv; + *cp++ = '\0'; + while (isspace(*cp)) + cp++; + if (!strcmp(line, "PS")) { + if (strcmp(cp, "{")) + goto inv; + skip_ps_block(); + continue; + } else if (strlen(line) != 1) + goto inv; + line[1] = ' '; + /* dispatch by single-char type */ + switch (line[0]) { + case 'v': + continue; /* ignore */ + /* simple graphics */ + case 'L': + case 'B': + case 'V': + case 'A': + /* ignore at this stage too */ + continue; + case 'P': + handle_pin(line, lineno); + continue; + case 'T': + handle_T_obj(line, lineno); + continue; + default: + goto inv; + } + } +} + +static +handle_pin(objline, objlineno) + char *objline; +{ + int numparams[7]; + char junkline[MAXLINE]; + register struct graphsym_pindef *pin; + + parse_numline(objline, objlineno, numparams, 7); + pin = (struct graphsym_pindef *) malloc(sizeof(struct graphsym_pindef)); + if (!pin) { + perror("malloc"); + exit(1); + } + bzero(pin, sizeof(struct graphsym_pindef)); + if (numparams[6]) { + pin->gspd_x = numparams[2]; + pin->gspd_y = numparams[3]; + } else { + pin->gspd_x = numparams[0]; + pin->gspd_y = numparams[1]; + } + *pintail = pin; + pintail = &pin->gspd_next; + symstruct->gs_npins++; + if (!getline(junkline) || strcmp(junkline, "{")) { + fprintf(stderr, + "%s: line %d: P line must be followed by '{' line\n", + symstruct->gs_pathname, objlineno); + exit(1); + } + read_pin_attrs(pin, objlineno); +} + +static +read_pin_attrs(pin, objlineno) + struct graphsym_pindef *pin; +{ + char line[MAXLINE]; + int Tline_parsed[9]; + register char *cp; + + for (;;) { + if (!getline(line)) { +badeof: fprintf(stderr, "%s: EOF in pin attribute block\n", + symstruct->gs_pathname); + exit(1); + } + if (line[0] == '%') /* PS-like comments */ + continue; + if (line[0] == '\0') /* allow blank lines too */ + continue; + if (line[0] == '}') + return; + if (!isalpha(line[0])) { +inv: fprintf(stderr, "%s: line %d: invalid symbol data\n", + symstruct->gs_pathname, lineno); + exit(1); + } + for (cp = line; isalpha(*cp); cp++) + ; + if (!isspace(*cp)) + goto inv; + *cp++ = '\0'; + if (!strcmp(line, "attr")) { + while (isspace(*cp)) + cp++; + handle_attr(pin, cp); + continue; + } else if (strcmp(line, "T")) { + fprintf(stderr, + "%s: line %d: wrong object type in pin attribute block\n", + symstruct->gs_pathname, lineno); + exit(1); + } + line[1] = ' '; + parse_numline(line, lineno, Tline_parsed, 9); + if (Tline_parsed[8] < 1) { + fprintf(stderr, "%s: line %d: T object: num_lines<1!\n", + symstruct->gs_pathname, lineno); + exit(1); + } + if (Tline_parsed[8] > 1) { + fprintf(stderr, + "%s: line %d: multiline text object in attribute block not supported\n", + symstruct->gs_pathname, lineno); + exit(1); + } + if (!getline(line)) + goto badeof; + handle_attr(pin, line); + } +} + +static +handle_attr(pin, line) + register struct graphsym_pindef *pin; + register char *line; +{ + register char *cp; + + cp = index(line, '='); + if (!cp) + return; + *cp++ = '\0'; + if (!*cp) /* avoid null string values */ + return; + if (!strcmp(line, "pinname")) { + if (pin->gspd_pinname) { +dup: fprintf(stderr, + "%s: line %d: duplicate %s attribute (ignored)\n", + symstruct->gs_pathname, lineno, line); + return; + } + pin->gspd_pinname = copystr(cp); + } else if (!strcmp(line, "pinnumber")) { + if (pin->gspd_pinnumber) + goto dup; + pin->gspd_pinnumber = copystr(cp); + if (!strcmp(cp, "%d")) + symstruct->gs_varpins++; + } else if (!strcmp(line, "forcenet")) { + if (pin->gspd_forcenet) + goto dup; + pin->gspd_forcenet = copystr(cp); + symstruct->gs_forcenets++; + } +} + +static +handle_T_obj(objline, objlineno) + char *objline; +{ + int numparams[9]; + char junkline[MAXLINE]; + register int i; + + parse_numline(objline, objlineno, numparams, 9); + if (numparams[8] < 1) { + fprintf(stderr, "%s: line %d: T object: num_lines<1!\n", + symstruct->gs_pathname, objlineno); + exit(1); + } + for (i = numparams[8]; i; i--) { + if (!getline(junkline)) { + fprintf(stderr, "%s: EOF in T object\n", + symstruct->gs_pathname); + exit(1); + } + } +} + +static +parse_numline(line, lineno, numarray, nfields) + char *line; + int lineno; + int *numarray; + int nfields; +{ + register char *cp, *np; + register int i; + + for (i = 0, cp = line+1; i < nfields; i++) { + if (!isspace(*cp)) { +inv: fprintf(stderr, "%s: line %d: invalid numeric line\n", + symstruct->gs_pathname, lineno); + exit(1); + } + while (isspace(*cp)) + cp++; + np = cp; + if (*cp == '-') + cp++; + if (!isdigit(*cp)) + goto inv; + while (isdigit(*cp)) + cp++; + numarray[i] = atoi(np); + } + if (*cp) + goto inv; +} + +static +getline(linebuf) + char *linebuf; +{ + register char *cp; + + if (fgets(linebuf, MAXLINE, inf) == NULL) + return(0); + lineno++; + /* strip trailing newline or other whitespace */ + cp = index(linebuf, '\0'); + while (cp > linebuf && isspace(cp[-1])) + cp--; + *cp = '\0'; + return(1); +} + +static +skip_ps_block() +{ + register int c, n; + + for (n = 0; n >= 0; ) { + c = getc(inf); + switch (c) { + case EOF: +badeof: fprintf(stderr, "%s: EOF in a PS block\n", + symstruct->gs_pathname); + exit(1); + case '%': + for (;;) { + c = getc(inf); + if (c == EOF) + goto badeof; + if (c == '\n') + break; + } + /* FALL THRU */ + case '\n': + lineno++; + continue; + case '(': + skip_over_ps_string(); + continue; + case ')': + fprintf(stderr, + "%s: line %d: unmatched \')\' in a PS block", + symstruct->gs_pathname, lineno); + exit(1); + case '{': + n++; + continue; + case '}': + n--; + continue; + } + } + c = getc(inf); + if (c != '\n') { + fprintf(stderr, +"%s: line %d: '}' closing PS block must be directly followed by newline\n", + symstruct->gs_pathname, lineno); + exit(1); + } + lineno++; +} + +static +skip_over_ps_string() +{ + register int c, n; + + for (n = 1; n > 0; ) { + c = getc(inf); + switch (c) { + case EOF: +badeof: fprintf(stderr, "%s: EOF in a PS block\n", + symstruct->gs_pathname); + exit(1); + case '\n': + lineno++; + continue; + case '(': + n++; + continue; + case ')': + n--; + continue; + case '\\': + c = getc(inf); + if (c == EOF) + goto badeof; + if (c == '\n') + lineno++; + continue; + } + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/matchtomcl.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,68 @@ +/* + * Logic to match uschem component instances to MCL components + */ + +#include <sys/types.h> +#include <stdio.h> +#include <ctype.h> +#include <strings.h> +#include "../libueda/mcl.h" +#include "schemstruct.h" + +extern struct component *find_comp_by_refdes(); +extern char *get_comp_attr(); + +match_schem_to_mcl(schem) + struct schem *schem; +{ + register struct schemobj *obj; + int errflag = 0; + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) + if (obj->obj_type == OBJTYPE_COMPINST) + if (match_compinst_to_mcl(schem, obj)) + errflag = 1; + if (errflag) + exit(1); + return(0); +} + +match_compinst_to_mcl(schem, obj) + struct schem *schem; + register struct schemobj *obj; +{ + char refdes[256]; + register char *cp; + register struct component *comp; + + strcpy(refdes, obj->compobj_instname); + cp = index(refdes, '\0'); + while (cp > refdes && islower(cp[-1])) + cp--; + *cp = '\0'; + comp = find_comp_by_refdes(refdes); + if (comp) { + obj->compobj_mclcomp = comp; + return(0); + } else { + fprintf(stderr, + "%s: line %d: component %s not found in the MCL\n", + schem->orig_filename, obj->obj_lineno, refdes); + return(-1); + } +} + +char * +get_compinst_attr(obj, attrname) + struct schemobj *obj; + register char *attrname; +{ + register struct decoration *decor; + + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) + if (decor->decor_type == DECOR_TYPE_ATTR && + !strcmp(decor->decorattr_name, attrname)) + return(decor->decorattr_value); + return(get_comp_attr(obj->compobj_mclcomp, attrname)); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/parser_assist.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,115 @@ +/* + * Routines to help the schematic parser, mostly allocation of data + * structures. + */ + +#include <sys/types.h> +#include <stdio.h> +#include <ctype.h> +#include <strings.h> +#include "schemstruct.h" +#include "parserint.h" + +extern char *malloc(); + +extern struct schem_parse_state schem_parse_state; + +struct schemobj * +parser_alloc_obj(objtype) +{ + register struct schemobj *obj; + + obj = (struct schemobj *) malloc(sizeof(struct schemobj)); + if (!obj) { + perror("malloc"); + exit(1); + } + bzero(obj, sizeof(struct schemobj)); + obj->obj_type = objtype; + obj->obj_lineno = schem_parse_state.lineno; + return(obj); +} + +struct decoration * +parser_alloc_decor(type) +{ + register struct decoration *dec; + + dec = (struct decoration *) malloc(sizeof(struct decoration)); + if (!dec) { + perror("malloc"); + exit(1); + } + bzero(dec, sizeof(struct decoration)); + dec->decor_type = type; + dec->decor_lineno = schem_parse_state.lineno; + return(dec); +} + +struct netpoint * +parser_alloc_netpoint(type) +{ + register struct netpoint *netpt; + + netpt = (struct netpoint *) malloc(sizeof(struct netpoint)); + if (!netpt) { + perror("malloc"); + exit(1); + } + bzero(netpt, sizeof(struct netpoint)); + netpt->netpt_type = type; + return(netpt); +} + +parser_add_object(obj) + struct schemobj *obj; +{ + schemobj_insert_before((struct schemobj *) schem_parse_state.schem, + obj); +} + +/* drawing sizes for graphical schematics */ + +struct drawing_size_kwtab drawing_size_keywords[] = { + {"A", 11000, 8500}, + {"B", 17000, 11000}, + {"C", 22000, 17000}, + {"D", 34000, 22000}, + {"E", 44000, 34000}, + {NULL, 0, 0} +}; + +struct xypair +parse_drawing_size_spec(str) + char *str; +{ + struct drawing_size_kwtab *kwp; + struct xypair retval; + register char *cp, *np; + + for (kwp = drawing_size_keywords; kwp->keyword; kwp++) + if (!strcmp(str, kwp->keyword)) { + retval.x = kwp->xdim; + retval.y = kwp->ydim; + return(retval); + } + + cp = str; + if (!isdigit(*cp)) { +inv: rdschem_error("invalid drawing size specification"); + exit(1); + } + for (np = cp; isdigit(*cp); cp++) + ; + if (*cp++ != 'x') + goto inv; + retval.x = atoi(np); + if (!isdigit(*cp)) + goto inv; + for (np = cp; isdigit(*cp); cp++) + ; + if (*cp) + goto inv; + retval.y = atoi(np); + return(retval); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/parserint.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,23 @@ +/* + * These data structures are internal to the schematic reading/parsing process + * and persist only while that operation is in progress. + */ + +/* tokens */ +#define STRING 256 +#define QSTRING 257 + +#define MAXSTRING 63 + +struct schem_parse_state { + FILE *file; + int lineno; + struct schem *schem; + char string[MAXSTRING+1]; + int pushback_token; +}; + +struct xypair { + int x; + int y; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/pinref.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,56 @@ +/* + * pin name reference parsing + */ + +#include <sys/types.h> +#include <stdio.h> +#include <ctype.h> +#include "schemstruct.h" + +extern struct schemobj *find_component_instance(); + +parse_pin_nameref(schem, lineno, nameref, compp, soughtpin, bynum) + struct schem *schem; + int lineno; + char *nameref; + struct schemobj **compp; + char **soughtpin; + int *bynum; +{ + register char *cp; + char chsave; + register struct schemobj *comp; + + cp = nameref; + if (!isalnum(*cp)) { +inv: fprintf(stderr, + "%s: line %d: \"%s\" is not a valid pin name reference\n", + schem->orig_filename, lineno, nameref); + return(-1); + } + while (isalnum(*cp)) + cp++; + chsave = *cp; + switch (*cp) { + case '.': + *bynum = 0; + break; + case '-': + *bynum = 1; + break; + default: + goto inv; + } + *cp = '\0'; + comp = find_component_instance(schem, nameref); + if (!comp) + fprintf(stderr, + "%s: line %d: component instance %s not found\n", + schem->orig_filename, lineno, nameref); + *cp++ = chsave; + *compp = comp; + if (!isgraph(*cp)) + goto inv; + *soughtpin = cp; + return(comp ? 0 : -1); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/pins.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,196 @@ +/* + * Working with graphical symbol pin instances + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "schemstruct.h" +#include "graphsym.h" + +extern char *malloc(); + +#define HASH_SIZE 1103 + +static int +hash_coord(x, y) +{ + return((x + y) % HASH_SIZE); +} + +static +add_pin_to_hash(schem, pin) + struct schem *schem; + register struct graphsym_pininst *pin; +{ + register struct graphsym_pininst *hp, **hpp; + + for (hpp = schem->pininst_hash + hash_coord(pin->x, pin->y); hp = *hpp; + hpp = &hp->nextinhash) + if (pin->x == hp->x && pin->y == hp->y) { + fprintf(stderr, + "%s: more than one pin at (%d,%d), see lines %d and %d\n", + schem->orig_filename, pin->x, pin->y, + hp->compinst->obj_lineno, pin->compinst->obj_lineno); + return(-1); + } + *hpp = pin; + return(0); +} + +static +instantiate_obj_pins(schem, obj, dohash) + struct schem *schem; + register struct schemobj *obj; +{ + register struct graphsym_pindef *pd; + register struct graphsym_pininst *pi; + int npins; + int x, y; + int errflag = 0, clashflag = 0; + + npins = obj->compobj_graphsym->gs_npins; + pi = (struct graphsym_pininst *) + malloc(sizeof(struct graphsym_pininst) * npins); + if (!pi) { + perror("malloc"); + exit(1); + } + obj->compobj_pins = pi; + for (pd = obj->compobj_graphsym->gs_pins; pd; pd = pd->gspd_next, pi++){ + pi->compinst = obj; + pi->pindef = pd; + x = pd->gspd_x; + y = pd->gspd_y; + if (obj->compobj_mirror) + x = -x; + switch (obj->compobj_rotate) { + case 0: + pi->x = x; + pi->y = y; + break; + case 90: + pi->x = -y; + pi->y = x; + break; + case 180: + pi->x = -x; + pi->y = -y; + break; + case 270: + pi->x = y; + pi->y = -x; + break; + default: + if (!errflag) { + fprintf(stderr, + "%s: line %d: symbol rotated by %d deg, can't do pin instances\n", + schem->orig_filename, obj->obj_lineno, + obj->compobj_rotate); + errflag = 1; + } + /* a dummy so we don't have to abort */ + pi->x = pi->y = 0; + } + pi->x += obj->compobj_x; + pi->y += obj->compobj_y; + pi->nextinhash = NULL; + if (dohash && !errflag) + if (add_pin_to_hash(schem, pi)) + clashflag = 1; + } + return(errflag || clashflag); +} + +/* prerequisite: load_graphsyms() */ +instantiate_graphsym_pins(schem, dohash) + struct schem *schem; +{ + register struct schemobj *obj; + int errstat = 0; + struct graphsym_pininst **hashtab; + + if (dohash) { + hashtab = (struct graphsym_pininst **) + malloc(sizeof(struct graphsym_pininst *) * HASH_SIZE); + if (!hashtab) { + perror("malloc"); + exit(1); + } + bzero(hashtab, sizeof(struct graphsym_pininst *) * HASH_SIZE); + schem->pininst_hash = hashtab; + } + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) + switch (obj->obj_type) { + case OBJTYPE_COMPINST: + if (!obj->compobj_isgraph) + continue; + /* FALL THRU */ + case OBJTYPE_GRAPHSYM: + if (instantiate_obj_pins(schem, obj, dohash)) + errstat = -1; + break; + } + return(errstat); +} + +report_pininst_hash_quality(schem) + struct schem *schem; +{ + struct graphsym_pininst **hashtab; + int maxchain, total; + register int hb, curchain; + register struct graphsym_pininst *pin; + + hashtab = schem->pininst_hash; + for (hb = 0, total = maxchain = 0; hb < HASH_SIZE; hb++) { + for (pin = hashtab[hb], curchain = 0; pin; + pin = pin->nextinhash) { + curchain++; + total++; + } + if (curchain > maxchain) + maxchain = curchain; + } + printf("%s: %d pin instances total, longest hash chain is %d\n", + schem->orig_filename, total, maxchain); +} + +struct graphsym_pininst * +find_comp_pininst(comp, soughtpin, bynum) + struct schemobj *comp; + char *soughtpin; + int bynum; +{ + int npins; + register int i; + register struct graphsym_pininst *pi; + register char *pinid; + + npins = comp->compobj_graphsym->gs_npins; + for (pi = comp->compobj_pins, i = 0; i < npins; pi++, i++) { + if (bynum) + pinid = pi->pindef->gspd_pinnumber; + else + pinid = pi->pindef->gspd_pinname; + if (pinid && !strcmp(pinid, soughtpin)) + return(pi); + } + return(NULL); +} + +struct graphsym_pininst * +find_pin_by_coord(schem, x, y) + struct schem *schem; + register int x, y; +{ + register struct graphsym_pininst *pin; + + for (pin = schem->pininst_hash[hash_coord(x, y)]; pin; + pin = pin->nextinhash) + if (pin->x == x && pin->y == y) + return(pin); + return(NULL); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/rdschem.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,60 @@ +/* + * Schematic read-in main routine + */ + +#include <sys/types.h> +#include <stdio.h> +#include "schemstruct.h" +#include "parserint.h" + +extern char *malloc(); + +struct schem_parse_state schem_parse_state; + +struct schem * +read_schem(filename) + char *filename; +{ + FILE *f; + struct schem *schem; + register int i; + + f = fopen(filename, "r"); + if (!f) { + perror(filename); + exit(1); + } + + schem = (struct schem *) malloc(sizeof(struct schem)); + if (!schem) { + perror("malloc"); + exit(1); + } + bzero(schem, sizeof(struct schem)); + schem->obj_next = (struct schemobj *) schem; + schem->obj_prev = (struct schemobj *) schem; + schem->orig_filename = filename; + + schem_parse_state.schem = schem; + schem_parse_state.file = f; + schem_parse_state.lineno = 1; + schem_parse_state.pushback_token = 0; + + /* call the meat of the parser */ + rdschem_parse_schemline(); + do + i = rdschem_parse_object(); + while (!i); + + fclose(f); + return(schem); +} + +rdschem_error(msg) + char *msg; +{ + fprintf(stderr, "%s: line %d: %s\n", + schem_parse_state.schem->orig_filename, + schem_parse_state.lineno, msg); + exit(1); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/rdschem_lex.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,205 @@ +/* + * token lexer for the schematic parser + */ + +#include <sys/types.h> +#include <stdio.h> +#include <ctype.h> +#include <strings.h> +#include "schemstruct.h" +#include "parserint.h" + +extern char *malloc(); + +extern struct schem_parse_state schem_parse_state; + +static +my_getchar() +{ + register int c; + + c = getc(schem_parse_state.file); + if (c < 0) + return(c); + if (!isascii(c)) { + rdschem_error("non-ASCII character"); + exit(1); + } + if (iscntrl(c) && c != '\n' && c != '\t') { + rdschem_error("invalid control character"); + exit(1); + } + return(c); +} + +rdschem_token() +{ + register int c; + register char *cp; + register int len; + static char delims[] = "\n\"%(),;={}"; + + if (c = schem_parse_state.pushback_token) { + schem_parse_state.pushback_token = 0; + return(c); + } +loop: c = my_getchar(); + switch (c) { + case EOF: + return(0); + case ' ': + case '\t': + goto loop; + case '"': + yylex_qstr(); + return(QSTRING); + case '%': + do + c = my_getchar(); + while (c != EOF && c != '\n'); + if (c == EOF) + return(0); + /* FALL THRU */ + case '\n': + schem_parse_state.lineno++; + goto loop; + case '(': + case ')': + case ',': + case ';': + case '=': + case '{': + case '}': + return(c); + } + cp = schem_parse_state.string; + *cp++ = c; + for (len = 1; ; ) { + c = my_getchar(); + if (c == EOF || c == ' ' || c == '\t') + break; + if (index(delims, c)) { + ungetc(c, schem_parse_state.file); + break; + } + if (len >= MAXSTRING) + rdschem_error("text token is too long"); + *cp++ = c; + len++; + } + *cp = '\0'; + return(STRING); +} + +static +yylex_qstr() +{ + register int c; + register char *cp; + register int len; + + cp = schem_parse_state.string; + for (len = 0; ; ) { + c = my_getchar(); + if (c == EOF || c == '\n') +unterm: rdschem_error("unterminated quoted string"); + if (c == '"') + break; + if (c == '\\') { + c = my_getchar(); + if (c == EOF || c == '\n') + goto unterm; + } + if (len >= MAXSTRING) + rdschem_error("quoted string is too long"); + *cp++ = c; + len++; + } + *cp = '\0'; +} + +struct graphblock * +rdschem_graphblock(type) +{ + struct graphblock *blk; + register int c, n; + + blk = (struct graphblock *) malloc(sizeof(struct graphblock)); + if (!blk) { + perror("malloc"); + exit(1); + } + blk->type = type; + blk->lineno = schem_parse_state.lineno; + c = my_getchar(); + if (c == EOF) +badeof: rdschem_error("EOF in a graphical block"); + if (c == '\n') + schem_parse_state.lineno++; + else + ungetc(c, schem_parse_state.file); + blk->offset = ftell(schem_parse_state.file); + + for (n = 0; n >= 0; ) { + c = my_getchar(); + switch (c) { + case EOF: + goto badeof; + case '%': + for (;;) { + c = my_getchar(); + if (c == EOF) + goto badeof; + if (c == '\n') + break; + } + /* FALL THRU */ + case '\n': + schem_parse_state.lineno++; + continue; + case '(': + skip_over_ps_string(); + continue; + case ')': + rdschem_error("unmatched \')\' in a graphical block"); + case '{': + n++; + continue; + case '}': + n--; + continue; + } + } + blk->length = ftell(schem_parse_state.file) - blk->offset - 1; + return(blk); +} + +static +skip_over_ps_string() +{ + register int c, n; + + for (n = 1; n > 0; ) { + c = my_getchar(); + switch (c) { + case EOF: +badeof: rdschem_error("EOF in a PS string in a graphical block"); + case '\n': + schem_parse_state.lineno++; + continue; + case '(': + n++; + continue; + case ')': + n--; + continue; + case '\\': + c = my_getchar(); + if (c == EOF) + goto badeof; + if (c == '\n') + schem_parse_state.lineno++; + continue; + } + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/rdschem_parse.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,696 @@ +/* + * uschem schematic parser + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "schemstruct.h" +#include "parserint.h" + +extern char *copystr(); + +extern struct schem_parse_state schem_parse_state; + +extern struct schemobj *parser_alloc_obj(); +extern struct decoration *parser_alloc_decor(); +extern struct netpoint *parser_alloc_netpoint(); +extern struct xypair parse_drawing_size_spec(); +extern struct graphblock *rdschem_graphblock(); + +rdschem_parse_schemline() +{ + register int t; + struct xypair drawing_size; + + t = rdschem_token(); + if (t != STRING || strcmp(schem_parse_state.string, "Schem")) { + fprintf(stderr, + "%s is not a uschem schematic (doesn't begin with Schem)\n", + schem_parse_state.schem->orig_filename); + exit(1); + } + + t = rdschem_token(); + if (t != STRING) +inv: rdschem_error("Schem line: syntax error"); + if (!strcmp(schem_parse_state.string, "graph")) { + schem_parse_state.schem->is_graph = 1; + t = rdschem_token(); + if (t != STRING && t != QSTRING) + goto inv; + drawing_size = + parse_drawing_size_spec(schem_parse_state.string); + schem_parse_state.schem->graph_xsize = drawing_size.x; + schem_parse_state.schem->graph_ysize = drawing_size.y; + } else if (!strcmp(schem_parse_state.string, "nograph")) + schem_parse_state.schem->is_graph = 0; + else + goto inv; + + t = rdschem_token(); + if (t != ';') + goto inv; +} + +static struct decoration * +parse_decor_attr() +{ + register struct decoration *decor; + register int t; + + decor = parser_alloc_decor(DECOR_TYPE_ATTR); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(attribute definition decoration) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("attribute name may not be a null string"); + decor->decorattr_name = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != '=') + goto syntaxerr; + t = rdschem_token(); + if (t != STRING && t != QSTRING) + goto syntaxerr; + if (!schem_parse_state.string[0]) + rdschem_error("attribute value may not be a null string"); + decor->decorattr_value = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != ')') + goto syntaxerr; + return(decor); +} + +static struct decoration * +parse_decor_displayattr() +{ + register struct decoration *decor; + register int t; + + decor = parser_alloc_decor(DECOR_TYPE_DISPLAYATTR); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(DisplayAttr decoration) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("attribute name may not be a null string"); + decor->decordisp_attr = copystr(schem_parse_state.string); + decor->decordisp_x = parse_number(); + decor->decordisp_y = parse_number(); + decor->decordisp_ptsize = parse_number(); + decor->decordisp_rotate = parse_number(); + decor->decordisp_alignment = parse_number(); + t = rdschem_token(); + if (t != ';') + goto syntaxerr; + return(decor); +} + +static struct decoration * +parse_decor_displaynetname() +{ + register struct decoration *decor; + register int t; + + decor = parser_alloc_decor(DECOR_TYPE_DISPLAYNETNAME); + decor->decordisp_x = parse_number(); + decor->decordisp_y = parse_number(); + decor->decordisp_ptsize = parse_number(); + decor->decordisp_rotate = parse_number(); + decor->decordisp_alignment = parse_number(); + t = rdschem_token(); + if (t != ';') + rdschem_error("(DisplayNetName decoration) syntax error"); + return(decor); +} + +static struct decoration * +parse_decor_pintonet() +{ + register struct decoration *decor; + register int t; + + decor = parser_alloc_decor(DECOR_TYPE_PINTONET); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(PinToNet decoration) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("pin ID may not be a null string"); + if (!strcmp(schem_parse_state.string, "#")) + rdschem_error("pin ID \"#\" is invalid"); + decor->decorpincon_pin = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != STRING && t != QSTRING) + goto syntaxerr; + if (!schem_parse_state.string[0]) + rdschem_error("net name may not be a null string"); + decor->decorpincon_netname = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != ';') + goto syntaxerr; + return(decor); +} + +static struct decoration * +parse_decor_noconnect() +{ + register struct decoration *decor; + register int t; + + decor = parser_alloc_decor(DECOR_TYPE_NOCONNECT); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(NoConnect decoration) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("pin ID may not be a null string"); + if (!strcmp(schem_parse_state.string, "#")) + rdschem_error("pin ID \"#\" is invalid"); + decor->decorpincon_pin = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != ';') + goto syntaxerr; + return(decor); +} + +static struct decoration * +parse_decor_symonpin() +{ + register struct decoration *decor; + register int t; + + decor = parser_alloc_decor(DECOR_TYPE_SYMONPIN); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(SymOnPin decoration) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("pin ID may not be a null string"); + if (!strcmp(schem_parse_state.string, "#")) + rdschem_error("pin ID \"#\" is invalid"); + decor->decorpinsym_pin = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != STRING && t != QSTRING) + goto syntaxerr; + if (!schem_parse_state.string[0]) + rdschem_error("graphical symbol name may not be a null string"); + decor->decorpinsym_symname = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t == STRING && !strcmp(schem_parse_state.string, "mirror")) { + decor->decorpinsym_mirror = 1; + t = rdschem_token(); + } + if (t != ';') + goto syntaxerr; + return(decor); +} + +static struct decoration * +parse_decor_graphblock(type) +{ + register int t; + register struct decoration *decor; + register struct graphblock *blk; + + t = rdschem_token(); + if (t != '{') + rdschem_error("GraphBlockG/GraphBlockPS must be followed by '{'"); + blk = rdschem_graphblock(type); + decor = parser_alloc_decor(DECOR_TYPE_GRAPHBLOCK); + decor->decorgraph_body = blk; + schem_parse_state.schem->has_graphblocks = 1; + return(decor); +} + +static struct decoration * +parse_decor_comment() +{ + register int t; + register struct decoration *decor; + + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(Comment decoration) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("schematic comment may not be a null string"); + decor = parser_alloc_decor(DECOR_TYPE_COMMENT); + decor->decorcomment_text = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != ';') + goto syntaxerr; + return(decor); +} + +struct decoration * +rdschem_parse_decor_block() +{ + struct decoration *decor, *head, **tailp; + register int t; + char errbuf[256]; + + for (head = NULL, tailp = &head; ; ) { + t = rdschem_token(); + switch (t) { + case 0: + rdschem_error("EOF in a decoration block"); + case '(': + decor = parse_decor_attr(); + goto addit; + case ';': + /* "null statement" */ + continue; + case '}': + return(head); + } + if (t != STRING) + rdschem_error("syntax error: decoration keyword expected"); + if (!strcmp(schem_parse_state.string, "DisplayAttr")) + decor = parse_decor_displayattr(); + else if (!strcmp(schem_parse_state.string, "DisplayNetName")) + decor = parse_decor_displaynetname(); + else if (!strcmp(schem_parse_state.string, "PinToNet")) + decor = parse_decor_pintonet(); + else if (!strcmp(schem_parse_state.string, "NoConnect")) + decor = parse_decor_noconnect(); + else if (!strcmp(schem_parse_state.string, "SymOnPin")) + decor = parse_decor_symonpin(); + else if (!strcmp(schem_parse_state.string, "GraphBlockG")) + decor = parse_decor_graphblock(GRAPHBLOCK_TYPE_GSCHEM); + else if (!strcmp(schem_parse_state.string, "GraphBlockPS")) + decor = parse_decor_graphblock(GRAPHBLOCK_TYPE_PS); + else if (!strcmp(schem_parse_state.string, "Comment")) + decor = parse_decor_comment(); + else { + sprintf(errbuf, + "%s is not a recognized decoration keyword", + schem_parse_state.string); + rdschem_error(errbuf); + } +addit: *tailp = decor; + tailp = &decor->decor_next; + } +} + +rdschem_parse_object() +{ + register int t; + char errbuf[256]; + + t = rdschem_token(); + if (!t) /* EOF aka end of schematic */ + return(1); + if (t == ';') /* "null statement" */ + return(0); + if (t != STRING) + rdschem_error("syntax error: object keyword expected"); + + if (!strcmp(schem_parse_state.string, "Component")) + return(rdschem_parse_compinst()); + if (!strcmp(schem_parse_state.string, "GraphSym")) + return(rdschem_parse_graphsym()); + if (!strcmp(schem_parse_state.string, "Net")) + return(rdschem_parse_net()); + if (!strcmp(schem_parse_state.string, "GraphNet")) + return(rdschem_parse_graphnet()); + if (!strcmp(schem_parse_state.string, "NetLine")) + return(rdschem_parse_netline()); + if (!strcmp(schem_parse_state.string, "BusSeg")) + return(rdschem_parse_busseg()); + if (!strcmp(schem_parse_state.string, "GraphBlockG")) + return(rdschem_parse_graphblock_obj(GRAPHBLOCK_TYPE_GSCHEM)); + if (!strcmp(schem_parse_state.string, "GraphBlockPS")) + return(rdschem_parse_graphblock_obj(GRAPHBLOCK_TYPE_PS)); + if (!strcmp(schem_parse_state.string, "Comment")) + return(rdschem_parse_comment_obj()); + + sprintf(errbuf, "%s is not a recognized object keyword", + schem_parse_state.string); + rdschem_error(errbuf); +} + +rdschem_parse_compinst() +{ + register int t; + register struct schemobj *obj; + + obj = parser_alloc_obj(OBJTYPE_COMPINST); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(Component object) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("component instance name may not be a null string"); + obj->compobj_instname = copystr(schem_parse_state.string); + + t = rdschem_token(); + if (t == STRING && !strcmp(schem_parse_state.string, "graph")) { + obj->compobj_isgraph = 1; + t = rdschem_token(); + if (t != STRING && t != QSTRING) + goto syntaxerr; + if (!schem_parse_state.string[0]) + rdschem_error("graphical symbol name may not be a null string"); + obj->compobj_graph_symname = copystr(schem_parse_state.string); + obj->compobj_x = parse_number(); + obj->compobj_y = parse_number(); + t = rdschem_token(); + if (t == STRING && !strcmp(schem_parse_state.string, "rot")) { + obj->compobj_rotate = parse_number(); + t = rdschem_token(); + } + if (t == STRING && !strcmp(schem_parse_state.string, "mirror")){ + obj->compobj_mirror = 1; + t = rdschem_token(); + } + } + + if (t == '{') { + obj->obj_decorations = rdschem_parse_decor_block(); + t = rdschem_token(); + } + + if (t != ';') + goto syntaxerr; + parser_add_object(obj); + return(0); +} + +rdschem_parse_graphsym() +{ + register int t; + register struct schemobj *obj; + + obj = parser_alloc_obj(OBJTYPE_GRAPHSYM); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(GraphSym object) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("graphical symbol name may not be a null string"); + obj->compobj_graph_symname = copystr(schem_parse_state.string); + + obj->compobj_x = parse_number(); + obj->compobj_y = parse_number(); + t = rdschem_token(); + if (t == STRING && !strcmp(schem_parse_state.string, "rot")) { + obj->compobj_rotate = parse_number(); + t = rdschem_token(); + } + if (t == STRING && !strcmp(schem_parse_state.string, "mirror")) { + obj->compobj_mirror = 1; + t = rdschem_token(); + } + if (t == '{') { + obj->obj_decorations = rdschem_parse_decor_block(); + t = rdschem_token(); + } + + if (t != ';') + goto syntaxerr; + parser_add_object(obj); + return(0); +} + +rdschem_parse_net() +{ + register int t; + register struct schemobj *obj; + register struct netpoint *netpt; + struct netpoint *head, **tailp; + + obj = parser_alloc_obj(OBJTYPE_NET); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(Net object) syntax error"); + if (schem_parse_state.string[0]) + obj->netobj_netname = copystr(schem_parse_state.string); + + head = NULL; + tailp = &head; + for (;;) { + t = rdschem_token(); + if (t == ';' || t == '{') + break; + if (t != STRING && t != QSTRING) + goto syntaxerr; + if (!schem_parse_state.string[0]) + goto syntaxerr; + netpt = parser_alloc_netpoint(NETPT_TYPE_PIN); + netpt->netpt_pin_nameref = copystr(schem_parse_state.string); + *tailp = netpt; + tailp = &netpt->netpt_next; + } + obj->netobj_points = head; + + if (t == '{') { + obj->obj_decorations = rdschem_parse_decor_block(); + t = rdschem_token(); + } + if (t != ';') + goto syntaxerr; + + if (obj->netobj_points) + parser_add_object(obj); + else { + fprintf(stderr, "%s: line %d: null Net object ignored\n", + schem_parse_state.schem->orig_filename, + schem_parse_state.lineno); + free(obj); + } + return(0); +} + +static struct xypair +parse_coord_pair() +{ + register int t; + struct xypair retval; + + retval.x = parse_number(); + t = rdschem_token(); + if (t != ',') +syntaxerr: rdschem_error("syntax error in coordinate pair"); + retval.y = parse_number(); + t = rdschem_token(); + if (t != ')') + goto syntaxerr; + return(retval); +} + +static struct netpoint * +parse_graphnet_point() +{ + register int t; + register struct netpoint *netpt; + struct xypair coord_pair; + + t = rdschem_token(); + if (t == '(') { + netpt = parser_alloc_netpoint(NETPT_TYPE_POINT); + coord_pair = parse_coord_pair(); + netpt->netpt_x = coord_pair.x; + netpt->netpt_y = coord_pair.y; + netpt->netpt_coord_valid = 1; + return(netpt); + } else if (t == STRING && !strcmp(schem_parse_state.string, "Pin")) { + netpt = parser_alloc_netpoint(NETPT_TYPE_PIN); + t = rdschem_token(); + if (t == '(') { + coord_pair = parse_coord_pair(); + netpt->netpt_x = coord_pair.x; + netpt->netpt_y = coord_pair.y; + netpt->netpt_coord_valid = 1; + t = rdschem_token(); + } + if (t == '=') { + t = rdschem_token(); + if (t != STRING && t != QSTRING || + !schem_parse_state.string[0]) + rdschem_error("syntax error: pin name reference expected"); + netpt->netpt_pin_nameref = + copystr(schem_parse_state.string); + } else if (netpt->netpt_coord_valid) + schem_parse_state.pushback_token = t; + else + rdschem_error("syntax error: Pin must be followed by coordinates or name reference"); + return(netpt); + } else if (t == STRING && !strcmp(schem_parse_state.string, "Tjoin")) { + netpt = parser_alloc_netpoint(NETPT_TYPE_TJOIN); + t = rdschem_token(); + if (t != '(') + rdschem_error("syntax error: Tjoin must be followed by coordinates"); + coord_pair = parse_coord_pair(); + netpt->netpt_x = coord_pair.x; + netpt->netpt_y = coord_pair.y; + netpt->netpt_coord_valid = 1; + return(netpt); + } else if (t == STRING && !strcmp(schem_parse_state.string, "Pseudo")) { + netpt = parser_alloc_netpoint(NETPT_TYPE_PSEUDO); + t = rdschem_token(); + if (t != '(') + rdschem_error("syntax error: Pseudo must be followed by coordinates"); + coord_pair = parse_coord_pair(); + netpt->netpt_x = coord_pair.x; + netpt->netpt_y = coord_pair.y; + netpt->netpt_coord_valid = 1; + return(netpt); + } + schem_parse_state.pushback_token = t; + return(NULL); +} + +rdschem_parse_graphnet() +{ + register int t; + register struct schemobj *obj; + register struct netpoint *netpt; + struct netpoint *head, **tailp; + + obj = parser_alloc_obj(OBJTYPE_GRAPHNET); + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(GraphNet object) syntax error"); + if (schem_parse_state.string[0]) + obj->netobj_netname = copystr(schem_parse_state.string); + + head = NULL; + tailp = &head; + for (;;) { + netpt = parse_graphnet_point(); + if (!netpt) + break; + *tailp = netpt; + tailp = &netpt->netpt_next; + } + obj->netobj_points = head; + + t = rdschem_token(); + if (t == '{') { + obj->obj_decorations = rdschem_parse_decor_block(); + t = rdschem_token(); + } + if (t != ';') + goto syntaxerr; + + if (obj->netobj_points) + parser_add_object(obj); + else { + fprintf(stderr, "%s: line %d: null GraphNet object ignored\n", + schem_parse_state.schem->orig_filename, + schem_parse_state.lineno); + free(obj); + } + return(0); +} + +rdschem_parse_netline() +{ + register int t; + register struct schemobj *obj; + struct xypair coord_pair; + + obj = parser_alloc_obj(OBJTYPE_NETLINE); + + t = rdschem_token(); + if (t != '(') +syntaxerr: rdschem_error("(NetLine object) syntax error"); + coord_pair = parse_coord_pair(); + obj->lineobj_x1 = coord_pair.x; + obj->lineobj_y1 = coord_pair.y; + t = rdschem_token(); + if (t != '(') + goto syntaxerr; + coord_pair = parse_coord_pair(); + obj->lineobj_x2 = coord_pair.x; + obj->lineobj_y2 = coord_pair.y; + + t = rdschem_token(); + if (t == '{') { + obj->obj_decorations = rdschem_parse_decor_block(); + t = rdschem_token(); + } + if (t != ';') + goto syntaxerr; + parser_add_object(obj); + return(0); +} + +rdschem_parse_busseg() +{ + register int t; + register struct schemobj *obj; + struct xypair coord_pair; + + obj = parser_alloc_obj(OBJTYPE_BUSSEG); + + t = rdschem_token(); + if (t != '(') +syntaxerr: rdschem_error("(BusSeg object) syntax error"); + coord_pair = parse_coord_pair(); + obj->lineobj_x1 = coord_pair.x; + obj->lineobj_y1 = coord_pair.y; + t = rdschem_token(); + if (t != '(') + goto syntaxerr; + coord_pair = parse_coord_pair(); + obj->lineobj_x2 = coord_pair.x; + obj->lineobj_y2 = coord_pair.y; + + t = rdschem_token(); + if (t == '{') { + obj->obj_decorations = rdschem_parse_decor_block(); + t = rdschem_token(); + } + if (t != ';') + goto syntaxerr; + parser_add_object(obj); + return(0); +} + +rdschem_parse_graphblock_obj(type) +{ + register int t; + register struct schemobj *obj; + register struct graphblock *blk; + + t = rdschem_token(); + if (t != '{') + rdschem_error("GraphBlockG/GraphBlockPS must be followed by '{'"); + blk = rdschem_graphblock(type); + obj = parser_alloc_obj(OBJTYPE_GRAPHBLOCK); + obj->graphblockobj_body = blk; + parser_add_object(obj); + schem_parse_state.schem->has_graphblocks = 1; + return(0); +} + +rdschem_parse_comment_obj() +{ + register int t; + register struct schemobj *obj; + + t = rdschem_token(); + if (t != STRING && t != QSTRING) +syntaxerr: rdschem_error("(Comment object) syntax error"); + if (!schem_parse_state.string[0]) + rdschem_error("schematic comment may not be a null string"); + obj = parser_alloc_obj(OBJTYPE_COMMENT); + obj->commentobj_text = copystr(schem_parse_state.string); + t = rdschem_token(); + if (t != ';') + goto syntaxerr; + parser_add_object(obj); + return(0); +} + +static int +parse_number() +{ + register int t; + char errbuf[256]; + + t = rdschem_token(); + if (t != STRING) + rdschem_error("syntax error (number expected)"); + if (!string_is_valid_decnum(schem_parse_state.string)) { + sprintf(errbuf, "\"%s\" is not a valid decimal number", + schem_parse_state.string); + rdschem_error(errbuf); + } + return(atoi(schem_parse_state.string)); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/schemobj.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,37 @@ +/* + * Schematic object utility functions + */ + +#include <sys/types.h> +#include <stdio.h> +#include "schemstruct.h" + +schemobj_insert_after(oldobj, newobj) + register struct schemobj *oldobj, *newobj; +{ + newobj->obj_next = oldobj->obj_next; + newobj->obj_prev = oldobj; + oldobj->obj_next = newobj; + newobj->obj_next->obj_prev = newobj; +} + +schemobj_insert_before(oldobj, newobj) + register struct schemobj *oldobj, *newobj; +{ + newobj->obj_next = oldobj; + newobj->obj_prev = oldobj->obj_prev; + oldobj->obj_prev = newobj; + newobj->obj_prev->obj_next = newobj; +} + +schemobj_unlink(delobj) + register struct schemobj *delobj; +{ + if (!delobj->obj_type) { + fprintf(stderr, + "Fatal internal error: attempt to unlink sentinel object\n"); + abort(); + } + delobj->obj_prev->obj_next = delobj->obj_next; + delobj->obj_next->obj_prev = delobj->obj_prev; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/schemstruct.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,196 @@ +/* + * data structures representing a schematic in memory + */ + +#define OBJTYPE_SENTINEL 0x00 +#define OBJTYPE_COMPINST 0x01 +#define OBJTYPE_GRAPHSYM 0x02 +#define OBJTYPE_NET 0x03 +#define OBJTYPE_GRAPHNET 0x04 +#define OBJTYPE_NETLINE 0x05 +#define OBJTYPE_BUSSEG 0x06 +#define OBJTYPE_GRAPHBLOCK 0x07 +#define OBJTYPE_COMMENT 0x08 +#define OBJTYPE_MAX 0x08 + +struct schem { + /* the first 3 fields must match struct schemobj to serve as sentinel */ + struct schemobj *obj_next; + struct schemobj *obj_prev; + int obj_type; + /* we're free from here onward */ + char *orig_filename; + int is_graph; + int graph_xsize; + int graph_ysize; + int has_graphblocks; + struct schemobj **compinst_hash; + struct graphsym_pininst **pininst_hash; +}; + +struct schemobj { + struct schemobj *obj_next; + struct schemobj *obj_prev; + int obj_type; + int obj_lineno; + struct decoration *obj_decorations; + /* the rest differs by type */ + union { + struct { /* Component and GraphSym */ + char *instname; + struct component *mclcomp; + int is_graph; + char *graph_symname; + struct graphsym *graphsym; + int x; + int y; + int rotate; + int mirror; + struct schemobj *next_in_hash; + struct graphsym_pininst *pin_instances; + } comp; + struct { /* Net and GraphNet */ + char *netname; + struct netpoint *points; + struct schemobj *grouphead; + int has_forcenet_syms; + } net; + struct { /* NetLine and BusSeg */ + int x1; + int y1; + int x2; + int y2; + } netline; + struct graphblock *graphblock_body; + char *comment_text; + } bytype; +}; + +/* for Component and GraphSym */ +#define compobj_instname bytype.comp.instname +#define compobj_mclcomp bytype.comp.mclcomp +#define compobj_isgraph bytype.comp.is_graph +#define compobj_graph_symname bytype.comp.graph_symname +#define compobj_graphsym bytype.comp.graphsym +#define compobj_x bytype.comp.x +#define compobj_y bytype.comp.y +#define compobj_rotate bytype.comp.rotate +#define compobj_mirror bytype.comp.mirror +#define compobj_nextinhash bytype.comp.next_in_hash +#define compobj_pins bytype.comp.pin_instances + +/* for Net and GraphNet */ +#define netobj_netname bytype.net.netname +#define netobj_points bytype.net.points +#define netobj_grouphead bytype.net.grouphead +#define netobj_forcenets bytype.net.has_forcenet_syms + +/* for NetLine and BusSeg */ +#define lineobj_x1 bytype.netline.x1 +#define lineobj_y1 bytype.netline.y1 +#define lineobj_x2 bytype.netline.x2 +#define lineobj_y2 bytype.netline.y2 + +/* for GraphBlocks and Comments */ +#define graphblockobj_body bytype.graphblock_body +#define commentobj_text bytype.comment_text + +struct netpoint { + struct netpoint *netpt_next; + int netpt_type; + char *netpt_pin_nameref; + int netpt_x; + int netpt_y; + int netpt_coord_valid; + struct schemobj *netpt_tjoin_to; +}; + +#define NETPT_TYPE_POINT 0 +#define NETPT_TYPE_PIN 1 +#define NETPT_TYPE_TJOIN 2 +#define NETPT_TYPE_PSEUDO 3 + +struct decoration { + struct decoration *decor_next; + int decor_type; + int decor_lineno; + /* the rest differs by type */ + union { + struct { + char *name; + char *value; + } attr; + struct { + char *attr; + int x; + int y; + int ptsize; + int rotate; + int alignment; + } display; + struct { + char *pin; + char *netname; + } pintonet; + struct { + char *pin; + char *symname; + struct graphsym *graphsym; + int mirror; + } symonpin; + struct graphblock *graphblock_body; + char *comment_text; + } bytype; +}; + +#define DECOR_TYPE_ATTR 0x01 +#define DECOR_TYPE_DISPLAYATTR 0x02 +#define DECOR_TYPE_DISPLAYNETNAME 0x03 +#define DECOR_TYPE_GRAPHBLOCK 0x04 +#define DECOR_TYPE_COMMENT 0x05 +#define DECOR_TYPE_PINTONET 0x06 +#define DECOR_TYPE_SYMONPIN 0x07 +#define DECOR_TYPE_NOCONNECT 0x08 + +#define decorattr_name bytype.attr.name +#define decorattr_value bytype.attr.value + +#define decordisp_attr bytype.display.attr +#define decordisp_x bytype.display.x +#define decordisp_y bytype.display.y +#define decordisp_ptsize bytype.display.ptsize +#define decordisp_rotate bytype.display.rotate +#define decordisp_alignment bytype.display.alignment + +#define decorpincon_pin bytype.pintonet.pin +#define decorpincon_netname bytype.pintonet.netname + +#define decorpinsym_pin bytype.symonpin.pin +#define decorpinsym_symname bytype.symonpin.symname +#define decorpinsym_gs bytype.symonpin.graphsym +#define decorpinsym_mirror bytype.symonpin.mirror + +#define decorgraph_body bytype.graphblock_body +#define decorcomment_text bytype.comment_text + +struct graphblock { + int type; + off_t offset; + size_t length; + int lineno; +}; + +#define GRAPHBLOCK_TYPE_PS 0 +#define GRAPHBLOCK_TYPE_GSCHEM 1 + +/* + * This doesn't really belong here, but I couldn't find a better place + * for this structure definition: I want to make this table available + * to the writer as well. + */ + +struct drawing_size_kwtab { + char *keyword; + int xdim; + int ydim; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/writerint.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,10 @@ +/* + * These data structures are internal to the schematic writing process + * and persist only while that operation is in progress. + */ + +struct schem_write_state { + FILE *outf; + FILE *orig_file; + struct schem *schem; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/libuschem/wrschem.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,344 @@ +/* + * Schematic write-out + */ + +#include <sys/types.h> +#include <stdio.h> +#include "schemstruct.h" +#include "writerint.h" + +extern FILE *reopen_schem_for_graphblocks(); + +extern struct drawing_size_kwtab drawing_size_keywords[]; + +struct schem_write_state schem_write_state; + +write_schem(schem, outf) + struct schem *schem; + FILE *outf; +{ + register struct schemobj *obj; + + schem_write_state.schem = schem; + schem_write_state.outf = outf; + schem_write_state.orig_file = reopen_schem_for_graphblocks(schem); + wrschem_emit_schemline(schem); + putc('\n', outf); + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) + wrschem_emit_object(obj); + + if (schem_write_state.orig_file) + fclose(schem_write_state.orig_file); +} + +wrschem_emit_schemline(schem) + register struct schem *schem; +{ + register struct drawing_size_kwtab *kwp; + + if (!schem->is_graph) { + fprintf(schem_write_state.outf, "Schem nograph;\n"); + return; + } + for (kwp = drawing_size_keywords; kwp->keyword; kwp++) + if (schem->graph_xsize == kwp->xdim && + schem->graph_ysize == kwp->ydim) { + fprintf(schem_write_state.outf, "Schem graph %s;\n", + kwp->keyword); + return; + } + fprintf(schem_write_state.outf, "Schem graph %dx%d;\n", + schem->graph_xsize, schem->graph_ysize); +} + +wrschem_emit_qstring(str) + char *str; +{ + register char *cp; + register int c; + + putc('\"', schem_write_state.outf); + for (cp = str; c = *cp; cp++) { + if (c == '\"' || c == '\\') + putc('\\', schem_write_state.outf); + putc(c, schem_write_state.outf); + } + putc('\"', schem_write_state.outf); +} + +wrschem_emit_string(str) + register char *str; +{ + if (schem_string_needs_quote(str)) + wrschem_emit_qstring(str); + else + fputs(str, schem_write_state.outf); +} + +schem_string_needs_quote(str) + char *str; +{ + register char *cp; + register int c; + + cp = str; + if (!*cp) + return(1); /* null strings can only be quoted */ + while (c = *cp++) + switch (c) { + case ' ': + case '\t': + case '\n': + case '"': + case '%': + case '(': + case ')': + case ',': + case ';': + case '=': + case '{': + case '}': + return(1); + } + return(0); +} + +wrschem_emit_object(obj) + register struct schemobj *obj; +{ + switch (obj->obj_type) { + case OBJTYPE_COMPINST: + fputs("Component ", schem_write_state.outf); + wrschem_emit_string(obj->compobj_instname); + if (obj->compobj_isgraph) { + fputs(" graph ", schem_write_state.outf); + wrschem_emit_qstring(obj->compobj_graph_symname); + fprintf(schem_write_state.outf, " %d %d", + obj->compobj_x, obj->compobj_y); + if (obj->compobj_rotate) + fprintf(schem_write_state.outf, " rot %d", + obj->compobj_rotate); + if (obj->compobj_mirror) + fputs(" mirror", schem_write_state.outf); + } + if (obj->obj_decorations) + wrschem_emit_decor_block(obj); + fputs(";\n", schem_write_state.outf); + return; + + case OBJTYPE_GRAPHSYM: + fputs("GraphSym ", schem_write_state.outf); + wrschem_emit_qstring(obj->compobj_graph_symname); + fprintf(schem_write_state.outf, " %d %d", + obj->compobj_x, obj->compobj_y); + if (obj->compobj_rotate) + fprintf(schem_write_state.outf, " rot %d", + obj->compobj_rotate); + if (obj->compobj_mirror) + fputs(" mirror", schem_write_state.outf); + if (obj->obj_decorations) + wrschem_emit_decor_block(obj); + fputs(";\n", schem_write_state.outf); + return; + + case OBJTYPE_NET: + wrschem_emit_net(obj, "Net", 0); + return; + + case OBJTYPE_GRAPHNET: + wrschem_emit_net(obj, "GraphNet", 1); + return; + + case OBJTYPE_NETLINE: + fprintf(schem_write_state.outf, "NetLine (%d,%d) (%d,%d)", + obj->lineobj_x1, obj->lineobj_y1, + obj->lineobj_x2, obj->lineobj_y2); + if (obj->obj_decorations) + wrschem_emit_decor_block(obj); + fputs(";\n", schem_write_state.outf); + return; + + case OBJTYPE_BUSSEG: + fprintf(schem_write_state.outf, "BusSeg (%d,%d) (%d,%d)", + obj->lineobj_x1, obj->lineobj_y1, + obj->lineobj_x2, obj->lineobj_y2); + if (obj->obj_decorations) + wrschem_emit_decor_block(obj); + fputs(";\n", schem_write_state.outf); + return; + + case OBJTYPE_GRAPHBLOCK: + wrschem_emit_graphblock(obj->graphblockobj_body); + return; + + case OBJTYPE_COMMENT: + fputs("Comment ", schem_write_state.outf); + wrschem_emit_qstring(obj->commentobj_text); + fputs(";\n", schem_write_state.outf); + return; + + default: + fprintf(stderr, + "Fatal internal error: unknown obj type in wrschem_emit_object()\n"); + abort(); + } +} + +/* for Net and GraphNet */ +wrschem_emit_net(obj, keyword, isgraphnet) + register struct schemobj *obj; + char *keyword; + int isgraphnet; +{ + register struct netpoint *netpt; + + fprintf(schem_write_state.outf, "%s ", keyword); + if (obj->netobj_grouphead && obj->netobj_grouphead->netobj_netname) + wrschem_emit_string(obj->netobj_grouphead->netobj_netname); + else if (obj->netobj_netname) + wrschem_emit_string(obj->netobj_netname); + else + fputs("\"\"", schem_write_state.outf); + + for (netpt = obj->netobj_points; netpt; netpt = netpt->netpt_next) { + putc(' ', schem_write_state.outf); + switch (netpt->netpt_type) { + case NETPT_TYPE_POINT: + fprintf(schem_write_state.outf, "(%d,%d)", + netpt->netpt_x, netpt->netpt_y); + break; + case NETPT_TYPE_PIN: + if (isgraphnet) { + fputs("Pin", schem_write_state.outf); + if (netpt->netpt_coord_valid) + fprintf(schem_write_state.outf, + "(%d,%d)", + netpt->netpt_x, netpt->netpt_y); + if (netpt->netpt_pin_nameref) + putc('=', schem_write_state.outf); + } + if (netpt->netpt_pin_nameref) + wrschem_emit_string(netpt->netpt_pin_nameref); + break; + case NETPT_TYPE_TJOIN: + fprintf(schem_write_state.outf, "Tjoin(%d,%d)", + netpt->netpt_x, netpt->netpt_y); + break; + case NETPT_TYPE_PSEUDO: + fprintf(schem_write_state.outf, "Pseudo(%d,%d)", + netpt->netpt_x, netpt->netpt_y); + break; + } + } + + if (obj->obj_decorations) + wrschem_emit_decor_block(obj); + fputs(";\n", schem_write_state.outf); +} + +wrschem_emit_graphblock(blk) + struct graphblock *blk; +{ + char *keyword; + + switch (blk->type) { + case GRAPHBLOCK_TYPE_PS: + keyword = "GraphBlockPS"; + break; + case GRAPHBLOCK_TYPE_GSCHEM: + keyword = "GraphBlockG"; + break; + default: + fprintf(stderr, + "Fatal internal error: unknown type in wrschem_emit_graphblock()\n"); + abort(); + } + fprintf(schem_write_state.outf, "%s {\n", keyword); + write_graphblock_to_file(blk, schem_write_state.orig_file, + schem_write_state.outf); + fputs("}\n", schem_write_state.outf); +} + +wrschem_emit_decor_block(obj) + struct schemobj *obj; +{ + register struct decoration *decor; + + fputs(" {\n", schem_write_state.outf); + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) + wrschem_emit_decor(decor); + putc('}', schem_write_state.outf); +} + +wrschem_emit_decor(decor) + register struct decoration *decor; +{ + switch (decor->decor_type) { + case DECOR_TYPE_ATTR: + fputs("\t(", schem_write_state.outf); + wrschem_emit_string(decor->decorattr_name); + putc('=', schem_write_state.outf); + wrschem_emit_qstring(decor->decorattr_value); + fputs(")\n", schem_write_state.outf); + return; + + case DECOR_TYPE_DISPLAYATTR: + fputs("\tDisplayAttr ", schem_write_state.outf); + wrschem_emit_string(decor->decordisp_attr); + fprintf(schem_write_state.outf, " %d %d %d %d %d;\n", + decor->decordisp_x, decor->decordisp_y, + decor->decordisp_ptsize, decor->decordisp_rotate, + decor->decordisp_alignment); + return; + + case DECOR_TYPE_DISPLAYNETNAME: + fprintf(schem_write_state.outf, + "\tDisplayNetName %d %d %d %d %d;\n", + decor->decordisp_x, decor->decordisp_y, + decor->decordisp_ptsize, decor->decordisp_rotate, + decor->decordisp_alignment); + return; + + case DECOR_TYPE_PINTONET: + fputs("\tPinToNet ", schem_write_state.outf); + wrschem_emit_string(decor->decorpincon_pin); + putc(' ', schem_write_state.outf); + wrschem_emit_string(decor->decorpincon_netname); + fputs(";\n", schem_write_state.outf); + return; + + case DECOR_TYPE_NOCONNECT: + fputs("\tNoConnect ", schem_write_state.outf); + wrschem_emit_string(decor->decorpincon_pin); + fputs(";\n", schem_write_state.outf); + return; + + case DECOR_TYPE_SYMONPIN: + fputs("\tSymOnPin ", schem_write_state.outf); + wrschem_emit_string(decor->decorpinsym_pin); + putc(' ', schem_write_state.outf); + wrschem_emit_qstring(decor->decorpinsym_symname); + if (decor->decorpinsym_mirror) + fputs(" mirror", schem_write_state.outf); + fputs(";\n", schem_write_state.outf); + return; + + case DECOR_TYPE_GRAPHBLOCK: + putc('\t', schem_write_state.outf); + wrschem_emit_graphblock(decor->decorgraph_body); + return; + + case DECOR_TYPE_COMMENT: + fputs("\tComment ", schem_write_state.outf); + wrschem_emit_qstring(decor->decorcomment_text); + fputs(";\n", schem_write_state.outf); + return; + + default: + fprintf(stderr, + "Fatal internal error: unknown decoration type in wrschem_emit_decor()\n"); + abort(); + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/man/ueda-cutelements.1 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,20 @@ +.TH CUTELEMENTS 1 "" "International Free Computing Task Force" \ +"uEDA Suite Documentation" +.SH NAME +ueda-cutelements \- extract elements from a PCB layout file +.SH SYNOPSIS +.B ueda-cutelements +[ +.I pcbfile +] +.SH DESCRIPTION +.PP +This program reads a PCB layout file (or any file containing concatenated +PCB elements, even if it isn't a complete and valid layout file) and extracts +all elements contained therein. +If no source file is specified, the standard input is read instead. +.PP +All element files are created in the current directory and named after the +element name in the source PCB. +.SH SEE ALSO +ueda-getfps(1)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/man/ueda-getfps.1 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,81 @@ +.TH GETFPS 1 "" "International Free Computing Task Force" \ +"uEDA Suite Documentation" +.SH NAME +ueda-getfps \- fetch all footprints for the board +.SH SYNOPSIS +.B ueda-getfps +[ +.B \-c +] [ +.B \-h +] +.B | +.B ueda-runm4 +.SH DESCRIPTION +.PP +.I Ueda-getfps +reads the MCL, extracts all +.B footprint= +attributes and generates a set of +.IR m4 (1) +macro calls which then needs to be run through +.IR ueda-runm4 (1). +The complete +.B +ueda-getfps | ueda-runm4 +pipeline produces the complete set of PCB elements (footprints) for the board. +.PP +The +.B \-c +option instructs +.I ueda-getfps +to check the design for the completeness of the pre-layout information. +Normally components in the MCL which do not have a +.B footprint= +attribute or have it set to +.B TBD +are ignored, but the +.B \-c +option causes a warning message to be issued instead. +.PP +The +.B \-h +option causes +a blank PCB template to be prepended as a header before the PCB elements +so that the resulting pipeline output is a complete and valid PCB layout file. +.SH FILES +MCL Master Component List +.SH SEE ALSO +ueda-cutelements(1), ueda-instfileelem(1), ueda-runm4(1) +.br +Introductory uEDA documentation +.SH DIAGNOSTICS +/usr/local/eda/ifctf-part-lib/m4-fp: bad directory +.in +8 +The required IFCTF part library is not installed correctly. +.in -8 +/usr/local/eda/file-element-dirs: No such file or directory +.in +8 +If a requested footprint is not found in the M4 library, the M4 code +automatically invokes +.IR ueda-instfileelem (1) +to look for it in the file element directories. +If the latter are not installed, you see this rather cryptic error message. +.in -8 +No footprint named \fIxxx\fP +.in +8 +The requested footprint could not be found, neither in M4 nor in the file +element libraries. +.in -8 +\fIXX\fP has no footprint +.br +\fIXX\fP: footprint=TBD +.in +8 +These diagnostics are produced with the +.B \-c +option and should be self-explanatory. +.in -8 +.SH BUGS +Exposing the +.IR ueda-getfps | ueda-runm4 +pipeline to the user is ugly.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/man/ueda-instfileelem.1 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,37 @@ +.TH INSTFILEELEM 1 "" "International Free Computing Task Force" \ +"uEDA Suite Documentation" +.SH NAME +ueda-instfileelem \- instantiate a file element +.SH SYNOPSIS +.B ueda-instfileelem +.I fp +.I refdes +[ +.I value +] +.SH DESCRIPTION +This program locates PCB footprint named +.I fp +in the file element libraries and emits an instantiation of it on the standard +output with the name and value fields filled in with the +.I refdes +and +.I value +arguments, respectively. +.SH FILES +/usr/local/eda/file-element-dirs +.PP +This file must contain the list of pathnames of directories containing file +elements, one per line. +Each listed directory must contain footprint (element) files, one footprint +in each file. +If a footprint named +.I xxx +is sought, its file must be named +.I xxx +or +.IR xxx.fp . +.SH SEE ALSO +ueda-getfps(1) +.SH DIAGNOSTICS +The messages printed on errors should be self-explanatory.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/man/ueda-mkbom.1 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,73 @@ +.TH MKBOM 1 "" "International Free Computing Task Force" \ +"uEDA Suite Documentation" +.SH NAME +ueda-mkbom \- generate a procurement-oriented BOM +.SH SYNOPSIS +.B ueda-mkbom +[ +.B \-c +] [ +.B \-p +.I popopt +] [ +.B \-r +] +.SH DESCRIPTION +.PP +This program generates the procurement-oriented BOM as explained in the +document +.IR "Bill of Materials (BOM) handling in uEDA" . +.PP +The +.B \-c +option instructs +.I ueda-mkbom +to check the design for the completeness of the parts information. +The procurement-oriented BOM contains only those components that have been +reduced to parts. +If a component has not been reduced to a part yet, +.I ueda-mkbom +ignores it; the +.B \-c +option causes a warning message to be emitted when this happens. +.PP +The +.B \-p +option specifies the population option for which the BOM should be produced. +.I Popopt +is either a comma-separated list of population group numbers to be included +or the keyword +.BR all . +The latter requests that all components be included, even those which have a +.B +population_option=NO +attribute specified. +The default is equivalent to +.BR \-p0 . +.PP +The +.B \-r +option causes a list of reference designators to be emitted for each part in +the BOM indicating which components use that part. +.SH FILES +MCL Master Component List +.SH SEE ALSO +ueda-shortbom(1) +.br +.I +Bill of Materials (BOM) handling in uEDA +.SH DIAGNOSTICS +\fIXX\fP has no part defined +.in +8 +These diagnostics are produced with the +.B \-c +option and should be self-explanatory. +.in -8 +part \fIXX\fP: no identifying information for the BOM +.in +8 +See the +.I +uEDA Master Component List (MCL) description +for explanation of the attributes required by +.IR ueda-mkbom . +.in -8
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/man/ueda-runm4.1 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,49 @@ +.TH RUNM4 1 "" "International Free Computing Task Force" \ +"uEDA Suite Documentation" +.SH NAME +ueda-runm4 \- run m4 with the PCB footprint library loaded +.SH SYNOPSIS +.B ueda-runm4 +.SH DESCRIPTION +.PP +.I Ueda-runm4 +is a simple +.IR sh (1) +script that invokes +.IR m4 (1) +with all macros of the IFCTF PCB footprint library loaded and available +for use. +Input may be given on stdin which uses these macros and output will be +produced on stdout with all macros correctly expanded. +.PP +.I Ueda-runm4 +is normally run as a post-processor for +.IR ueda-getfps (1). +.SH FILES +/usr/local/eda/ifctf-part-lib IFCTF part library +.SH SEE ALSO +ueda-getfps(1), ueda-instfileelem(1) +.br +Introductory uEDA documentation +.SH DIAGNOSTICS +/usr/local/eda/ifctf-part-lib/m4-fp: bad directory +.in +8 +The required IFCTF part library is not installed correctly. +.in -8 +/usr/local/eda/file-element-dirs: No such file or directory +.in +8 +If a requested footprint is not found in the M4 library, the M4 code +automatically invokes +.IR ueda-instfileelem (1) +to look for it in the file element directories. +If the latter are not installed, you see this rather cryptic error message. +.in -8 +No footprint named \fIxxx\fP +.in +8 +The requested footprint could not be found, neither in M4 nor in the file +element libraries. +.in -8 +.SH BUGS +The M4 code in the IFCTF part library uses some features only present +in the 4.3BSD-Quasijarus version of +.IR m4 (1).
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/man/ueda-shortbom.1 Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,69 @@ +.TH SHORTBOM 1 "" "International Free Computing Task Force" \ +"uEDA Suite Documentation" +.SH NAME +ueda-shortbom \- generate a short BOM from the MCL +.SH SYNOPSIS +.B ueda-shortbom +[ +.B \-a +] [ +.B \-p +.I popopt +] [ +.B \-s +.I sep +] [ +.B \-t +] +.SH DESCRIPTION +.PP +This program generates a short BOM as explained in the +document +.IR "Bill of Materials (BOM) handling in uEDA" . +.PP +The default output is intended for a display or printer with fixed +character spacing; ASCII space characters are inserted between columns. +The number of spaces inserted is determined by the width of the widest +entry in each column plus the column separation. +The latter defaults to 2 spaces but can be changed with the +.B \-s +option. +.PP +The +.B \-t +option selects an alternative output format in which the columns are +separated by a single ASCII tab character. +This format is ideal for feeding to +.IR tbl (1) +and ultimately to +.IR troff (1). +The column headings are also suppressed in this output format on the +assumption that they can be made prettier in the post-processing. +.PP +The +.B \-p +option specifies the population option for which the BOM should be produced. +.I Popopt +is either a comma-separated list of population group numbers to be included +or the keyword +.BR all . +The latter requests that all components be included, even those which have a +.B +population_option=NO +attribute specified. +The default is equivalent to +.BR \-p0 . +.PP +The +.B \-a +option requests the generation of an assembly BOM. +The assembly BOM differs from the corresponding ``regular'' short BOM in that if +a component is to be socketed, the part information emitted is for the socket +rather than the component to be pushed into it. +.SH FILES +MCL Master Component List +.SH SEE ALSO +ueda-mkbom(1) +.br +.I +Bill of Materials (BOM) handling in uEDA
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/mclutils/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,3 @@ +getfps +mkbom +shortbom
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/mclutils/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,21 @@ +CFLAGS= -O +PROGS= getfps mkbom shortbom +LIBUEDA=../libueda/libueda.a +BINDIR= /usr/local + +all: ${PROGS} + +${PROGS}: ${LIBUEDA} + ${CC} ${CFLAGS} -o $@ $@.o ${LIBUEDA} + +install: + install -c -o bin -g bin -m 755 getfps ${BINDIR}/ueda-getfps + install -c -o bin -g bin -m 755 mkbom ${BINDIR}/ueda-mkbom + install -c -o bin -g bin -m 755 shortbom ${BINDIR}/ueda-shortbom + +clean: + rm -f *.[ao] a.out core errs ${PROGS} + +getfps: getfps.o +mkbom: mkbom.o +shortbom: shortbom.o
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/mclutils/getfps.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,79 @@ +/* + * This program "gets" all footprints for the board. The footprint attributes + * are extracted from the MCL and a set of M4 macro calls is emitted on stdout + * which when run through M4 will produce all footprints for the board with the + * refdes and value filled in. + */ + +#include <stdio.h> +#include <strings.h> +#include "../libueda/mcl.h" + +extern char *optarg; + +extern char *MCLfile; +extern struct component components[]; +extern int ncomponents; +extern char *get_comp_attr(); + +int check_completeness; + +main(argc, argv) + char **argv; +{ + register int c; + register struct component *comp; + register char *footprint, *value; + + while ((c = getopt(argc, argv, "chM:")) != EOF) + switch (c) { + case 'c': + check_completeness++; + break; + case 'h': + puts("include(template.pcb)"); + break; + case 'M': + MCLfile = optarg; + break; + default: + /* getopt prints the error message */ + exit(1); + } + + read_MCL(); + + for (comp = components, c = 0; c < ncomponents; comp++, c++) { + footprint = get_comp_attr(comp, "footprint"); + if (!footprint) { + if (check_completeness) + fprintf(stderr, "%s has no footprint\n", + comp->name); + continue; + } + if (!strcmp(footprint, "none")) + continue; + if (!strcmp(footprint, "TBD")) { + if (check_completeness) + fprintf(stderr, "%s: footprint=TBD\n", + comp->name); + continue; + } + value = get_comp_attr(comp, "pcbvalue"); + if (!value) + value = get_comp_attr(comp, "value"); + if (!value) + value = get_comp_attr(comp, "device"); + if (!value) + value = get_comp_attr(comp, "manufacturer_part_number"); + if (!value) + value = ""; + if (strncmp(footprint, "file:", 5)) + printf("make_footprint(`%s',`%s',`%s')\n", footprint, + comp->name, value); + else + printf("make_footprint_file(`%s',`%s',`%s')\n", + footprint + 5, comp->name, value); + } + exit(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/mclutils/mkbom.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,259 @@ +/* + * This program generates a procurement-oriented BOM from the MCL. + */ + +#include <stdio.h> +#include <strings.h> +#include "../libueda/mcl.h" + +extern char *optarg; +extern char *malloc(); + +extern char *MCLfile; +extern struct component components[]; +extern int ncomponents; +extern char *get_comp_attr(), *get_comp_multiattr(); +extern struct component *find_partdef_by_name(); + +struct refdeslist { + char *refdes; + struct refdeslist *next; +}; + +struct bompart { + struct component *part; + int qty; + struct bompart *next; + struct refdeslist *refdeslist; +}; + +int check_completeness, refdes_lists; +struct bompart *bomhead; + +do_cmdline_opts(argc, argv) + char **argv; +{ + register int c; + + while ((c = getopt(argc, argv, "cM:p:r")) != EOF) + switch (c) { + case 'c': + check_completeness++; + break; + case 'M': + MCLfile = optarg; + break; + case 'p': + set_popopt_list(optarg); + break; + case 'r': + refdes_lists++; + break; + default: + /* getopt prints the error message */ + exit(1); + } +} + +main(argc, argv) + char **argv; +{ + do_cmdline_opts(argc, argv); + read_MCL(); + tally_parts(); + output(); + exit(0); +} + +tally_parts() +{ + int c; + register struct component *comp; + register char *attr; + struct component *socket; + + for (comp = components, c = 0; c < ncomponents; comp++, c++) { + if (!check_component_popopt(comp)) + continue; + if (comp->partdef == NULL) { + attr = get_comp_attr(comp, "part"); + if (attr && !strcmp(attr, "none")) + continue; + if (check_completeness) + fprintf(stderr, "%s has no part defined\n", + comp->name); + continue; + } + add_part_to_bom(comp->partdef, comp->name); + attr = get_comp_attr(comp, "socket"); + if (attr) { + socket = find_partdef_by_name(attr); + if (socket) + add_part_to_bom(socket, comp->name); + else + fprintf(stderr, + "%s: socket part %s not found\n", + comp->name, attr); + } + } +} + +add_part_to_bom(part, refdes) + struct component *part; + char *refdes; +{ + register struct bompart *bp, **bpp; + + for (bpp = &bomhead; bp = *bpp; bpp = &bp->next) + if (bp->part == part) { + bp->qty++; + add_refdes_to_bompart(bp, refdes); + return; + } + /* new part */ + bp = (struct bompart *) malloc(sizeof(struct bompart)); + if (bp == NULL) { + perror("malloc"); + exit(1); + } + bp->part = part; + bp->qty = 1; + bp->next = NULL; + bp->refdeslist = NULL; + *bpp = bp; + add_refdes_to_bompart(bp, refdes); +} + +add_refdes_to_bompart(bp, refdes) + struct bompart *bp; + char *refdes; +{ + register struct refdeslist *le, **lep; + + if (!refdes_lists) + return; + for (lep = &bp->refdeslist; le = *lep; lep = &le->next) + ; + le = (struct refdeslist *) malloc(sizeof(struct refdeslist)); + if (!le) { + perror("malloc"); + exit(1); + } + le->refdes = refdes; + le->next = NULL; + *lep = le; +} + +output() +{ + register int i; + register struct component *part; + register struct bompart *bp; + char *manuf, *partno, *desc, *spectitle; + + printf("Part\t\t\t\t\t\t\t\t\t Qty\n"); + for (i = 0; i < 79; i++) + putchar('-'); + putchar('\n'); + + for (bp = bomhead; bp; bp = bp->next) { + part = bp->part; + manuf = get_comp_attr(part, "manufacturer"); + partno = get_comp_attr(part, "manufacturer_part_number"); + if (!partno) + partno = get_comp_attr(part, "device"); + desc = get_comp_attr(part, "description"); + spectitle = get_comp_attr(part, "bom_part_title"); + if (spectitle) { + fputs(spectitle, stdout); + i = strlen(spectitle); + } else if (manuf && partno) + i = printf("%s %s", manuf, partno); + else if (desc) { + fputs(desc, stdout); + i = strlen(desc); + desc = NULL; /* used it */ + } else { + fprintf(stderr, + "part %s: no identifying information for the BOM\n", + part->name); + continue; + } + for (i /= 8; i < 9; i++) + putchar('\t'); + printf("%7d\n", bp->qty); + if (desc) + printf(" %s\n", desc); + do_comments(part); + do_sources(part); + do_substitutes(part); + if (refdes_lists) + dump_refdes_list(bp->refdeslist); + } +} + +do_sources(part) + register struct component *part; +{ + int scnt; + register char *src; + char *vendor, *vpn; + + for (scnt = 0; src = get_comp_multiattr(part, "source", &scnt); ) + printf(" Source: %s\n", src); + if (scnt) + return; + /* no source= attributes, check for the old style vendor ones */ + vendor = get_comp_attr(part, "vendor"); + vpn = get_comp_attr(part, "vendor_part_number"); + if (vendor && vpn) + printf(" Source: %s %s\n", vendor, vpn); + else if (vendor) + printf(" Source: %s\n", vendor); +} + +do_substitutes(part) + register struct component *part; +{ + int scnt; + register char *s; + + for (scnt = 0; s = get_comp_multiattr(part, "substitute", &scnt); ) + printf(" Acceptable substitute: %s\n", s); +} + +do_comments(part) + register struct component *part; +{ + int scnt; + register char *s; + + for (scnt = 0; s = get_comp_multiattr(part, "bom_comment", &scnt); ) + printf(" %s\n", s); +} + +dump_refdes_list(le) + register struct refdeslist *le; +{ + register int acc, i; + + for (acc = 0; le; le = le->next) { + i = strlen(le->refdes) + 1; + if (le->next) + i++; + if (acc && (acc + i >= 80)) { + putchar('\n'); + acc = 0; + } + if (!acc) { + putchar(' '); + acc++; + } + printf(" %s", le->refdes); + if (le->next) + putchar(','); + acc += i; + } + if (acc) + putchar('\n'); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/mclutils/shortbom.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,182 @@ +/* + * This program generates a "short" BOM from the MCL. + */ + +#include <stdio.h> +#include <strings.h> +#include "../libueda/mcl.h" + +extern char *optarg; +extern char *malloc(); + +extern char *MCLfile; +extern struct component components[]; +extern int ncomponents; +extern char *get_comp_attr(); +extern struct component *find_partdef_by_name(); + +struct bomline { + char *refdes; + char *manuf; + char *partno; + char *description; +}; + +int column_sep_width = 2, tabbed; +int assembly; +struct bomline *bombuf; +int nbomlines; +char unknownstr[] = "unknown"; +int refdes_col_width, manuf_col_width, partno_col_width; + +do_cmdline_opts(argc, argv) + char **argv; +{ + register int c; + + while ((c = getopt(argc, argv, "aM:p:s:t")) != EOF) + switch (c) { + case 'a': + assembly++; + break; + case 'M': + MCLfile = optarg; + break; + case 'p': + set_popopt_list(optarg); + break; + case 's': + column_sep_width = atoi(optarg); + break; + case 't': + tabbed++; + break; + default: + /* getopt prints the error message */ + exit(1); + } +} + +main(argc, argv) + char **argv; +{ + do_cmdline_opts(argc, argv); + read_MCL(); + bombuf = (struct bomline *) + malloc(sizeof(struct bomline) * (ncomponents+1)); + if (!bombuf) { + perror("malloc"); + exit(1); + } + bombuf[0].refdes = "Refdes"; + bombuf[0].manuf = "Manuf"; + bombuf[0].partno = "Part #"; + bombuf[0].description = "Description"; + construct_bom(); + if (tabbed) + tabbed_output(); + else { + compute_col_widths(); + output(); + } + exit(0); +} + +construct_bom() +{ + int c, i; + register struct component *comp, *part; + register char *attr; + + for (comp = components, c = 0, i = 1; c < ncomponents; comp++, c++) { + if (!check_component_popopt(comp)) + continue; + attr = get_comp_attr(comp, "part"); + if (attr && !strcmp(attr, "none")) + continue; + bombuf[i].refdes = comp->name; + if (assembly && (attr = get_comp_attr(comp, "socket"))) { + part = find_partdef_by_name(attr); + if (!part) { + fprintf(stderr, + "%s: socket part %s not found\n", + comp->name, attr); + continue; + } + } else + part = comp; + attr = get_comp_attr(part, "manufacturer"); + if (attr) + bombuf[i].manuf = attr; + else + bombuf[i].manuf = unknownstr; + if (attr = get_comp_attr(part, "manufacturer_part_number")) + bombuf[i].partno = attr; + else if (attr = get_comp_attr(part, "device")) + bombuf[i].partno = attr; + else + bombuf[i].partno = unknownstr; + bombuf[i].description = get_comp_attr(part, "description"); + i++; + } + nbomlines = i; +} + +compute_col_widths() +{ + int c; + register int i; + register struct bomline *line; + + for (line = bombuf, c = 0; c < nbomlines; line++, c++) { + i = strlen(line->refdes); + if (i > refdes_col_width) + refdes_col_width = i; + i = strlen(line->manuf); + if (i > manuf_col_width) + manuf_col_width = i; + i = strlen(line->partno); + if (i > partno_col_width) + partno_col_width = i; + } +} + +output() +{ + int c; + register int i; + register struct bomline *line; + + for (line = bombuf, c = 0; c < nbomlines; line++, c++) { + fputs(line->refdes, stdout); + i = refdes_col_width + column_sep_width - strlen(line->refdes); + while (i--) + putchar(' '); + fputs(line->manuf, stdout); + i = manuf_col_width + column_sep_width - strlen(line->manuf); + while (i--) + putchar(' '); + fputs(line->partno, stdout); + if (line->description) { + i = partno_col_width + column_sep_width - + strlen(line->partno); + while (i--) + putchar(' '); + fputs(line->description, stdout); + } + putchar('\n'); + } +} + +tabbed_output() +{ + int c; + register struct bomline *line; + + for (line = bombuf+1, c = 1; c < nbomlines; line++, c++) { + printf("%s\t%s\t%s", line->refdes, line->manuf, line->partno); + if (line->description) + printf("\t%s", line->description); + putchar('\n'); + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/migration/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,1 @@ +g2uschem
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/migration/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,16 @@ +CFLAGS= -O +PROGS= g2uschem +BINDIR= /usr/local + +all: ${PROGS} + +${PROGS}: + ${CC} ${CFLAGS} -o $@ $@.c + +install: + install -c -o bin -g bin -m 755 ${PROGS} ${BINDIR} + +clean: + rm -f *.[ao] a.out core errs ${PROGS} + +g2uschem: g2uschem.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/migration/g2uschem.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,509 @@ +#include <ctype.h> +#include <stdio.h> +#include <strings.h> + +#define MAXLINE 256 +#define MAXATTRS 16 +#define ATTRBUF_SIZE 4096 + +struct attr { + int graphparams[8]; + char *name; + char *value; +}; + +FILE *inf, *outf; +char *infname, *outfname; +int lineno; +int x_offset, y_offset; + +main(argc, argv) + char **argv; +{ + char line[MAXLINE]; + int objlineno; + struct attr attrs[MAXATTRS]; + char attrbuf[ATTRBUF_SIZE]; + int nattrs; + register int c; + + if (argc > 1) { + infname = argv[1]; + inf = fopen(infname, "r"); + if (!inf) { + perror(infname); + exit(1); + } + } else { + inf = stdin; + infname = "stdin"; + } + if (argc > 2) { + outfname = argv[2]; + outf = fopen(outfname, "w"); + if (!outf) { + perror(outfname); + exit(1); + } + } else { + outf = stdout; + outfname = "stdout"; + } + + while (getline(line)) { + if (!isalpha(line[0])) { + fprintf(stderr, "%s: line %d: gschem object expected\n", + infname, lineno); + exit(1); + } + objlineno = lineno; + /* check for attached attributes */ + c = getc(inf); + if (c == '{') { + skipline(); + nattrs = read_attrs(attrs, attrbuf); + } else { + if (c != EOF) + ungetc(c, inf); + nattrs = 0; + } + /* dispatch by object type */ + switch (line[0]) { + case 'v': + continue; /* ignore */ + /* simple graphics */ + case 'L': + case 'B': + case 'V': + case 'A': + if (nattrs) + fprintf(stderr, + "%s: line %d: attributes attached to %c object (ignored)\n", + infname, objlineno, line[0]); + handle_simple_graph(line, objlineno); + continue; + case 'T': + handle_T_obj(line, objlineno); + continue; + case 'N': + handle_net(line, objlineno, attrs, nattrs); + continue; + case 'U': + handle_bus(line, objlineno, attrs, nattrs); + continue; + case 'C': + handle_component(line, objlineno, attrs, nattrs); + continue; + default: + fprintf(stderr, + "%s: line %d: object type %c not supported\n", + infname, objlineno, line[0]); + } + } + exit(0); +} + +handle_component(objline, objlineno, attrs, nattrs) + char *objline; + struct attr *attrs; +{ + int numparams[5]; + char *cp, *symname; + struct attr *refdes; + register int i; + + parse_numline(objline, objlineno, numparams, 5, &cp); + if (!isspace(*cp)) { +inv: fprintf(stderr, "%s: line %d: invalid C line\n", infname, + objlineno); + exit(1); + } + while (isspace(*cp)) + cp++; + if (!isalnum(*cp)) + goto inv; + for (symname = cp; isalnum(*cp) || *cp == '-' || *cp == '_'; cp++) + ; + if (strcmp(cp, ".sym")) + goto inv; + *cp = '\0'; + + /* weed some out based on the symbol name */ + if (!strcmp(symname, "nc-x")) + return; /* we'll do that differently */ + if (strlen(symname) == 7 && !strncmp(symname, "title-", 6)) { + /* handle titleblock */ + fprintf(outf, "Schem graph %c;\n", symname[6]); + x_offset = numparams[0]; + y_offset = numparams[1]; + return; + } + + /* do we have a refdes? */ + refdes = NULL; + for (i = 0; i < nattrs; i++) + if (!strcmp(attrs[i].name, "refdes")) { + refdes = attrs + i; + break; + } + if (refdes) + emit_component_instance(numparams, symname, attrs, nattrs, + refdes, objlineno); + else + emit_graph_symbol(numparams, symname, attrs, nattrs, objlineno); +} + +emit_component_instance(numparams, symname, attrs, nattrs, refdes, objlineno) + int *numparams; + char *symname; + struct attr *attrs, *refdes; +{ + register struct attr *ap; + register int i; + + fprintf(outf, "Component %s graph \"%s\" %d %d", refdes->value, symname, + numparams[0] - x_offset, numparams[1] - y_offset); + if (numparams[3]) + fprintf(outf, " rot %d", numparams[3]); + if (numparams[4]) + fputs(" mirror", outf); + fputs(" {\n", outf); + + /* attribute data */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + if (ap != refdes) + fprintf(outf, "\t(%s=\"%s\")\n", ap->name, ap->value); + /* attribute graphics */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + if (ap->graphparams[4]) + fprintf(outf, "\tDisplayAttr %s %d %d %d %d %d;\n", + ap->name, ap->graphparams[0] - x_offset, + ap->graphparams[1] - y_offset, + ap->graphparams[3], + ap->graphparams[6], ap->graphparams[7]); + fputs("};\n", outf); +} + +emit_graph_symbol(numparams, symname, attrs, nattrs, objlineno) + int *numparams; + char *symname; + struct attr *attrs; +{ + register struct attr *ap; + register int i; + + fprintf(outf, "GraphSym \"%s\" %d %d", symname, + numparams[0] - x_offset, numparams[1] - y_offset); + if (numparams[3]) + fprintf(outf, " rot %d", numparams[3]); + if (numparams[4]) + fputs(" mirror", outf); + + if (nattrs) + fputs(" {\n", outf); + else { + fputs(";\n", outf); + return; + } + + /* attribute data */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + fprintf(outf, "\t(%s=\"%s\")\n", ap->name, ap->value); + /* attribute graphics */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + if (ap->graphparams[4]) + fprintf(outf, "\tDisplayAttr %s %d %d %d %d %d;\n", + ap->name, ap->graphparams[0] - x_offset, + ap->graphparams[1] - y_offset, + ap->graphparams[3], + ap->graphparams[6], ap->graphparams[7]); + fputs("};\n", outf); +} + +handle_net(objline, objlineno, attrs, nattrs) + char *objline; + struct attr *attrs; +{ + int numparams[5]; + register struct attr *ap; + register int i; + + parse_numline(objline, objlineno, numparams, 5, NULL); + fprintf(outf, "NetLine (%d,%d) (%d,%d)", numparams[0] - x_offset, + numparams[1] - y_offset, numparams[2] - x_offset, + numparams[3] - y_offset); + if (nattrs) + fputs(" {\n", outf); + else { + fputs(";\n", outf); + return; + } + + /* attribute data */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + fprintf(outf, "\t(%s=\"%s\")\n", ap->name, ap->value); + /* attribute graphics */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + if (ap->graphparams[4]) + fprintf(outf, "\tDisplayAttr %s %d %d %d %d %d;\n", + ap->name, ap->graphparams[0] - x_offset, + ap->graphparams[1] - y_offset, + ap->graphparams[3], + ap->graphparams[6], ap->graphparams[7]); + fputs("};\n", outf); +} + +handle_bus(objline, objlineno, attrs, nattrs) + char *objline; + struct attr *attrs; +{ + int numparams[6]; + register struct attr *ap; + register int i; + + parse_numline(objline, objlineno, numparams, 6, NULL); + fprintf(outf, "BusSeg (%d,%d) (%d,%d)", numparams[0] - x_offset, + numparams[1] - y_offset, numparams[2] - x_offset, + numparams[3] - y_offset); + if (nattrs) + fputs(" {\n", outf); + else { + fputs(";\n", outf); + return; + } + + /* attribute data */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + fprintf(outf, "\t(%s=\"%s\")\n", ap->name, ap->value); + /* attribute graphics */ + for (ap = attrs, i = 0; i < nattrs; ap++, i++) + if (ap->graphparams[4]) + fprintf(outf, "\tDisplayAttr %s %d %d %d %d %d;\n", + ap->name, ap->graphparams[0] - x_offset, + ap->graphparams[1] - y_offset, + ap->graphparams[3], + ap->graphparams[6], ap->graphparams[7]); + fputs("};\n", outf); +} + +handle_simple_graph(objline, objlineno) + char *objline; +{ + translate_simple_graph_line(objline, objlineno); + fprintf(outf, "GraphBlockG {\n%s\n}\n", objline); +} + +translate_simple_graph_line(objline, objlineno) + char *objline; +{ + int numparams[16]; + + switch (objline[0]) { + case 'L': + parse_numline(objline, objlineno, numparams, 10, NULL); + numparams[0] -= x_offset; + numparams[1] -= y_offset; + numparams[2] -= x_offset; + numparams[3] -= y_offset; + sprintf(objline, "L %d %d %d %d %d %d %d %d %d %d", + numparams[0], numparams[1], numparams[2], numparams[3], + numparams[4], numparams[5], numparams[6], numparams[7], + numparams[8], numparams[9]); + return; + case 'B': + parse_numline(objline, objlineno, numparams, 16, NULL); + numparams[0] -= x_offset; + numparams[1] -= y_offset; + sprintf(objline, + "B %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d", + numparams[0], numparams[1], numparams[2], numparams[3], + numparams[4], numparams[5], numparams[6], numparams[7], + numparams[8], numparams[9], numparams[10],numparams[11], + numparams[12],numparams[13],numparams[14], + numparams[15]); + return; + case 'V': + parse_numline(objline, objlineno, numparams, 15, NULL); + numparams[0] -= x_offset; + numparams[1] -= y_offset; + sprintf(objline, + "V %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d", + numparams[0], numparams[1], numparams[2], numparams[3], + numparams[4], numparams[5], numparams[6], numparams[7], + numparams[8], numparams[9], numparams[10],numparams[11], + numparams[12],numparams[13],numparams[14]); + return; + case 'A': + parse_numline(objline, objlineno, numparams, 11, NULL); + numparams[0] -= x_offset; + numparams[1] -= y_offset; + sprintf(objline, "A %d %d %d %d %d %d %d %d %d %d %d", + numparams[0], numparams[1], numparams[2], numparams[3], + numparams[4], numparams[5], numparams[6], numparams[7], + numparams[8], numparams[9], numparams[10]); + return; + default: + fprintf(stderr, + "unknown type in translate_simple_graph_line()\n"); + exit(1); + } +} + +handle_T_obj(objline, objlineno) + char *objline; +{ + int numparams[9]; + char textline[MAXLINE]; + register int i; + + parse_numline(objline, objlineno, numparams, 9, NULL); + if (numparams[8] < 1) { + fprintf(stderr, "%s: line %d: T object: num_lines<1!\n", + infname, objlineno); + exit(1); + } + fprintf(outf, "GraphBlockG {\nT %d %d %d %d %d %d %d %d %d\n", + numparams[0] - x_offset, numparams[1] - y_offset, numparams[2], + numparams[3], numparams[4], numparams[5], numparams[6], + numparams[7], numparams[8]); + for (i = numparams[8]; i; i--) { + if (!getline(textline)) { + fprintf(stderr, "%s: EOF in T object\n", infname); + exit(1); + } + fprintf(outf, "%s\n", textline); + } + fputs("}\n", outf); +} + +read_attrs(attrs, attrbuf) + struct attr *attrs; + char *attrbuf; +{ + char Tline[MAXLINE]; + int Tline_parsed[9]; + char attrline[MAXLINE]; + int nattrs, chars_used; + char *bufptr; + register char *cp; + register int i; + + for (nattrs = 0, chars_used = 0, bufptr = attrbuf; ; ) { + if (!getline(Tline)) { +badeof: fprintf(stderr, "%s: EOF in attribute block\n", + infname); + exit(1); + } + switch (Tline[0]) { + case 'T': + break; + case '}': + return(nattrs); + default: + fprintf(stderr, + "%s: line %d: wrong line type in attribute block\n", + infname, lineno); + exit(1); + } + parse_numline(Tline, lineno, Tline_parsed, 9, NULL); + if (Tline_parsed[8] < 1) { + fprintf(stderr, "%s: line %d: T object: num_lines<1!\n", + infname, lineno); + exit(1); + } + if (Tline_parsed[8] > 1) { + fprintf(stderr, + "%s: line %d: multiline text object in attribute block not supported\n", + infname, lineno); + exit(1); + } + if (!getline(attrline)) + goto badeof; + cp = index(attrline, '='); + if (!cp) /* non-attribute text item */ + continue; /* ignore these */ + /* break name and value */ + *cp++ = '\0'; + if (nattrs >= MAXATTRS) { + fprintf(stderr, "%s: line %d: too many attributes\n", + infname, lineno); + exit(1); + } + for (i = 0; i < 8; i++) + attrs[nattrs].graphparams[i] = Tline_parsed[i]; + i = strlen(attrline) + 1; + chars_used += i; + if (chars_used > ATTRBUF_SIZE) { +bufovflo: fprintf(stderr, "%s: line %d: attr text buf overflow\n", + infname, lineno); + exit(1); + } + bcopy(attrline, bufptr, i); + attrs[nattrs].name = bufptr; + bufptr += i; + i = strlen(cp) + 1; + chars_used += i; + if (chars_used > ATTRBUF_SIZE) + goto bufovflo; + bcopy(cp, bufptr, i); + attrs[nattrs].value = bufptr; + bufptr += i; + nattrs++; + } +} + +parse_numline(line, lineno, numarray, nfields, endp) + char *line; + int lineno; + int *numarray; + int nfields; + char **endp; +{ + register char *cp, *np; + register int i; + + for (i = 0, cp = line+1; i < nfields; i++) { + if (!isspace(*cp)) { +inv: fprintf(stderr, "%s: line %d: invalid numeric line\n", + infname, lineno); + exit(1); + } + while (isspace(*cp)) + cp++; + np = cp; + if (*cp == '-') + cp++; + if (!isdigit(*cp)) + goto inv; + while (isdigit(*cp)) + cp++; + numarray[i] = atoi(np); + } + if (endp) + *endp = cp; + else if (*cp) + goto inv; +} + +getline(linebuf) + char *linebuf; +{ + register char *cp; + + if (fgets(linebuf, MAXLINE, inf) == NULL) + return(0); + lineno++; + /* strip trailing newline or other whitespace */ + cp = index(linebuf, '\0'); + while (cp > linebuf && isspace(cp[-1])) + cp--; + *cp = '\0'; + return(1); +} + +skipline() +{ + char junkline[MAXLINE]; + + getline(junkline); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,1 @@ +ueda-sverp
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,16 @@ +CFLAGS= -O +OBJS= elaborate.o lexer.o link.o main.o misc.o output.o prim.o vparse.o +LIBS= ../libueda/libueda.a +PROG= ueda-sverp +BINDIR= /usr/local + +all: ${PROG} + +${PROG}: ${OBJS} ${LIBS} + ${CC} -o $@ ${OBJS} ${LIBS} + +install: + install -c -o bin -g bin -m 755 ${PROG} ${BINDIR} + +clean: + rm -f *.[ao] a.out core errs ${PROG}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/elaborate.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,392 @@ +/* + * Here we elaborate the hierarchy and create our flat netlist. + */ + +#include <stdio.h> +#include <strings.h> +#include "struct.h" +#include "lexer.h" /* for MAXDIGITS */ + +extern char *malloc(); + +struct output_net *output_net_head; +struct output_element *output_element_head; +int total_good_nets, total_singular_nets, total_null_nets; +int total_output_elements; + +static struct output_net **output_net_tail = &output_net_head; +static struct output_element **output_element_tail = &output_element_head; + +static struct output_net ** +alloc_mod_net_array(mod) + struct module_def *mod; +{ + int total_wires; + unsigned alloc_size; + register struct output_net **array; + + total_wires = mod->nwires_ports + mod->nwires_internal; + alloc_size = sizeof(struct output_net *) * total_wires; + array = (struct output_net **) malloc(alloc_size); + if (!array) { + perror("malloc"); + exit(1); + } + return(array); +} + +static struct output_net ** +alloc_connect_net_array(mod) + struct module_def *mod; +{ + register unsigned alloc_size; + register struct output_net **array; + + alloc_size = sizeof(struct output_net *) * mod->nwires_ports; + array = (struct output_net **) malloc(alloc_size); + if (!array) { + perror("malloc"); + exit(1); + } + bzero(array, alloc_size); + return(array); +} + +static struct output_net * +create_real_net(hier_prefix, base_name, is_bus, bus_pos) + char *hier_prefix, *base_name; +{ + int len; + register char *buf; + register struct output_net *net; + + len = sizeof(struct output_net) + strlen(hier_prefix) + + strlen(base_name) + 1; + if (is_bus) + len += MAXDIGITS + 2; + buf = malloc(len); + if (!buf) { + perror("malloc"); + exit(1); + } + net = (struct output_net *) buf; + bzero(net, sizeof(struct output_net)); + buf += sizeof(struct output_net); + if (is_bus) + sprintf(buf, "%s%s[%d]", hier_prefix, base_name, bus_pos); + else + sprintf(buf, "%s%s", hier_prefix, base_name); + net->name = buf; + *output_net_tail = net; + output_net_tail = &net->next; + return(net); +} + +static void +create_module_nets(mod, hier_prefix, fillp) + struct module_def *mod; + char *hier_prefix; + register struct output_net **fillp; +{ + register struct module_net_def *nd; + register int i, incr; + + for (nd = mod->nets; nd; nd = nd->next) { + if (nd->is_port) + continue; + if (!nd->is_bus) { + *fillp++ = create_real_net(hier_prefix, nd->name, 0); + continue; + } + if (nd->bus_msb < nd->bus_lsb) + incr = 1; + else + incr = -1; + for (i = nd->bus_msb; i != nd->bus_lsb + incr; i += incr) + *fillp++ = create_real_net(hier_prefix, nd->name, 1, i); + } +} + +elaborate_module(mod, inst_name, hier_prefix, in_conn_array) + register struct module_def *mod; + char *inst_name, *hier_prefix; + struct output_net **in_conn_array; +{ + register struct output_net **mod_net_array; + register struct module_def_subinst *sub; + + if (mod->nwires_internal) { + mod_net_array = alloc_mod_net_array(mod); + if (mod->nwires_ports) + bcopy(in_conn_array, mod_net_array, + sizeof(struct output_net *) * mod->nwires_ports); + create_module_nets(mod, hier_prefix, + mod_net_array + mod->nwires_ports); + } else + mod_net_array = in_conn_array; + + for (sub = mod->subinst; sub; sub = sub->next) + elaborate_subinst(mod, inst_name, hier_prefix, mod_net_array, + sub); + + if (mod->nwires_internal) + free(mod_net_array); +} + +static void +report_connect_conflict(new_inst, ce, offset) + char *new_inst; + struct connect_entry *ce; + int offset; +{ + register struct module_net_def *port = ce->down_portdef; + int bus_pos; + + if (port->is_bus) { + offset += ce->down_offset; + if (port->bus_msb > port->bus_lsb) + bus_pos = port->bus_msb - offset; + else + bus_pos = port->bus_msb + offset; + fprintf(stderr, + "elaborating %s: multiple connections to port %s[%d]\n", + new_inst, port->name, bus_pos); + } else + fprintf(stderr, + "elaborating %s: multiple connections to port %s\n", + new_inst, port->name); + exit(1); +} + +static void +check_connect_conflict(new_inst, ce, conn_array) + char *new_inst; + register struct connect_entry *ce; + register struct output_net **conn_array; +{ + register int start, i; + + start = ce->down_portdef->array_index + ce->down_offset; + for (i = 0; i < ce->down_width; i++) + if (conn_array[start + i]) + report_connect_conflict(new_inst, ce, i); +} + +static struct output_net * +create_nc_net(mup, old_inst, ce) + struct module_def *mup; + char *old_inst; + struct connect_entry *ce; +{ + register struct output_net *net; + + net = (struct output_net *) malloc(sizeof(struct output_net)); + if (!net) { + perror("malloc"); + exit(1); + } + bzero(net, sizeof(struct output_net)); + net->nc_module_name = mup->name; + net->nc_module_lineno = ce->src_lineno; + net->nc_module_inst = old_inst; + return(net); +} + +static struct output_net * +process_subinst_connect(mup, sub, old_inst, new_inst, mod_net_array, conn_array) + struct module_def *mup; + struct module_def_subinst *sub; + char *old_inst, *new_inst; + struct output_net **mod_net_array; + register struct output_net **conn_array; +{ + struct output_net *nc_head = 0, **nc_tail = &nc_head; + register struct connect_entry *ce; + int start; + register int i; + register struct output_net *nc_net; + + for (ce = sub->connections; ce; ce = ce->next) { + check_connect_conflict(new_inst, ce, conn_array); + if (ce->up_netdef) { + bcopy(mod_net_array + ce->up_netdef->array_index + + ce->up_offset, + conn_array + ce->down_portdef->array_index + + ce->down_offset, + sizeof(struct output_net *) * ce->up_width); + continue; + } + /* it's a no-connect */ + start = ce->down_portdef->array_index + ce->down_offset; + for (i = 0; i < ce->down_width; i++) { + nc_net = create_nc_net(mup, old_inst, ce); + conn_array[start + i] = nc_net; + *nc_tail = nc_net; + nc_tail = &nc_net->next; + } + } + return(nc_head); +} + +static void +report_missing_connect(new_inst, port, offset) + char *new_inst; + register struct module_net_def *port; + int offset; +{ + int bus_pos; + + if (port->is_bus) { + if (port->bus_msb > port->bus_lsb) + bus_pos = port->bus_msb - offset; + else + bus_pos = port->bus_msb + offset; + fprintf(stderr, + "elaborating %s: missing connection to port %s[%d]\n", + new_inst, port->name, bus_pos); + } else + fprintf(stderr, + "elaborating %s: missing connection to port %s\n", + new_inst, port->name); + exit(1); +} + +static void +check_missing_connect(new_inst, mdown, conn_array) + char *new_inst; + struct module_def *mdown; + struct output_net **conn_array; +{ + register struct module_net_def *port; + register struct output_net **connp = conn_array; + register int i; + + for (port = mdown->nets; port; port = port->next) { + if (!port->is_port) + return; /* all ports are upfront */ + if (!port->is_bus) { + if (!*connp++) + report_missing_connect(new_inst, port, 0); + continue; + } + for (i = 0; i < port->bus_width; i++) + if (!*connp++) + report_missing_connect(new_inst, port, i); + } +} + +static void +report_bad_nc_net(net) + register struct output_net *net; +{ + fprintf(stderr, +"error: NC pseudo-net created at module %s line %d inst %s goes to more than one pin\n", + net->nc_module_name, net->nc_module_lineno, + net->nc_module_inst); + exit(1); +} + +static void +check_nc_nets(head) + struct output_net *head; +{ + register struct output_net *net; + + for (net = head; net; net = net->next) + if (net->npoints > 1) + report_bad_nc_net(net); +} + +elaborate_subinst(mup, inst_name, hier_prefix, mod_net_array, sub) + struct module_def *mup; + char *inst_name, *hier_prefix; + struct output_net **mod_net_array; + struct module_def_subinst *sub; +{ + char *new_inst, *new_prefix; + struct module_def *mdown = sub->submod_def; + struct output_net **conn_array, *nc_nets; + + new_inst = malloc(strlen(hier_prefix) + strlen(sub->inst_name) + 1); + if (!new_inst) { + perror("malloc"); + exit(1); + } + sprintf(new_inst, "%s%s", hier_prefix, sub->inst_name); + if (mdown->nports) { + conn_array = alloc_connect_net_array(mdown); + nc_nets = process_subinst_connect(mup, sub, inst_name, new_inst, + mod_net_array, conn_array); + check_missing_connect(new_inst, mdown, conn_array); + } else { + conn_array = 0; + nc_nets = 0; + } + + if (mdown->is_primitive) + elaborate_primitive(mdown, new_inst, conn_array); + else { + new_prefix = malloc(strlen(hier_prefix) + + strlen(sub->inst_name) + 2); + if (!new_prefix) { + perror("malloc"); + exit(1); + } + sprintf(new_prefix, "%s%s.", hier_prefix, sub->inst_name); + elaborate_module(mdown, new_inst, new_prefix, conn_array); + free(new_prefix); + if (conn_array) + free(conn_array); + } + + if (nc_nets) + check_nc_nets(nc_nets); +} + +static void +incr_net_points_for_output_element(elem) + struct output_element *elem; +{ + register struct output_net **p, **endp; + + p = elem->connections; + endp = p + elem->prim_def->nports; + for (; p < endp; p++) + (*p)->npoints++; +} + +elaborate_primitive(mod, inst_name, in_conn_array) + struct module_def *mod; + char *inst_name; + struct output_net **in_conn_array; +{ + register struct output_element *elem; + + elem = (struct output_element *) malloc(sizeof(struct output_element)); + if (!elem) { + perror("malloc"); + exit(1); + } + elem->prim_def = mod; + elem->hier_inst_name = inst_name; + elem->connections = in_conn_array; + elem->next = 0; + *output_element_tail = elem; + output_element_tail = &elem->next; + total_output_elements++; + incr_net_points_for_output_element(elem); +} + +tally_output_nets() +{ + register struct output_net *net; + + for (net = output_net_head; net; net = net->next) { + if (net->npoints > 1) + total_good_nets++; + else if (net->npoints == 1) + total_singular_nets++; + else + total_null_nets++; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/lexer.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,215 @@ +/* + * This module contains the lexer underlying the parser for the minimal + * subset of Verilog we grok; the same lexer will be used to read and parse + * the primitives definition file. + */ + +#include <ctype.h> +#include <stdio.h> +#include "lexer.h" + +char *parser_filename; +FILE *parser_readF; +int parser_lineno; +char parser_read_word[MAXWORD+1]; +int parser_read_number; +int pushback_token; + +void +parse_error(msg) + char *msg; +{ + fprintf(stderr, "%s line %d: %s\n", parser_filename, parser_lineno, + msg); + exit(1); +} + +static +my_getchar() +{ + register int c; + + c = getc(parser_readF); + if (c < 0) + return(c); + if (!isascii(c)) + parse_error("non-ASCII character"); + if (iscntrl(c) && c != '\n' && c != '\t') + parse_error("invalid control character"); + return(c); +} + +static void +handle_trad_comment() +{ + register int c, flag; + + for (flag = 0; ; ) { + c = my_getchar(); + if (c < 0) + parse_error("/* comment ends in EOF"); + if (c == '\n') + parser_lineno++; + if (c == '/' && flag) + return; + flag = (c == '*'); + } +} + +static void +handle_line_comment() +{ + register int c; + + for (;;) { + c = my_getchar(); + if (c < 0) + parse_error("// comment ends in EOF"); + if (c == '\n') { + parser_lineno++; + return; + } + } +} + +static void +handle_comment() +{ + int c; + + c = my_getchar(); + switch (c) { + case '*': + /* traditional C comment style */ + handle_trad_comment(); + return; + case '/': + /* new-fangled double slash comment style */ + handle_line_comment(); + return; + default: + parse_error("character after '/' is not '*' or '/'"); + exit(1); + } +} + +static void +handle_num_token(first_digit) +{ + register int c, n; + + parser_read_number = first_digit - '0'; + for (n = 1; ; n++) { + c = my_getchar(); + if (!isdigit(c)) + break; + parser_read_number *= 10; + parser_read_number += c - '0'; + } + if (c >= 0) { + if (isalpha(c) || c == '_') + parse_error( + "digits followed by letters: neither word nor number"); + ungetc(c, parser_readF); + } + if (n > MAXDIGITS) + parse_error("number is too long (MAXDIGITS exceeded)"); +} + +static void +handle_word_token(first_char) +{ + register int c; + register char *cp; + register int len; + + cp = parser_read_word; + *cp++ = first_char; + for (len = 1; ; ) { + c = my_getchar(); + if (!isalnum(c) && c != '_' && c != '$') + break; + if (len >= MAXWORD) + parse_error("text token is too long"); + *cp++ = c; + len++; + } + *cp = '\0'; + if (c < 0) + return; + ungetc(c, parser_readF); +} + +static void +handle_qstr() +{ + register int c; + register char *cp; + register int len; + + cp = parser_read_word; + for (len = 0; ; ) { + c = my_getchar(); + if (c == EOF || c == '\n') +unterm: parse_error("unterminated quoted string"); + if (c == '"') + break; + if (c == '\\') { + c = my_getchar(); + if (c == EOF || c == '\n') + goto unterm; + } + if (len >= MAXWORD) + parse_error("quoted string is too long"); + *cp++ = c; + len++; + } + *cp = '\0'; +} + +get_token() +{ + register int c; + + if (c = pushback_token) { + pushback_token = 0; + return(c); + } +loop: c = my_getchar(); + switch (c) { + case EOF: + return(0); + case ' ': + case '\t': + goto loop; + case '\n': + parser_lineno++; + goto loop; + case '/': + handle_comment(); + goto loop; + case '(': + case ')': + case ',': + case '.': + case ':': + case ';': + case '[': + case ']': + return(c); + case '"': + handle_qstr(); + return(QSTRING); + } + if (isdigit(c)) { + handle_num_token(c); + return(NUMBER); + } + if (isalpha(c) || c == '_') { + handle_word_token(c); + return(WORD); + } + fprintf(stderr, "%s line %d: bad character \'%c\'\n", parser_filename, + parser_lineno, c); + exit(1); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/lexer.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,8 @@ +/* tokens */ +#define WORD 256 +#define NUMBER 257 +#define QSTRING 258 + +/* limits */ +#define MAXWORD 63 +#define MAXDIGITS 5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/link.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,198 @@ +/* + * ueda-sverp link pass + */ + +#include <stdio.h> +#include <strings.h> +#include "struct.h" + +extern struct module_def *glob_module_list, *top_module_def; +extern int top_module_candidates; + +extern struct module_def *find_module_by_name(); + +static void +toplevel_candidate(mod) + struct module_def *mod; +{ + top_module_candidates++; + if (!top_module_def) + top_module_def = mod; +} + +static struct module_net_def * +find_port_by_name(mod, portname) + struct module_def *mod; + register char *portname; +{ + register struct module_net_def *n; + + for (n = mod->nets; n; n = n->next) + if (!strcmp(n->name, portname)) + break; + if (n && n->is_port) + return(n); + else + return(0); +} + +static void +handle_downport_range(mup, ins, conn) + struct module_def *mup; + struct module_def_subinst *ins; + register struct connect_entry *conn; +{ + register struct module_net_def *port; + + port = conn->down_portdef; + if (!port->is_bus) { + fprintf(stderr, +"module %s line %d: mod %s port %s is not a bus, range spec is meaningless\n", + mup->name, conn->src_lineno, ins->submod_name, + port->name); + exit(1); + } + if (port->bus_msb > port->bus_lsb) { + if (conn->down_range_msb < conn->down_range_lsb) { +error_reversed: fprintf(stderr, + "module %s line %d: reversed range on bus port %s\n", + mup->name, conn->src_lineno, port->name); + exit(1); + } + if (conn->down_range_msb > port->bus_msb) { +error_outofrange: fprintf(stderr, + "module %s line %d: subrange on bus port %s exceeds full bus range\n", + mup->name, conn->src_lineno, port->name); + exit(1); + } + if (conn->down_range_lsb < port->bus_lsb) + goto error_outofrange; + conn->down_offset = port->bus_msb - conn->down_range_msb; + conn->down_width = conn->down_range_msb - conn->down_range_lsb + + 1; + } else { + if (conn->down_range_msb > conn->down_range_lsb) + goto error_reversed; + if (conn->down_range_msb < port->bus_msb) + goto error_outofrange; + if (conn->down_range_lsb > port->bus_lsb) + goto error_outofrange; + conn->down_offset = conn->down_range_msb - port->bus_msb; + conn->down_width = conn->down_range_lsb - conn->down_range_msb + + 1; + } +} + +static void +connect_by_name(mup, ins) + struct module_def *mup; + register struct module_def_subinst *ins; +{ + register struct connect_entry *conn; + register struct module_net_def *port; + + for (conn = ins->connections; conn; conn = conn->next) { + port = find_port_by_name(ins->submod_def, conn->down_portname); + if (!port) { + fprintf(stderr, + "instance %s in module %s: lower module %s has no port named \"%s\"\n", + ins->inst_name, mup->name, + ins->submod_name, conn->down_portname); + exit(1); + } + conn->down_portdef = port; + if (conn->down_range_given) + handle_downport_range(mup, ins, conn); + else { + conn->down_offset = 0; + conn->down_width = port->bus_width; + } + } +} + +static void +connect_by_order(mup, ins) + struct module_def *mup; + register struct module_def_subinst *ins; +{ + struct module_def *mdown; + register struct module_net_def *port; + register struct connect_entry *conn; + + mdown = ins->submod_def; + if (ins->connect_by_order != mdown->nports) { + fprintf(stderr, +"instance %s in module %s: connect by order port count mismatch (%d ports, %d connections)\n", + ins->inst_name, mup->name, mdown->nports, + ins->connect_by_order); + exit(1); + } + for (conn = ins->connections, port = mdown->nets; conn; + conn = conn->next, port = port->next) { + conn->down_portdef = port; + conn->down_offset = 0; + conn->down_width = port->bus_width; + } +} + +static void +check_width_match(mup, ins) + struct module_def *mup; + struct module_def_subinst *ins; +{ + register struct connect_entry *conn; + + for (conn = ins->connections; conn; conn = conn->next) + if (conn->up_netdef && conn->up_width != conn->down_width) { + fprintf(stderr, + "module %s line %d: width mismatch on connection to port %s\n", + mup->name, conn->src_lineno, + conn->down_portdef->name); + exit(1); + } +} + +static void +linkpass_process_inst(mup, ins) + struct module_def *mup; + register struct module_def_subinst *ins; +{ + register struct module_def *mdown; + + mdown = find_module_by_name(ins->submod_name); + if (!mdown) { + fprintf(stderr, + "instance %s in module %s: lower module \"%s\" not found\n", + ins->inst_name, mup->name, ins->submod_name); + exit(1); + } + ins->submod_def = mdown; + if (ins->connect_by_order) + connect_by_order(mup, ins); + else + connect_by_name(mup, ins); + check_width_match(mup, ins); +} + +static void +linkpass_process_mod(mod) + struct module_def *mod; +{ + register struct module_def_subinst *ins; + + for (ins = mod->subinst; ins; ins = ins->next) + linkpass_process_inst(mod, ins); +} + +link_pass() +{ + register struct module_def *m; + + for (m = glob_module_list; m; m = m->next) { + if (m->is_primitive) + continue; + if (!m->nports) + toplevel_candidate(m); + linkpass_process_mod(m); + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/main.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,90 @@ +/* + * main() function for ueda-sverp + */ + +#include <stdio.h> +#include "struct.h" + +struct module_def *glob_module_list, *top_module_def; +char *primitives_filename = "primitives", *top_module_expl; +int verbose, top_module_candidates; +char *output_filename = "sverp.out"; + +static void +usage() +{ + fprintf(stderr, +"usage: ueda-sverp [-p primfile] [-t top-module] [-v] verilog-sources\n"); + exit(1); +} + +static void +process_options(argc, argv) + char **argv; +{ + register int c; + extern char *optarg; + + while ((c = getopt(argc, argv, "I:o:p:t:v")) != EOF) { + switch (c) { + case 'I': + add_symfile_dir(optarg); + continue; + case 'o': + output_filename = optarg; + continue; + case 'p': + primitives_filename = optarg; + continue; + case 't': + top_module_expl = optarg; + continue; + case 'v': + verbose++; + continue; + default: + usage(); + } + } +} + +main(argc, argv) + char **argv; +{ + extern int optind; + + process_options(argc, argv); + if (optind >= argc) + usage(); + for (; optind < argc; optind++) { + if (verbose) + printf("Reading Verilog source %s\n", argv[optind]); + read_verilog_file(argv[optind]); + } + if (top_module_expl) + process_explicit_topmod(); + if (verbose) + printf("Reading primitive definitions from %s\n", + primitives_filename); + set_default_sympath(); /* for xGA definition files */ + read_primitives_file(primitives_filename); + if (verbose) + printf("Linking instantiations to lower modules\n"); + link_pass(); + if (!top_module_def) { + fprintf(stderr, "error: no top module found\n"); + exit(1); + } + if (!top_module_expl && top_module_candidates > 1) { + fprintf(stderr, + "error: more than one top module candidate, use -t option\n"); + exit(1); + } + if (verbose) + printf("Elaborating hierarchy from top module %s\n", + top_module_def->name); + elaborate_module(top_module_def, top_module_def->name, "", 0); + tally_output_nets(); + generate_output(); + exit(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/misc.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,48 @@ +/* + * ueda-sverp miscellaneous functions + */ + +#include <stdio.h> +#include <strings.h> +#include "struct.h" + +extern struct module_def *glob_module_list, *top_module_def; +extern char *top_module_expl; + +struct module_def * +find_module_by_name(namesought) + register char *namesought; +{ + register struct module_def *m; + + for (m = glob_module_list; m; m = m->next) + if (!strcmp(m->name, namesought)) + break; + return(m); +} + +process_explicit_topmod() +{ + register struct module_def *mod; + + mod = find_module_by_name(top_module_expl); + if (!mod) { + fprintf(stderr, "error: module \"%s\" (-t option) not found\n", + top_module_expl); + exit(1); + } + if (mod->is_primitive) { + fprintf(stderr, + "error: module %s selected with -t is a primitive\n", + top_module_expl); + exit(1); + } + if (mod->nports) { + fprintf(stderr, + "error: module %s (-t option) has ports and thus cannot be top\n", + top_module_expl); + exit(1); + } + /* all checks passed */ + top_module_def = mod; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/output.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,156 @@ +/* + * ueda-sverp netlist output + */ + +#include <stdio.h> +#include <strings.h> +#include "struct.h" + +extern struct output_net *output_net_head; +extern struct output_element *output_element_head; +extern int total_good_nets, total_singular_nets, total_null_nets; +extern int total_output_elements; +extern char *output_filename; + +static FILE *outF; +static int net_comment_column; + +static void +find_net_comment_column() +{ + register struct output_net *net; + register int len, maxlen; + + maxlen = 0; + for (net = output_net_head; net; net = net->next) { + if (net->npoints < 2) + continue; + len = strlen(net->name); + if (len > maxlen) + maxlen = len; + } + maxlen += 4; + do + maxlen++; + while (maxlen % 8); + net_comment_column = maxlen; +} + +static void +emit_good_nets() +{ + register struct output_net *net; + register int col; + + fprintf(outF, "\n# Elaborated net wires (%d total):\n#\n", + total_good_nets); + for (net = output_net_head; net; net = net->next) { + if (net->npoints < 2) + continue; + fprintf(outF, "NET %s", net->name); + col = 4 + strlen(net->name); + do { + fputc('\t', outF); + col += 8; + col &= ~7; + } while (col < net_comment_column); + fprintf(outF, "# %d points\n", net->npoints); + } +} + +static void +emit_singular_nets() +{ + register struct output_net *net; + + fprintf(outF, + "\n# Singular nets converted into no-connects (%d total):\n#\n", + total_singular_nets); + for (net = output_net_head; net; net = net->next) { + if (net->npoints != 1) + continue; + fprintf(outF, "# %s\n", net->name); + } +} + +static void +emit_null_nets() +{ + register struct output_net *net; + + fprintf(outF, "\n# Net wires declared but not used (%d total):\n#\n", + total_null_nets); + for (net = output_net_head; net; net = net->next) { + if (net->npoints) + continue; + fprintf(outF, "# %s\n", net->name); + } +} + +static void +emit_output_element(elem) + struct output_element *elem; +{ + register struct module_def *mod = elem->prim_def; + register struct module_net_def *port; + register struct output_net **connp = elem->connections, *conn; + char *pinkw, *pinname; + + fprintf(outF, "\nCOMPONENT %s {\n PRIMITIVE %s\n\n", + elem->hier_inst_name, mod->name); + if (mod->prim_is_mapped) + pinkw = "PINMAP"; + else + pinkw = "PIN"; + for (port = mod->nets; port; port = port->next) { + pinname = port->name; + if (mod->prim_numeric_pins) + pinname += 4; + fprintf(outF, " %s %s = ", pinkw, pinname); + conn = *connp++; + if (conn->name) { + if (conn->npoints > 1) + fprintf(outF, "NET %s", conn->name); + else + fprintf(outF, "NC (singular net %s)", + conn->name); + } else + fprintf(outF, "NC (module %s line %d inst %s)", + conn->nc_module_name, conn->nc_module_lineno, + conn->nc_module_inst); + fputc('\n', outF); + } + fputs("}\n", outF); +} + +static void +emit_output_elements() +{ + register struct output_element *elem; + + fprintf(outF, "\n# Total instantiated components: %d\n", + total_output_elements); + for (elem = output_element_head; elem; elem = elem->next) + emit_output_element(elem); +} + +generate_output() +{ + outF = fopen(output_filename, "w"); + if (!outF) { + perror(output_filename); + exit(1); + } + fputs("# This netlist has been generated by ueda-sverp\n", outF); + fputs("# from structural Verilog sources\n", outF); + if (total_good_nets) { + find_net_comment_column(); + emit_good_nets(); + } + if (total_singular_nets) + emit_singular_nets(); + if (total_null_nets) + emit_null_nets(); + emit_output_elements(); + fclose(outF); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/prim.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,190 @@ +/* + * Parsing of the primitives definition file happens here. + */ + +#include <stdio.h> +#include <strings.h> +#include "../libueda/xga.h" +#include "struct.h" +#include "lexer.h" + +extern char *malloc(); + +extern struct grid_pkg_desc *read_grid_pkg_file(); + +extern struct module_def *glob_module_list; + +extern char *parser_filename; +extern FILE *parser_readF; +extern int parser_lineno; +extern char parser_read_word[]; +extern int parser_read_number; +extern int pushback_token; + +static struct module_def *curmod; + +static void +create_module() +{ + register struct module_def *mod, **modp; + char *buf; + + for (modp = &glob_module_list; mod = *modp; modp = &mod->next) { + if (!strcmp(mod->name, parser_read_word)) + parse_error("primitive conflicts with a module name"); + } + buf = malloc(sizeof(struct module_def) + strlen(parser_read_word) + 1); + if (!buf) { + perror("malloc"); + exit(1); + } + mod = (struct module_def *) buf; + bzero(mod, sizeof(struct module_def)); + buf += sizeof(struct module_def); + strcpy(buf, parser_read_word); + mod->name = buf; + mod->is_primitive = 1; + *modp = mod; + curmod = mod; +} + +static void +add_pin(pinname) + register char *pinname; +{ + register struct module_net_def *n, **np; + char *buf; + + for (np = &curmod->nets; n = *np; np = &n->next) { + if (!strcmp(n->name, pinname)) + parse_error("duplicate pin name"); + } + buf = malloc(sizeof(struct module_net_def) + strlen(pinname) + 1); + if (!buf) { + perror("malloc"); + exit(1); + } + n = (struct module_net_def *) buf; + bzero(n, sizeof(struct module_net_def)); + buf += sizeof(struct module_net_def); + strcpy(buf, pinname); + n->name = buf; + n->is_port = 1; + n->def_complete = 1; + n->bus_width = 1; + n->array_index = curmod->nports; + *np = n; + curmod->nports++; + curmod->nwires_ports++; +} + +static void +handle_num_pins() +{ + int t; + register int i; + char namebuf[MAXDIGITS+5]; + + curmod->prim_numeric_pins = 1; + t = get_token(); + if (t != NUMBER) + parse_error("expected a number after numpins"); + for (i = 1; i <= parser_read_number; i++) { + sprintf(namebuf, "pin_%d", i); + add_pin(namebuf); + } +} + +static void +handle_named_pins(ismapped) +{ + register int t; + + curmod->prim_is_mapped = ismapped; + t = get_token(); + if (t != '(') + parse_error("expected '(' after named_pins or mapped_pins"); + for (;;) { + t = get_token(); + if (t == ')') + return; + if (t != WORD) + parse_error("expected pin name"); + add_pin(parser_read_word); + t = get_token(); + if (t == ')') + return; + if (t != ',') + parse_error("expected ',' or ')' in pin name list"); + } +} + +static void +handle_grid_pkg() +{ + int t; + register struct grid_pkg_desc *desc; + register int r, c; + char namebuf[32]; + + t = get_token(); + if (t != QSTRING) + parse_error("expected quoted filename after grid"); + desc = read_grid_pkg_file(parser_read_word); + for (r = 0; r < desc->nrows; r++) + for (c = 0; c < desc->ncolumns; c++) { + if (desc->holes_array[r * desc->ncolumns + c]) + continue; + sprintf(namebuf, "%c%d", desc->row_letters[r], c + 1); + add_pin(namebuf); + } + free_grid_pkg_desc(desc); +} + +read_primitives_file(filename_arg) + char *filename_arg; +{ + register int t; + + parser_filename = filename_arg; + parser_readF = fopen(parser_filename, "r"); + if (!parser_readF) { + perror(parser_filename); + exit(1); + } + parser_lineno = 1; + pushback_token = 0; + + for (;;) { + t = get_token(); + if (!t) + break; + if (t != WORD) + parse_error("expected primitive name"); + create_module(); + t = get_token(); + if (t != WORD) + parse_error("expected pins type keyword"); + if (!strcmp(parser_read_word, "numpins")) + handle_num_pins(); + else if (!strcmp(parser_read_word, "grid")) + handle_grid_pkg(); + else if (!strcmp(parser_read_word, "named_pins")) + handle_named_pins(0); + else if (!strcmp(parser_read_word, "mapped_pins")) + handle_named_pins(1); + else { + fprintf(stderr, + "%s line %d: \"%s\" is not an understood primitive type\n", + parser_filename, parser_lineno, + parser_read_word); + exit(1); + } + t = get_token(); + if (t != ';') + parse_error("expected terminating ';'"); + } + + fclose(parser_readF); + return(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/struct.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,92 @@ +/* + * Data structures for our structural Verilog to flat netlist processor + */ + +/* + * Definition of a module as a thing in itself, before elaboration + */ +struct module_def { + char *name; + struct module_def *next; + int is_primitive; + /* ports and internal nets */ + struct module_net_def *nets; + int nports; + /* counts of individual wires (buses expanded) */ + int nwires_ports; + int nwires_internal; + /* downward instantiations */ + struct module_def_subinst *subinst; + /* primitives only */ + int prim_numeric_pins; + int prim_is_mapped; +}; + +/* + * Definition of a wire or bus visible in a module (thing-in-itself), + * either port or internal wire. + */ +struct module_net_def { + char *name; + struct module_net_def *next; + int is_port; + int def_complete; + int is_bus; + int bus_msb; + int bus_lsb; + int bus_width; + int array_index; +}; + +/* + * Definition of an instantiation statement in a module as a thing-in-itself + */ +struct module_def_subinst { + char *submod_name; + struct module_def *submod_def; + char *inst_name; + struct module_def_subinst *next; + struct connect_entry *connections; + int connect_by_order; +}; + +/* + * Definition of a connection from a module to a downward port + */ +struct connect_entry { + struct connect_entry *next; + /* upper end of the connection */ + struct module_net_def *up_netdef; /* NULL means no connect */ + int up_offset; + int up_width; + /* lower end of the connection before link pass */ + char *down_portname; /* NULL means connect by order */ + int down_range_given; + int down_range_msb; + int down_range_lsb; + /* lower end of the connection after link pass */ + struct module_net_def *down_portdef; + int down_offset; + int down_width; + /* source line number */ + int src_lineno; +}; + +/* output of the elaboration pass */ + +struct output_net { + char *name; /* NULL means no connect */ + int npoints; /* # of package pins connected to this net */ + struct output_net *next; + /* no-connect pseudo-nets */ + char *nc_module_name; + int nc_module_lineno; + char *nc_module_inst; +}; + +struct output_element { + struct module_def *prim_def; + char *hier_inst_name; + struct output_net **connections; + struct output_element *next; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/sverp/vparse.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,512 @@ +/* + * Parser for the minimal subset of Verilog we grok + */ + +#include <stdio.h> +#include <strings.h> +#include "struct.h" +#include "lexer.h" + +extern char *malloc(); + +extern struct module_def *glob_module_list; + +extern char *parser_filename; +extern FILE *parser_readF; +extern int parser_lineno; +extern char parser_read_word[]; +extern int parser_read_number; +extern int pushback_token; + +static struct module_def *curmod; +static struct module_def_subinst *subinst; +static struct connect_entry *curconn, **subinst_nextconn; + +/* internal (to the parser) structure for passing range info */ +struct range_info { + int range_given; + int range_msb; + int range_lsb; +}; + +static int +capture_range(spec) + struct range_info *spec; +{ + register int t; + + t = get_token(); + if (t != '[') { + pushback_token = t; + bzero(spec, sizeof(struct range_info)); + return(0); + } + spec->range_given = 1; + t = get_token(); + if (t != NUMBER) + parse_error("expected number after '['"); + spec->range_msb = parser_read_number; + t = get_token(); + if (t == ']') { + spec->range_lsb = spec->range_msb; + return(1); + } + if (t != ':') + parse_error("expected ':' or ']' after MSB number"); + t = get_token(); + if (t != NUMBER) + parse_error("expected number after ':'"); + spec->range_lsb = parser_read_number; + t = get_token(); + if (t != ']') + parse_error("expected ']' after LSB number"); + return(1); +} + +static void +create_module() +{ + register struct module_def *mod, **modp; + char *buf; + + for (modp = &glob_module_list; mod = *modp; modp = &mod->next) { + if (!strcmp(mod->name, parser_read_word)) + parse_error("duplicate module name"); + } + buf = malloc(sizeof(struct module_def) + strlen(parser_read_word) + 1); + if (!buf) { + perror("malloc"); + exit(1); + } + mod = (struct module_def *) buf; + bzero(mod, sizeof(struct module_def)); + buf += sizeof(struct module_def); + strcpy(buf, parser_read_word); + mod->name = buf; + *modp = mod; + curmod = mod; +} + +static void +add_port() +{ + register struct module_net_def *n, **np; + char *buf; + + for (np = &curmod->nets; n = *np; np = &n->next) { + if (!strcmp(n->name, parser_read_word)) + parse_error("duplicate port name in module line"); + } + buf = malloc(sizeof(struct module_net_def) + strlen(parser_read_word) + + 1); + if (!buf) { + perror("malloc"); + exit(1); + } + n = (struct module_net_def *) buf; + bzero(n, sizeof(struct module_net_def)); + buf += sizeof(struct module_net_def); + strcpy(buf, parser_read_word); + n->name = buf; + n->is_port = 1; + *np = n; + curmod->nports++; +} + +static void +process_port_list() +{ + register int t; + + for (;;) { + t = get_token(); + if (t == ')') + return; + if (t != WORD) + parse_error("expected port name in module line"); + add_port(); + t = get_token(); + if (t == ')') + return; + if (t != ',') + parse_error("expected ',' or ')' in module line"); + } +} + +static void +netdef_set_businfo(n, range) + register struct module_net_def *n; + register struct range_info *range; +{ + if (!range->range_given) { + n->is_bus = 0; + n->bus_width = 1; + return; + } + if (range->range_msb == range->range_lsb) + parse_error("bus declaration with MSB==LSB is meaningless"); + n->is_bus = 1; + n->bus_msb = range->range_msb; + n->bus_lsb = range->range_lsb; + if (n->bus_msb > n->bus_lsb) + n->bus_width = n->bus_msb - n->bus_lsb + 1; + else + n->bus_width = n->bus_lsb - n->bus_msb + 1; +} + +static void +complete_port_def(range) + struct range_info *range; +{ + register struct module_net_def *n; + + for (n = curmod->nets; n; n = n->next) + if (!strcmp(n->name, parser_read_word)) + break; + if (!n) { + fprintf(stderr, "%s line %d: no port named %s\n", + parser_filename, parser_lineno, parser_read_word); + exit(1); + } + if (n->def_complete) { + fprintf(stderr, + "%s line %d: inout decl for %s is a redefinition\n", + parser_filename, parser_lineno, parser_read_word); + exit(1); + } + netdef_set_businfo(n, range); + n->def_complete = 1; +} + +static void +add_wire(range) + struct range_info *range; +{ + register struct module_net_def *n, **np; + char *buf; + + for (np = &curmod->nets; n = *np; np = &n->next) + if (!strcmp(n->name, parser_read_word)) { + fprintf(stderr, + "%s line %d: wire %s is a redefinition\n", + parser_filename, parser_lineno, + parser_read_word); + exit(1); + } + buf = malloc(sizeof(struct module_net_def) + strlen(parser_read_word) + + 1); + if (!buf) { + perror("malloc"); + exit(1); + } + n = (struct module_net_def *) buf; + bzero(n, sizeof(struct module_net_def)); + buf += sizeof(struct module_net_def); + strcpy(buf, parser_read_word); + n->name = buf; + *np = n; + netdef_set_businfo(n, range); + n->def_complete = 1; +} + +static void +process_netdef_line(is_port) +{ + struct range_info range; + register int t; + + capture_range(&range); + for (;;) { + t = get_token(); + if (t == ';') + return; + if (t != WORD) + parse_error("expected ident on wire def line"); + if (is_port) + complete_port_def(&range); + else + add_wire(&range); + t = get_token(); + if (t == ';') + return; + if (t != ',') + parse_error("expected ',' or ';' in wire def line"); + } +} + +static void +create_subinst(submod_name, inst_name) + char *submod_name, *inst_name; +{ + register struct module_def_subinst *s, **sp; + char *buf; + + for (sp = &curmod->subinst; s = *sp; sp = &s->next) + if (!strcmp(s->inst_name, inst_name)) + parse_error("duplicate subinstance name"); + buf = malloc(sizeof(struct module_def_subinst) + strlen(submod_name) + + strlen(inst_name) + 2); + if (!buf) { + perror("malloc"); + exit(1); + } + s = (struct module_def_subinst *) buf; + bzero(s, sizeof(struct module_def_subinst)); + buf += sizeof(struct module_def_subinst); + strcpy(buf, submod_name); + s->submod_name = buf; + buf += strlen(submod_name) + 1; + strcpy(buf, inst_name); + s->inst_name = buf; + *sp = s; + subinst = s; + subinst_nextconn = &s->connections; +} + +static void +alloc_connect_entry(downport) + char *downport; +{ + struct connect_entry *s; + int len; + char *buf; + + if (downport) + len = sizeof(struct connect_entry) + strlen(downport) + 1; + else + len = sizeof(struct connect_entry); + s = (struct connect_entry *) malloc(len); + if (!s) { + perror("malloc"); + exit(1); + } + bzero(s, sizeof(struct connect_entry)); + if (downport) { + buf = (char *)(s + 1); + strcpy(buf, downport); + s->down_portname = buf; + } + curconn = s; + *subinst_nextconn = s; + subinst_nextconn = &s->next; +} + +static void +connect_upper() +{ + struct range_info range; + register struct module_net_def *n; + + for (n = curmod->nets; n; n = n->next) + if (!strcmp(n->name, parser_read_word)) + break; + if (!n) { + fprintf(stderr, "%s line %d: no net named %s\n", + parser_filename, parser_lineno, parser_read_word); + exit(1); + } + curconn->up_netdef = n; + if (!capture_range(&range)) { + curconn->up_offset = 0; + curconn->up_width = n->bus_width; + return; + } + if (!n->is_bus) { + fprintf(stderr, + "%s line %d: net %s is not a bus, range spec is meaningless\n", + parser_filename, parser_lineno, n->name); + exit(1); + } + if (n->bus_msb > n->bus_lsb) { + if (range.range_msb < range.range_lsb) { +error_reversed: fprintf(stderr, + "%s line %d: reversed range on bus %s\n", + parser_filename, parser_lineno, n->name); + exit(1); + } + if (range.range_msb > n->bus_msb) { +error_outofrange: fprintf(stderr, + "%s line %d: subrange of bus %s to connect exceeds full bus range\n", + parser_filename, parser_lineno, n->name); + exit(1); + } + if (range.range_lsb < n->bus_lsb) + goto error_outofrange; + curconn->up_offset = n->bus_msb - range.range_msb; + curconn->up_width = range.range_msb - range.range_lsb + 1; + } else { + if (range.range_msb > range.range_lsb) + goto error_reversed; + if (range.range_msb < n->bus_msb) + goto error_outofrange; + if (range.range_lsb > n->bus_lsb) + goto error_outofrange; + curconn->up_offset = range.range_msb - n->bus_msb; + curconn->up_width = range.range_lsb - range.range_msb + 1; + } +} + +static void +connect_by_name() +{ + struct range_info range; + register int t; + + for (;;) { + t = get_token(); + if (t == ')') + return; + if (t != '.') + parse_error("expected '.' for downward port"); + t = get_token(); + if (t != WORD) + parse_error("expected downward port name after '.'"); + alloc_connect_entry(parser_read_word); + curconn->src_lineno = parser_lineno; + if (capture_range(&range)) { + curconn->down_range_given = 1; + curconn->down_range_msb = range.range_msb; + curconn->down_range_lsb = range.range_lsb; + } + t = get_token(); + if (t != '(') + parse_error("expected '(' for connect-by-name"); + t = get_token(); + if (t != ')') { + if (t != WORD) + parse_error( + "expected in-module net name to connect"); + connect_upper(); + t = get_token(); + if (t != ')') + parse_error("expected ')' for connect-by-name"); + } + t = get_token(); + if (t == ')') + return; + if (t != ',') + parse_error("expected ',' or ')' in connection list"); + } +} + +static void +connect_by_order() +{ + register int t; + + for (;;) { + t = get_token(); + if (t == ')') + return; + if (t != WORD) + parse_error("expected in-module net name to connect"); + alloc_connect_entry(0); + curconn->src_lineno = parser_lineno; + connect_upper(); + subinst->connect_by_order++; + t = get_token(); + if (t == ')') + return; + if (t != ',') + parse_error("expected ',' or ')' in connection list"); + } +} + +static void +process_subinst() +{ + char submod_name[MAXWORD+1]; + register int t; + + strcpy(submod_name, parser_read_word); + t = get_token(); + if (t != WORD) + parse_error("expected instance name after submodule name"); + create_subinst(submod_name, parser_read_word); + t = get_token(); + if (t != '(') + parse_error("expected '(' after <module> <instance>"); + t = get_token(); + pushback_token = t; + if (t == '.') + connect_by_name(); + else + connect_by_order(); + t = get_token(); + if (t != ';') + parse_error("expected ';' at the end of instantiation"); +} + +static void +preen_module_nets() +{ + register struct module_net_def *n; + register int idx; + + idx = 0; + for (n = curmod->nets; n; n = n->next) { + if (!n->def_complete) { + fprintf(stderr, + "error: definition of port %s in module %s is incomplete\n", + n->name, curmod->name); + exit(1); + } + n->array_index = idx; + idx += n->bus_width; + if (n->is_port) + curmod->nwires_ports += n->bus_width; + else + curmod->nwires_internal += n->bus_width; + } +} + +read_verilog_file(filename_arg) + char *filename_arg; +{ + register int t; + + parser_filename = filename_arg; + parser_readF = fopen(parser_filename, "r"); + if (!parser_readF) { + perror(parser_filename); + exit(1); + } + parser_lineno = 1; + pushback_token = 0; + + t = get_token(); + if (t != WORD || strcmp(parser_read_word, "module")) + parse_error("first token is expected to be \"module\""); + t = get_token(); + if (t != WORD) + parse_error("module name expected after \"module\""); + create_module(); + t = get_token(); + if (t != '(') + parse_error("expected '(' after module <modname>"); + process_port_list(); + t = get_token(); + if (t != ';') + parse_error("expected ';' at the end of module line"); + + for (;;) { + t = get_token(); + if (t != WORD) + parse_error( + "expected word token at the beginning of module item"); + if (!strcmp(parser_read_word, "endmodule")) + break; + if (!strcmp(parser_read_word, "input") || + !strcmp(parser_read_word, "output") || + !strcmp(parser_read_word, "inout")) + process_netdef_line(1); + else if (!strcmp(parser_read_word, "wire")) + process_netdef_line(0); + else + process_subinst(); + } + + fclose(parser_readF); + preen_module_nets(); + return(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,1 @@ +uschem-netlist
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,17 @@ +CFLAGS= -O +OBJS= dowork.o main.o netobj.o pcbout.o pinlist.o pintonet.o stats.o nets.o \ + nlcomp.o pinconn.o +LIBS= ../libuschem/libuschem.a ../libueda/libueda.a +PROG= uschem-netlist +BINDIR= /usr/local + +all: ${PROG} + +${PROG}: ${OBJS} ${LIBS} + ${CC} -o $@ ${OBJS} ${LIBS} + +install: + install -c -o bin -g bin -m 755 ${PROG} ${BINDIR} + +clean: + rm -f *.[ao] a.out core errs ${PROG}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/dowork.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,55 @@ +#include <sys/types.h> +#include <stdio.h> +#include "netlist.h" +#include "../libuschem/schemstruct.h" + +extern struct nlcomp *mclcomp_to_nlcomp(); +extern struct pinconn *alloc_pinconn(); +extern char *get_compinst_attr(); +extern char *pinname_to_pinnumber(); + +extern struct schem *curschem; +extern int global_errflag; + +extern struct net noconnect_pseudo_net; + +do_connect(net, compinst, soughtpin, bynum, lineno) + struct net *net; + struct schemobj *compinst; + char *soughtpin; + int bynum, lineno; +{ + register struct component *comp; + register char *pinnum; + char *slot; + register struct pinconn *pc; + + comp = compinst->compobj_mclcomp; + if (bynum) + pinnum = soughtpin; + else { + slot = get_compinst_attr(compinst, "slot"); + pinnum = pinname_to_pinnumber(comp, soughtpin, slot); + if (!pinnum) { + /* error msg already printed */ + global_errflag++; + return; + } + } + pc = alloc_pinconn(); + pc->comp = mclcomp_to_nlcomp(comp); + pc->pinnum = pinnum; + pc->net = net; + pc->origin_file = curschem->orig_filename; + pc->origin_line = lineno; + if (record_pin_connection(pc)) + free(pc); +} + +do_noconnect(compinst, soughtpin, bynum, lineno) + struct schemobj *compinst; + char *soughtpin; + int bynum, lineno; +{ + do_connect(&noconnect_pseudo_net, compinst, soughtpin, bynum, lineno); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/main.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,148 @@ +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "../libuschem/schemstruct.h" + +extern int optind; +extern char *optarg; + +extern char *MCLfile; + +extern struct schem *read_schem(); + +extern int pcb_netlist_output(); +extern int pinlist_output(); +extern int stats_output(); + +struct schem *curschem; +int allow_unnamed_nets, check_completeness, sort_netlist_output; +int global_errflag; +char *outfilename; +FILE *outfile; +int (*do_output)() = pcb_netlist_output; + +main(argc, argv) + char **argv; +{ + register int c; + register struct schem *schem; + char **avp; + + while ((c = getopt(argc, argv, "cI:M:o:O:su")) != EOF) + switch (c) { + case 'c': + check_completeness++; + break; + case 'I': + add_symfile_dir(optarg); + break; + case 'M': + MCLfile = optarg; + break; + case 'o': + outfilename = optarg; + break; + case 'O': + select_output_backend(optarg); + break; + case 's': + sort_netlist_output++; + break; + case 'u': + allow_unnamed_nets++; + break; + default: +usage: fprintf(stderr, "usage: %s [-options] schemfile...\n", + argv[0]); + exit(1); + } + if (!argv[optind]) + goto usage; + + read_MCL(); + hash_MCL(); + set_default_sympath(); + read_pinouts(); + alloc_nlcomp_array(); + + for (avp = argv + optind; *avp; avp++) { + schem = read_schem(*avp); + curschem = schem; + match_schem_to_mcl(schem); + if (hash_component_instances(schem) < 0) + exit(1); + if (preen_graphnets(schem, 1, 0, 0, 0) < 0) + exit(1); + process_schem(); + } + if (global_errflag) + fprintf(stderr, "Errors found; netlist may be incomplete\n"); + do_output(); + + exit(0); +} + +process_schem() +{ + register struct schemobj *obj; + int has_netlines = 0; + + for (obj = curschem->obj_next; obj != (struct schemobj *)curschem; + obj = obj->obj_next) + switch (obj->obj_type) { + case OBJTYPE_COMPINST: + check_compinst_pintonet(obj); + continue; + case OBJTYPE_NET: + case OBJTYPE_GRAPHNET: + process_netobj(obj); + continue; + case OBJTYPE_NETLINE: + if (!has_netlines) { + fprintf(stderr, + "%s contains NetLine objects which are not netlistable\n", + curschem->orig_filename); + has_netlines++; + global_errflag++; + } + continue; + } +} + +struct output_backend_spec { + char *keyword; + int (*func)(); +} output_backend_list[] = { + {"pcb", pcb_netlist_output}, + {"geda", pcb_netlist_output}, + {"pinlist", pinlist_output}, + {"stats", stats_output}, + {NULL, NULL}}; + +select_output_backend(arg) + char *arg; +{ + register struct output_backend_spec *tp; + + for (tp = output_backend_list; tp->keyword; tp++) + if (!strcmp(tp->keyword, arg)) + break; + if (!tp->func) { + fprintf(stderr, "%s: unknown or unimplemented output backend\n", + arg); + exit(1); + } + do_output = tp->func; +} + +open_output_file() +{ + if (outfilename) { + outfile = fopen(outfilename, "w"); + if (!outfile) { + perror(outfilename); + exit(1); + } + } else + outfile = stdout; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/netlist.h Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,28 @@ +/* + * Netlist data structures + */ + +struct nlcomp { + struct component *mclcomp; + int npins; + struct pinconn **pintab; + struct pinconn *pinchain; + int nconnects; +}; + +struct net { + char *netname; + struct pinconn *pins; + int npoints; + struct net *next; +}; + +struct pinconn { + struct nlcomp *comp; + char *pinnum; + struct net *net; + char *origin_file; + int origin_line; + struct pinconn *next_in_net; + struct pinconn *next_in_comp; +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/netobj.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,61 @@ +#include <sys/types.h> +#include <stdio.h> +#include "netlist.h" +#include "../libuschem/schemstruct.h" + +extern struct net *alloc_nethead(); +extern struct net *get_nethead_for_netname(); + +extern struct schem *curschem; +extern int global_errflag; + +static struct net *curnet; +static struct schemobj *cur_grouphead; + +process_netobj(obj) + register struct schemobj *obj; +{ + register struct netpoint *netpt; + + if (!obj->netobj_grouphead || obj->netobj_grouphead != cur_grouphead) { + curnet = NULL; + cur_grouphead = obj->netobj_grouphead; + } + if (!curnet && obj->netobj_netname) + curnet = get_nethead_for_netname(obj->netobj_netname); + for (netpt = obj->netobj_points; netpt; netpt = netpt->netpt_next) + if (netpt->netpt_type == NETPT_TYPE_PIN) + process_netpoint(obj, netpt); +} + +process_netpoint(netobj, netpt) + struct schemobj *netobj; + register struct netpoint *netpt; +{ + struct schemobj *comp; + char *soughtpin; + int bynum; + + if (!netpt->netpt_pin_nameref) { + fprintf(stderr, +"%s: line %d: Pin connection specified by coordinates only not netlistable\n", + curschem->orig_filename, netobj->obj_lineno); + fprintf(stderr, "Run uschem-rewrite -g %s to fix\n", + curschem->orig_filename); + global_errflag++; + return; + } + if (parse_pin_nameref(curschem, netobj->obj_lineno, + netpt->netpt_pin_nameref, &comp, &soughtpin, + &bynum) < 0) { + /* error msg already printed */ + global_errflag++; + return; + } + /* handle unnamed nets -- point of no return */ + if (!curnet) { + curnet = alloc_nethead(); + add_unnamed_net(curnet); + } + do_connect(curnet, comp, soughtpin, bynum, netobj->obj_lineno); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/nets.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,127 @@ +/* + * Working with struct net objects (netheads) + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "netlist.h" + +extern char *malloc(); + +#define HASH_SIZE 1103 + +static struct net *named_net_hash[HASH_SIZE]; +int total_named_nets; + +struct net **sorted_named_nets; + +struct net *unnamed_net_list; +int total_unnamed_nets; + +struct net noconnect_pseudo_net = {"NO_CONNECT", NULL, 0, NULL}; + +static int +hash_netname(str) + char *str; +{ + register u_long accum = 0; + register char *cp; + register int c, i; + + for (cp = str, i = 1; c = *cp; cp++, i++) + accum += c * i; + return(accum % HASH_SIZE); +} + +struct net * +alloc_nethead() +{ + register struct net *n; + + n = (struct net *) malloc(sizeof(struct net)); + if (!n) { + perror("malloc"); + exit(1); + } + bzero(n, sizeof(struct net)); + return(n); +} + +struct net * +get_nethead_for_netname(netname) + register char *netname; +{ + register struct net *n, **np; + + for (np = named_net_hash + hash_netname(netname); n = *np; + np = &n->next) + if (!strcmp(n->netname, netname)) + return(n); + n = alloc_nethead(); + n->netname = netname; + *np = n; + total_named_nets++; + return(n); +} + +report_named_net_hash_quality() +{ + int maxchain; + register int hb, curchain; + register struct net *n; + + for (hb = 0, maxchain = 0; hb < HASH_SIZE; hb++) { + for (n = named_net_hash[hb], curchain = 0; n; n = n->next) + curchain++; + if (curchain > maxchain) + maxchain = curchain; + } + printf("Total named nets: %d\n", total_named_nets); + printf("Longest hash chain: %d\n", maxchain); +} + +named_net_forall(callback) + int (*callback)(); +{ + register struct net *n, **hb; + register int i; + + for (hb = named_net_hash, i = 0; i < HASH_SIZE; hb++, i++) + for (n = *hb; n; n = n->next) + callback(n); +} + +static +netname_sort_compare(net1, net2) + struct net **net1, **net2; +{ + return(strcmp((*net1)->netname, (*net2)->netname)); +} + +sort_named_nets() +{ + register struct net *n, **hb, **op; + register int i; + + sorted_named_nets = + (struct net **) malloc(sizeof(struct net *) * total_named_nets); + if (!sorted_named_nets) { + perror("malloc"); + exit(1); + } + op = sorted_named_nets; + for (hb = named_net_hash, i = 0; i < HASH_SIZE; hb++, i++) + for (n = *hb; n; n = n->next) + *op++ = n; + qsort(sorted_named_nets, total_named_nets, sizeof(struct net *), + netname_sort_compare); +} + +add_unnamed_net(n) + register struct net *n; +{ + n->next = unnamed_net_list; + unnamed_net_list = n; + total_unnamed_nets++; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/nlcomp.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,63 @@ +#include <sys/types.h> +#include <stdio.h> +#include "../libueda/mcl.h" +#include "netlist.h" + +extern char *malloc(); + +extern struct component components[]; +extern int ncomponents; + +extern char *get_comp_attr(); + +struct nlcomp *netlist_comps; + +alloc_nlcomp_array() +{ + register int i; + + netlist_comps = (struct nlcomp *) + malloc(sizeof(struct nlcomp) * ncomponents); + if (!netlist_comps) { + perror("malloc"); + exit(1); + } + bzero(netlist_comps, sizeof(struct nlcomp) * ncomponents); + for (i = 0; i < ncomponents; i++) { + netlist_comps[i].mclcomp = components + i; + fill_nlcomp(netlist_comps + i); + } +} + +fill_nlcomp(nlc) + register struct nlcomp *nlc; +{ + char *npins_attr; + register int n; + register struct pinconn **pintab; + + npins_attr = get_comp_attr(nlc->mclcomp, "npins"); + if (!npins_attr) + return; + n = atoi(npins_attr); + if (n <= 0) { + fprintf(stderr, "%s: invalid npins attribute\n", + nlc->mclcomp->name); + exit(1); + } + nlc->npins = n; + pintab = (struct pinconn **) malloc(sizeof(struct pinconn *) * n); + if (!pintab) { + perror("malloc"); + exit(1); + } + bzero(pintab, sizeof(struct pinconn *) * n); + nlc->pintab = pintab; +} + +struct nlcomp * +mclcomp_to_nlcomp(comp) + struct component *comp; +{ + return(netlist_comps + (comp - components)); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/pcbout.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,135 @@ +/* + * Netlist output in the gEDA/PCB format + */ + +#include <stdio.h> +#include <strings.h> +#include "../libueda/mcl.h" +#include "netlist.h" + +extern struct net **sorted_named_nets; +extern int total_named_nets; +extern struct net *unnamed_net_list; + +extern FILE *outfile; +extern int allow_unnamed_nets, check_completeness, sort_netlist_output; + +static int unnamed_net_count; + +static +emit_net(netname, points) + char *netname; + struct pinconn *points; +{ + register struct pinconn *pc; + int linelen, linefresh; + register int i; + + fprintf(outfile, "%s\t", netname); + linelen = (strlen(netname) + 8) & ~7; + for (pc = points, linefresh = 1; pc; pc = pc->next_in_net) { + i = strlen(pc->comp->mclcomp->name) + strlen(pc->pinnum) + 2; + if (!linefresh && linelen + i > 78) { + fputs(" \\\n\t", outfile); + linelen = 8; + linefresh = 1; + } + if (linefresh) + i--; + else + putc(' ', outfile); + fprintf(outfile, "%s-%s", pc->comp->mclcomp->name, pc->pinnum); + linelen += i; + linefresh = 0; + } + putc('\n', outfile); +} + +static +emit_named_net(net) + register struct net *net; +{ + if (net->npoints == 0) { + fprintf(stderr, "Net %s has no points, discarded\n", + net->netname); + return; + } + if (net->npoints == 1 && check_completeness) + fprintf(stderr, "Warning: net %s has only 1 point\n", + net->netname); + emit_net(net->netname, net->pins); +} + +static +do_sorted_named_nets() +{ + register struct net **np; + register int i; + + for (np = sorted_named_nets, i = 0; i < total_named_nets; np++, i++) + emit_named_net(*np); +} + +static +report_singular_unnamed_net(net) + struct net *net; +{ + register struct pinconn *pc; + + pc = net->pins; + fprintf(stderr, + "Pin %s-%s assigned to a singular unnamed net (%s line %d)\n", + pc->comp->mclcomp->name, pc->pinnum, pc->origin_file, + pc->origin_line); +} + +static +do_unnamed_nets() +{ + register struct net *net; + char bogonetname[32]; + + for (net = unnamed_net_list; net; net = net->next) { + if (net->npoints == 0) { + /* + * These can only result from previous errors, + * i.e., we thought we had a pin going to an unnamed + * net, allocated a nethead for it, but the pin + * turned out to be invalid. + * + * Here we silently discard these aberrations w/o + * printing anything because the original error + * must have already been reported. + */ + continue; + } + if (net->npoints == 1) { + report_singular_unnamed_net(net); + /* don't emit these */ + continue; + } + /* a *real* unnamed net */ + unnamed_net_count++; + if (allow_unnamed_nets) { + sprintf(bogonetname, "unnamed_net_%d", + unnamed_net_count); + emit_net(bogonetname, net->pins); + } + } + if (unnamed_net_count && !allow_unnamed_nets) + fprintf(stderr, "%d unnamed nets left out\n", + unnamed_net_count); +} + +pcb_netlist_output() +{ + open_output_file(); + if (sort_netlist_output) { + sort_named_nets(); + do_sorted_named_nets(); + } else + named_net_forall(emit_named_net); + do_unnamed_nets(); + if (check_completeness) + check_for_unused_comps(); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/pinconn.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,125 @@ +/* + * Recording of pin connections + */ + +#include <stdio.h> +#include <strings.h> +#include "../libueda/mcl.h" +#include "netlist.h" + +extern char *malloc(); + +int total_pin_connections; +int total_expl_noconnects; + +extern struct net noconnect_pseudo_net; + +struct pinconn * +alloc_pinconn() +{ + register struct pinconn *pc; + + pc = (struct pinconn *) malloc(sizeof(struct pinconn)); + if (!pc) { + perror("malloc"); + exit(1); + } + bzero(pc, sizeof(struct pinconn)); + return(pc); +} + +static +report_connection(pc) + register struct pinconn *pc; +{ + register struct net *n; + + n = pc->net; + if (n->netname) + fprintf(stderr, "assigned to net %s by %s line %d\n", + n->netname, pc->origin_file, pc->origin_line); + else + fprintf(stderr, "assigned to an unnamed net by %s line %d\n", + pc->origin_file, pc->origin_line); +} + +record_pin_connection(pc) + register struct pinconn *pc; +{ + register struct nlcomp *nlc; + register struct net *n; + int stat; + + nlc = pc->comp; + if (nlc->npins) + stat = record_pin_connection_tab(pc); + else + stat = record_pin_connection_chain(pc); + if (stat) + return(stat); + n = pc->net; + pc->next_in_net = n->pins; + n->pins = pc; + n->npoints++; + if (n != &noconnect_pseudo_net) { + nlc->nconnects++; + total_pin_connections++; + } else + total_expl_noconnects++; + return(0); +} + +static +record_pin_connection_tab(pc) + register struct pinconn *pc; +{ + register struct nlcomp *nlc; + register int n; + + nlc = pc->comp; + n = atoi(pc->pinnum); + if (n < 1 || n > nlc->npins) { + fprintf(stderr, "%s: line %d: %s pin number %s is invalid\n", + pc->origin_file, pc->origin_line, nlc->mclcomp->name, + pc->pinnum); + exit(1); + } + n--; + if (nlc->pintab[n]) { + if (nlc->pintab[n]->net == pc->net) /* same pin to same net? */ + return(1); /* redundant but harmless */ + fprintf(stderr, + "%s pin %s is connected to more than one net:\n", + nlc->mclcomp->name, pc->pinnum); + report_connection(nlc->pintab[n]); + report_connection(pc); + exit(1); + } + nlc->pintab[n] = pc; + return(0); +} + +static +record_pin_connection_chain(pc) + register struct pinconn *pc; +{ + struct nlcomp *nlc; + struct component *comp; + register struct pinconn *s, **sp; + + nlc = pc->comp; + comp = nlc->mclcomp; + for (sp = &nlc->pinchain; s = *sp; sp = &s->next_in_comp) + if (!strcmp(s->pinnum, pc->pinnum)) { + if (s->net == pc->net) /* same pin to same net? */ + return(1); /* redundant but harmless */ + fprintf(stderr, + "%s pin %s is connected to more than one net:\n", + comp->name, pc->pinnum); + report_connection(s); + report_connection(pc); + exit(1); + } + *sp = pc; + return(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/pinlist.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,86 @@ +/* + * Informal pin list output + */ + +#include <stdio.h> +#include "../libueda/mcl.h" +#include "netlist.h" + +extern struct nlcomp *netlist_comps; +extern int ncomponents; + +extern FILE *outfile; + +static +list_pins_tab(comp) + struct nlcomp *comp; +{ + register struct pinconn **ppc, *pc; + register struct net *n; + int i, npins; + + npins = comp->npins; + for (ppc = comp->pintab, i = 1; i <= npins; ppc++, i++) { + if (pc = *ppc) { + n = pc->net; + if (n->netname) + fprintf(outfile, "\tPin %d = %s (%s line %d)\n", + i, n->netname, pc->origin_file, + pc->origin_line); + else + fprintf(outfile, + "\tPin %d = unnamed net (%s line %d)\n", + i, pc->origin_file, pc->origin_line); + } else + fprintf(outfile, "\tPin %d left unconnected\n", i); + } +} + +static +list_pins_chain(comp) + struct nlcomp *comp; +{ + register struct pinconn *pc; + register struct net *n; + + for (pc = comp->pinchain; pc; pc = pc->next_in_comp) { + n = pc->net; + if (n->netname) + fprintf(outfile, "\tPin %s = %s (%s line %d)\n", + pc->pinnum, n->netname, pc->origin_file, + pc->origin_line); + else + fprintf(outfile, + "\tPin %s = unnamed net (%s line %d)\n", + pc->pinnum, pc->origin_file, pc->origin_line); + } +} + +pinlist_output() +{ + register struct nlcomp *comp; + register int i; + + open_output_file(); + for (comp = netlist_comps, i = 0; i < ncomponents; comp++, i++) { + fprintf(outfile, "%s:\n", comp->mclcomp->name); + if (!comp->nconnects) + fputs("\tNo connections\n", outfile); + else if (comp->pintab) + list_pins_tab(comp); + else + list_pins_chain(comp); + } +} + +check_for_unused_comps() +{ + register struct nlcomp *comp; + register int i; + + for (comp = netlist_comps, i = 0; i < ncomponents; comp++, i++) + if (!comp->nconnects) + fprintf(stderr, + "Warning: component %s has no connections\n", + comp->mclcomp->name); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/pintonet.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,56 @@ +#include <sys/types.h> +#include <stdio.h> +#include "netlist.h" +#include "../libuschem/schemstruct.h" + +extern struct net *get_nethead_for_netname(); + +check_compinst_pintonet(obj) + register struct schemobj *obj; +{ + register struct decoration *decor; + + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) + switch (decor->decor_type) { + case DECOR_TYPE_PINTONET: + handle_pintonet(obj, decor); + continue; + case DECOR_TYPE_NOCONNECT: + handle_noconnect_decor(obj, decor); + continue; + } +} + +handle_pintonet(comp, decor) + struct schemobj *comp; + register struct decoration *decor; +{ + register char *soughtpin; + int bynum; + register struct net *n; + + soughtpin = decor->decorpincon_pin; + if (soughtpin[0] == '#') { + soughtpin++; + bynum = 1; + } else + bynum = 0; + n = get_nethead_for_netname(decor->decorpincon_netname); + do_connect(n, comp, soughtpin, bynum, decor->decor_lineno); +} + +handle_noconnect_decor(comp, decor) + struct schemobj *comp; + register struct decoration *decor; +{ + register char *soughtpin; + int bynum; + + soughtpin = decor->decorpincon_pin; + if (soughtpin[0] == '#') { + soughtpin++; + bynum = 1; + } else + bynum = 0; + do_noconnect(comp, soughtpin, bynum, decor->decor_lineno); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-netlist/stats.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,13 @@ +#include <stdio.h> + +extern int total_unnamed_nets; +extern int total_pin_connections; +extern int total_expl_noconnects; + +stats_output() +{ + report_named_net_hash_quality(); + printf("Total unnamed nets: %d\n", total_unnamed_nets); + printf("Total pin connections: %d\n", total_pin_connections); + printf("Total NoConnect pins: %d\n", total_expl_noconnects); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,1 @@ +uschem-print
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,20 @@ +CFLAGS= -O +OBJS= decor.o gschemcode.o main.o papersize.o pathnames.o printpage.o \ + prolog.o pstring.o +LIBS= ../libuschem/libuschem.a ../libueda/libueda.a +PROG= uschem-print +PSFILES=defaultprefs.ps transfont.ps uschem-procset.ps +BINDIR= /usr/local +SUPDIR= /usr/local/eda/uschem-support + +all: ${PROG} + +${PROG}: ${OBJS} ${LIBS} + ${CC} -o $@ ${OBJS} ${LIBS} + +install: + install -c -o bin -g bin -m 755 ${PROG} ${BINDIR} + install -c -o bin -g bin -m 444 ${PSFILES} ${SUPDIR} + +clean: + rm -f *.[ao] a.out core errs ${PROG}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/decor.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,172 @@ +/* + * Printing object decorations + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "../libueda/mcl.h" +#include "../libuschem/schemstruct.h" +#include "../libuschem/graphsym.h" + +extern char *get_comp_attr(); +extern struct graphsym_pininst *find_comp_pininst(); + +extern struct schem *schem_being_printed; + +extern char *gschem_text_halign[9]; +extern char *gschem_text_valign[9]; + +static int decor_font_ptsize; + +char * +pull_attr_from_obj(obj, attrname) + register struct schemobj *obj; + register char *attrname; +{ + register struct decoration *decor; + + if (obj->obj_type == OBJTYPE_COMPINST) { + if (!strcmp(attrname, "refdes")) + return(obj->compobj_mclcomp->name); + if (!strcmp(attrname, "instname")) + return(obj->compobj_instname); + } + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) + if (decor->decor_type == DECOR_TYPE_ATTR && + !strcmp(decor->decorattr_name, attrname)) + return(decor->decorattr_value); + if (obj->obj_type == OBJTYPE_COMPINST) + return(get_comp_attr(obj->compobj_mclcomp, attrname)); + else + return(NULL); +} + +reset_decor_font() +{ + decor_font_ptsize = 0; +} + +print_obj_decors(obj) + struct schemobj *obj; +{ + register struct decoration *decor; + register char *dispval; + + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) + switch (decor->decor_type) { + case DECOR_TYPE_DISPLAYATTR: + dispval = pull_attr_from_obj(obj, decor->decordisp_attr); + if (dispval) + print_textdisp_decor(decor, dispval); + else + fprintf(stderr, + "%s: line %d: DisplayAttr: attribute %s unknown\n", + schem_being_printed->orig_filename, + decor->decor_lineno, decor->decordisp_attr); + continue; + case DECOR_TYPE_DISPLAYNETNAME: + if (obj->obj_type != OBJTYPE_GRAPHNET) { + fprintf(stderr, + "%s: line %d: DisplayNetName invalid in objects other than GraphNet\n", + schem_being_printed->orig_filename, + decor->decor_lineno); + continue; + } + dispval = obj->netobj_netname; + if (dispval) + print_textdisp_decor(decor, dispval); + else + fprintf(stderr, + "%s: line %d: DisplayNetName on an unnamed GraphNet\n", + schem_being_printed->orig_filename, + decor->decor_lineno); + continue; + case DECOR_TYPE_SYMONPIN: + if (obj->obj_type != OBJTYPE_COMPINST) { + fprintf(stderr, + "%s: line %d: SymOnPin invalid in objects other than components\n", + schem_being_printed->orig_filename, + decor->decor_lineno); + continue; + } + print_symonpin(obj, decor); + continue; + case DECOR_TYPE_GRAPHBLOCK: + print_graphblock(decor->decorgraph_body); + continue; + } +} + +print_textdisp_decor(decor, dispval) + register struct decoration *decor; + char *dispval; +{ + if (decor->decordisp_alignment < 0 || decor->decordisp_alignment > 8) { + fprintf(stderr, + "%s: line %d: display decoration: alignment %d is invalid\n", + schem_being_printed->orig_filename, + decor->decor_lineno, decor->decordisp_alignment); + return; + } + if (decor_font_ptsize != decor->decordisp_ptsize) { + decor_font_ptsize = decor->decordisp_ptsize; + printf("/Helvetica %d selisofnt\n", decor_font_ptsize); + } + emit_ps_string(dispval); + printf(" %s %s %d %d %d Tshow\n", + gschem_text_halign[decor->decordisp_alignment], + gschem_text_valign[decor->decordisp_alignment], + decor->decordisp_rotate, + decor->decordisp_x, decor->decordisp_y); +} + +print_symonpin(comp, symdec) + struct schemobj *comp; + struct decoration *symdec; +{ + struct graphsym *sop_gs; + register struct graphsym_pindef *sop_pindef; + register char *soughtpin; + int bynum; + register struct graphsym_pininst *hostpin; + struct schemobj fakeobj; + + sop_gs = symdec->decorpinsym_gs; + if (sop_gs->gs_npins > 1) { + fprintf(stderr, + "%s: line %d: SymOnPin symbols may not have more than 1 pin\n", + schem_being_printed->orig_filename, + symdec->decor_lineno); + return; + } + sop_pindef = sop_gs->gs_pins; + soughtpin = symdec->decorpinsym_pin; + if (soughtpin[0] == '#') { + bynum = 1; + soughtpin++; + } else + bynum = 0; + hostpin = find_comp_pininst(comp, soughtpin, bynum); + if (!hostpin) { + fprintf(stderr, "%s: line %d: SymOnPin: %s pin %s not found\n", + schem_being_printed->orig_filename, + symdec->decor_lineno, comp->compobj_instname, + symdec->decorpinsym_pin); + return; + } + /* everything located, do it */ + bzero(&fakeobj, sizeof fakeobj); + fakeobj.obj_type = OBJTYPE_GRAPHSYM; + fakeobj.obj_lineno = symdec->decor_lineno; + fakeobj.compobj_graphsym = sop_gs; + fakeobj.compobj_x = -sop_pindef->gspd_x; + fakeobj.compobj_y = -sop_pindef->gspd_y; + if (symdec->decorpinsym_mirror) { + fakeobj.compobj_mirror = 1; + fakeobj.compobj_x = -fakeobj.compobj_x; + } + fakeobj.compobj_x += hostpin->x; + fakeobj.compobj_y += hostpin->y; + print_graph_compinst(&fakeobj); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/defaultprefs.ps Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,6 @@ +1.4 settextfudge +/defaultlinewidth 1000 72 div def +/pinthickness 10 def +/netlinewidth 10 def +/buslinewidth 30 def +/conndotradius 30 def
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/gschemcode.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,484 @@ +/* + * We print gschem code in two places: symbols and graphblocks. + */ + +#include <sys/types.h> +#include <ctype.h> +#include <stdio.h> +#include <strings.h> +#include "../libuschem/graphsym.h" +#include "../libuschem/schemstruct.h" + +static char leftstr[] = "/left"; +static char rightstr[] = "/right"; +static char topstr[] = "/top"; +static char bottomstr[] = "/bottom"; +static char ctrstr[] = "/ctr"; + +char *gschem_text_halign[9] = {leftstr, leftstr, leftstr, + ctrstr, ctrstr, ctrstr, + rightstr, rightstr, rightstr}; +char *gschem_text_valign[9] = {bottomstr,ctrstr, topstr, + bottomstr,ctrstr, topstr, + bottomstr,ctrstr, topstr}; + +#define MAXLINE 256 + +static FILE *inf; +static char *pathname; +static int lineno; +static int issym, in_pinblock; +static int linewidth, dashed; +static int font_ptsize; +static int varpin_count; + +print_gschem_code_sym(file, sym) + FILE *file; + struct graphsym *sym; +{ + inf = file; + pathname = sym->gs_pathname; + lineno = 0; + issym = 1; + mymain(); +} + +print_gschem_code_graphblk(file, blk, orig_filename) + FILE *file; + struct graphblock *blk; + char *orig_filename; +{ + inf = file; + pathname = orig_filename; + lineno = blk->lineno; + issym = 0; + fseek(inf, blk->offset, 0); + mymain(); +} + +static +mymain() +{ + char line[MAXLINE]; + register char *cp; + register int c; + + in_pinblock = 0; + linewidth = -1; + dashed = 0; + font_ptsize = 0; + varpin_count = 0; + while (getline(line)) { + switch (line[0]) { + case '%': /* PS-like comments */ + case '\0': /* allow blank lines too */ + continue; + case '{': + in_pinblock++; + continue; + case '}': + if (!in_pinblock) + return; + in_pinblock--; + continue; + } + if (!isalpha(line[0])) { +inv: fprintf(stderr, "%s: line %d: invalid gschem code\n", + pathname, lineno); + exit(1); + } + for (cp = line; isalpha(*cp); cp++) + ; + if (!isspace(*cp)) + goto inv; + *cp++ = '\0'; + while (isspace(*cp)) + cp++; + if (!strcmp(line, "PS")) { + if (strcmp(cp, "{")) + goto inv; + do_ps_block(); + /* be safe about the graphics state */ + linewidth = -1; + font_ptsize = 0; + continue; + } else if (strlen(line) != 1) + continue; /* ignore these */ + line[1] = ' '; + /* dispatch by single-char type */ + switch (line[0]) { + case 'v': + continue; /* ignore */ + /* simple graphics */ + case 'L': + do_line(line); + continue; + case 'B': + do_box(line); + continue; + case 'V': + do_circle(line); + continue; + case 'A': + do_arc(line); + continue; + case 'P': + handle_pin(line); + continue; + case 'T': + handle_T_obj(line, lineno); + continue; + default: + goto inv; + } + } +} + +static +do_line(objline) + char *objline; +{ + int numparams[10]; + + parse_numline(objline, lineno, numparams, 10); + if (setdash(numparams[7], numparams[8], numparams[9]) < 0) + return; + setlinewidth(numparams[5]); + emit_coordpair(numparams[0], numparams[1]); + fputs("moveto ", stdout); + emit_coordpair(numparams[2], numparams[3]); + puts("lineto stroke"); +} + +static +do_box(objline) + char *objline; +{ + int numparams[16]; + + parse_numline(objline, lineno, numparams, 16); + switch (numparams[10]) { + case 0: + if (setdash(numparams[7], numparams[8], numparams[9]) < 0) + return; + setlinewidth(numparams[5]); + emit_coordpair(numparams[0], numparams[1]); + emit_coordpair(numparams[2], numparams[3]); + puts("rectstroke"); + return; + case 1: + emit_coordpair(numparams[0], numparams[1]); + emit_coordpair(numparams[2], numparams[3]); + puts("rectfill"); + return; + default: + fprintf(stderr, + "%s: line %d: fill type %d not implemented; object omitted\n", + pathname, lineno, numparams[10]); + } +} + +static +do_circle(objline) + char *objline; +{ + int numparams[15]; + + parse_numline(objline, lineno, numparams, 15); + switch (numparams[9]) { + case 0: + if (setdash(numparams[6], numparams[7], numparams[8]) < 0) + return; + setlinewidth(numparams[4]); + emit_coordpair(numparams[0], numparams[1]); + printf("%d circlestroke\n", numparams[2]); + return; + case 1: + emit_coordpair(numparams[0], numparams[1]); + printf("%d circlefill\n", numparams[2]); + return; + default: + fprintf(stderr, + "%s: line %d: fill type %d not implemented; object omitted\n", + pathname, lineno, numparams[9]); + } +} + +static +do_arc(objline) + char *objline; +{ + int numparams[11]; + + parse_numline(objline, lineno, numparams, 11); + if (!numparams[4]) /* degenerate? */ + return; /* ignore those */ + if (setdash(numparams[8], numparams[9], numparams[10]) < 0) + return; + setlinewidth(numparams[6]); + puts("newpath"); + emit_coordpair(numparams[0], numparams[1]); + printf("%d %d %d%s%s arc stroke\n", numparams[2], numparams[3], + numparams[3] + numparams[4], numparams[4] > 0 ? "" : " exch", + issym ? " mirrorarc" : ""); +} + +static +setlinewidth(newval) +{ + if (newval != linewidth) { + linewidth = newval; + if (linewidth) + printf("%d setlinewidth\n", linewidth); + else + puts("defaultlinewidth setlinewidth"); + } + return(0); +} + +static +setdash(dashstyle, dashlength, dashspace) +{ + switch (dashstyle) { + case 0: + if (dashed) { + puts("setsolid"); + dashed = 0; + } + return(0); + case 2: + printf("[%d %d] 0 setdash\n", dashlength, dashspace); + dashed = 1; + return(0); + default: + fprintf(stderr, + "%s: line %d: dash style %d not implemented; object omitted\n", + pathname, lineno, dashstyle); + return(-1); + } +} + +static +emit_coordpair(x, y) +{ + printf("%d%s %d ", x, issym ? " mirror" : "", y); +} + +static +handle_pin(objline) + char *objline; +{ + int numparams[7]; + + parse_numline(objline, lineno, numparams, 7); + printf("%d mirror %d %d mirror %d drawpin\n", numparams[0], + numparams[1], numparams[2], numparams[3]); +} + +static +handle_T_obj(objline, objlineno) + char *objline; +{ + int numparams[9]; + char textline[MAXLINE]; + register int i; + register char *cp; + int readystr, isvarpin; + + parse_numline(objline, objlineno, numparams, 9); + if (numparams[8] < 1) { + fprintf(stderr, "%s: line %d: T object: num_lines<1!\n", + pathname, objlineno); + exit(1); + } + if (numparams[8] > 1) + fprintf(stderr, + "warning: multiline T objects not implemented (found in %s)\n", + pathname); + for (i = numparams[8]; i; i--) { + if (!getline(textline)) { + fprintf(stderr, "%s: EOF in T object\n", pathname); + exit(1); + } + if (!numparams[4]) /* visible? */ + continue; /* nope */ + isvarpin = 0; + if (issym) { + readystr = 0; + cp = index(textline, '='); + if (cp) { + cp++; + if (!in_pinblock) /* we don't print */ + continue; /* top level attrs */ + if (!strcmp(cp, "%d")) + isvarpin = 1; + } else + cp = textline; + } else { + cp = textline; + readystr = (cp[0] == '('); + } + if (numparams[7] < 0 || numparams[7] > 8) { + fprintf(stderr, + "%s: line %d: T object: alignment %d is invalid\n", + pathname, objlineno, numparams[7]); + continue; + } + if (font_ptsize != numparams[3]) { + font_ptsize = numparams[3]; + printf("/Helvetica %d selisofnt\n", font_ptsize); + } + if (isvarpin) + printf("pins %d get", varpin_count++); + else if (readystr) + fputs(cp, stdout); + else + emit_ps_string(cp); + printf(" %s%s %s %d ", gschem_text_halign[numparams[7]], + issym ? " mirrortext" : "", + gschem_text_valign[numparams[7]], numparams[6]); + emit_coordpair(numparams[0], numparams[1]); + puts("Tshow"); + } +} + +static +parse_numline(line, lineno, numarray, nfields) + char *line; + int lineno; + int *numarray; + int nfields; +{ + register char *cp, *np; + register int i; + + for (i = 0, cp = line+1; i < nfields; i++) { + if (!isspace(*cp)) { +inv: fprintf(stderr, "%s: line %d: invalid numeric line\n", + pathname, lineno); + exit(1); + } + while (isspace(*cp)) + cp++; + np = cp; + if (*cp == '-') + cp++; + if (!isdigit(*cp)) + goto inv; + while (isdigit(*cp)) + cp++; + numarray[i] = atoi(np); + } + if (*cp) + goto inv; +} + +static +getline(linebuf) + char *linebuf; +{ + register char *cp; + + if (fgets(linebuf, MAXLINE, inf) == NULL) + return(0); + lineno++; + /* strip trailing newline or other whitespace */ + cp = index(linebuf, '\0'); + while (cp > linebuf && isspace(cp[-1])) + cp--; + *cp = '\0'; + return(1); +} + +static +do_ps_block() +{ + register int c, n; + + for (n = 0; ; ) { + c = getc(inf); + switch (c) { + case EOF: +badeof: fprintf(stderr, "%s: EOF in a PS block\n", pathname); + exit(1); + case '%': + for (;;) { + c = getc(inf); + if (c == EOF) + goto badeof; + if (c == '\n') + break; + } + /* FALL THRU */ + case '\n': + putchar(c); + lineno++; + continue; + case '(': + putchar(c); + skip_over_ps_string(); + continue; + case ')': + fprintf(stderr, + "%s: line %d: unmatched \')\' in a PS block", + pathname, lineno); + exit(1); + case '{': + putchar(c); + n++; + continue; + case '}': + if (!n) + goto out; + putchar(c); + n--; + continue; + default: + putchar(c); + continue; + } + } +out: c = getc(inf); + if (c != '\n') { + fprintf(stderr, +"%s: line %d: '}' closing PS block must be directly followed by newline\n", + pathname, lineno); + exit(1); + } + lineno++; + putchar(c); +} + +static +skip_over_ps_string() +{ + register int c, n; + + for (n = 1; n > 0; ) { + c = getc(inf); + if (c == EOF) { +badeof: fprintf(stderr, "%s: EOF in a PS block\n", pathname); + exit(1); + } + putchar(c); + switch (c) { + case '\n': + lineno++; + continue; + case '(': + n++; + continue; + case ')': + n--; + continue; + case '\\': + c = getc(inf); + if (c == EOF) + goto badeof; + putchar(c); + if (c == '\n') + lineno++; + continue; + } + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/main.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,126 @@ +#include <sys/types.h> +#include <stdio.h> +#include "../libuschem/schemstruct.h" + +extern char *malloc(); + +extern int optind; +extern char *optarg; + +extern char *MCLfile; + +extern struct schem *read_schem(); + +extern char default_prefs_pathname[]; + +struct schem **schem_pages; +int npages; +char *prefs_file = default_prefs_pathname; +int printsize_x = 1224, printsize_y = 792, printmargin; + +main(argc, argv) + char **argv; +{ + register int c; + register struct schem *schem; + + while ((c = getopt(argc, argv, "I:m:M:p:P:")) != EOF) + switch (c) { + case 'I': + add_symfile_dir(optarg); + break; + case 'm': + printmargin = atoi(optarg); + break; + case 'M': + MCLfile = optarg; + break; + case 'p': + prefs_file = optarg; + break; + case 'P': + set_paper_size(optarg); + break; + default: +usage: fprintf(stderr, "usage: %s [-options] schemfile...\n", + argv[0]); + exit(1); + } + if (!argv[optind]) + goto usage; + npages = argc - optind; + + read_MCL(); + hash_MCL(); + set_default_sympath(); + read_pinouts(); + + schem_pages = (struct schem **) malloc(sizeof(struct schem *) * npages); + if (!schem_pages) { + perror("malloc"); + exit(1); + } + for (c = 0; c < npages; c++) { + schem = read_schem(argv[optind+c]); + if (!schem->is_graph) { + fprintf(stderr, + "%s: non-graphical schematic cannot be printed\n", + schem->orig_filename); + exit(1); + } + schem_pages[c] = schem; + match_schem_to_mcl(schem); + load_graphsyms(schem); + instantiate_graphsym_pins(schem, 0); /* for SymOnPin */ + } + + emit_header(); + emit_prolog(); + emit_setup(); + for (c = 0; c < npages; c++) + print_schem_page(c); + puts("%%Trailer"); + puts("%%EOF"); + + exit(0); +} + +emit_header() +{ + puts("%!PS-Adobe-3.0"); + puts("%%Creator: uschem-print"); + puts("%%LanguageLevel: 2"); + puts("%%Orientation: Landscape"); + printf("%%%%Pages: %d\n", npages); + puts("%%EndComments"); +} + +emit_setup() +{ + puts("%%BeginSetup"); + printf("/printsize_x %d def\n", printsize_x); + printf("/printsize_y %d def\n", printsize_y); + puts("<< /PageSize [printsize_x printsize_y] >> setpagedevice"); + printf("/printmargin %d def\n", printmargin); + puts("$uschem begin"); + emit_file(prefs_file); + puts("end"); + puts("%%EndSetup"); +} + +emit_file(pathname) + char *pathname; +{ + register FILE *f; + char buf[512]; + register int cc; + + f = fopen(pathname, "r"); + if (!f) { + perror(pathname); + exit(1); + } + while ((cc = fread(buf, 1, sizeof buf, f)) > 0) + fwrite(buf, 1, cc, stdout); + fclose(f); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/papersize.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,57 @@ +#include <stdio.h> +#include <ctype.h> +#include <strings.h> + +extern int printsize_x, printsize_y; + +struct paper_size_kwtab { + char *keyword; + int xdim; + int ydim; +} paper_sizes[] = { + {"letter", 792, 612}, + {"legal", 1008, 612}, + {"ledger", 1224, 792}, + {"tabloid", 1224, 792}, + {"11x17", 1224, 792}, + {"A", 792, 612}, + {"B", 1224, 792}, + {"C", 1584, 1224}, + {"D", 2448, 1584}, + {"E", 3168, 2448}, + {NULL, 0, 0} +}; + +set_paper_size(str) + char *str; +{ + struct paper_size_kwtab *kwp; + register char *cp, *np; + + for (kwp = paper_sizes; kwp->keyword; kwp++) + if (!strcmp(str, kwp->keyword)) { + printsize_x = kwp->xdim; + printsize_y = kwp->ydim; + return; + } + + cp = str; + if (!isdigit(*cp)) { +inv: fprintf(stderr, + "uschem-print: -P %s: invalid paper size specification\n", + str); + exit(1); + } + for (np = cp; isdigit(*cp); cp++) + ; + if (*cp++ != 'x') + goto inv; + printsize_x = atoi(np); + if (!isdigit(*cp)) + goto inv; + for (np = cp; isdigit(*cp); cp++) + ; + if (*cp) + goto inv; + printsize_y = atoi(np); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/pathnames.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,5 @@ +char uschem_procset_pathname[] = + "/usr/local/eda/uschem-support/uschem-procset.ps"; +char transfont_procset_pathname[] = + "/usr/local/eda/uschem-support/transfont.ps"; +char default_prefs_pathname[] = "/usr/local/eda/uschem-support/defaultprefs.ps";
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/printpage.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,204 @@ +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "../libuschem/schemstruct.h" +#include "../libuschem/graphsym.h" + +extern FILE *reopen_schem_for_graphblocks(); +extern char *get_compinst_attr(); +extern char *pinname_to_pinnumber(); + +extern struct schem **schem_pages; +extern int npages; + +struct schem *schem_being_printed; +FILE *schemfile_for_graphblocks; + +static enum {LINEWIDTH_UNDEF, LINEWIDTH_NET, LINEWIDTH_BUS} pagelevel_linewidth; + +print_schem_page(pageno) + int pageno; /* zero-based */ +{ + register struct schem *schem; + register struct schemobj *obj; + + schem = schem_pages[pageno]; + schem_being_printed = schem; + schemfile_for_graphblocks = reopen_schem_for_graphblocks(schem); + printf("%%%%Page: %s %d\n", schem->orig_filename, pageno + 1); + puts("save $uschem begin"); + printf("/drawingsize_x %d def\n", schem->graph_xsize); + printf("/drawingsize_y %d def\n", schem->graph_ysize); + puts("setscale"); + pagelevel_linewidth = LINEWIDTH_UNDEF; + reset_decor_font(); + for (obj = schem->obj_next; obj != (struct schemobj *) schem; + obj = obj->obj_next) + print_schem_obj(obj); + if (schemfile_for_graphblocks) + fclose(schemfile_for_graphblocks); + puts("end restore showpage"); + return(0); +} + +print_schem_obj(obj) + register struct schemobj *obj; +{ + switch (obj->obj_type) { + case OBJTYPE_COMPINST: + if (!obj->compobj_isgraph) + return; + /* FALL THRU */ + case OBJTYPE_GRAPHSYM: + print_graph_compinst(obj); + return; + case OBJTYPE_GRAPHNET: + if (pagelevel_linewidth != LINEWIDTH_NET) { + puts("netlinewidth setlinewidth"); + pagelevel_linewidth = LINEWIDTH_NET; + } + print_graphnet(obj); + print_obj_decors(obj); + return; + case OBJTYPE_NETLINE: + if (pagelevel_linewidth != LINEWIDTH_NET) { + puts("netlinewidth setlinewidth"); + pagelevel_linewidth = LINEWIDTH_NET; + } + printf("%d %d moveto %d %d lineto stroke\n", obj->lineobj_x1, + obj->lineobj_y1, obj->lineobj_x2, obj->lineobj_y2); + print_obj_decors(obj); + return; + case OBJTYPE_BUSSEG: + if (pagelevel_linewidth != LINEWIDTH_BUS) { + puts("buslinewidth setlinewidth"); + pagelevel_linewidth = LINEWIDTH_BUS; + } + printf("%d %d moveto %d %d lineto stroke\n", obj->lineobj_x1, + obj->lineobj_y1, obj->lineobj_x2, obj->lineobj_y2); + print_obj_decors(obj); + return; + case OBJTYPE_GRAPHBLOCK: + print_graphblock(obj->graphblockobj_body); + return; + } +} + +print_graph_compinst(obj) + register struct schemobj *obj; +{ + register struct graphsym *gs; + char *slot; + + gs = obj->compobj_graphsym; + printf("save %d %d translate", obj->compobj_x, obj->compobj_y); + if (obj->compobj_rotate) + printf(" %d rotate", obj->compobj_rotate); + putchar('\n'); + printf("/mirrored %s def\n", obj->compobj_mirror ? "true" : "false"); + if (gs->gs_varpins) { + if (obj->obj_type != OBJTYPE_COMPINST) { + fprintf(stderr, +"%s: line %d: symbol \"%s\" has variable pins; may not be used w/o component\n", + schem_being_printed->orig_filename, + obj->obj_lineno, gs->gs_name); + exit(1); + } + slot = get_compinst_attr(obj, "slot"); + define_varpins(gs, obj->compobj_mclcomp, slot); + } + printf("symbols /%s get exec restore\n", gs->gs_name); + print_obj_decors(obj); +} + +define_varpins(gs, comp, slot) + struct graphsym *gs; + struct component *comp; + char *slot; +{ + register struct graphsym_pindef *pin; + register char *cp; + + puts("/pins ["); + for (pin = gs->gs_pins; pin; pin = pin->gspd_next) + if (pin->gspd_pinnumber && !strcmp(pin->gspd_pinnumber, "%d")) { + if (pin->gspd_pinname) + cp = pinname_to_pinnumber(comp, + pin->gspd_pinname, slot); + else { + fprintf(stderr, + "Symbol %s: variable pin has no pinname attribute\n", + gs->gs_name); + cp = NULL; + } + putchar(' '); + if (cp) + emit_ps_string(cp); + else { + putchar('('); + putchar(')'); + } + putchar('\n'); + } + puts("] def"); +} + +print_graphnet(obj) + struct schemobj *obj; +{ + register struct netpoint *netpt; + register int first; + + for (netpt = obj->netobj_points, first = 1; netpt; + netpt = netpt->netpt_next) { + if (!netpt->netpt_coord_valid) { + fprintf(stderr, + "%s: line %d: GraphNet contains Pin w/o coordinates, not printed\n", + schem_being_printed->orig_filename, + obj->obj_lineno); + puts("newpath"); /* kludge in lieu of abort */ + return; + } + printf("%d %d %s\n", netpt->netpt_x, netpt->netpt_y, + first ? "moveto" : "lineto"); + first = 0; + } + puts("stroke"); + /* connection dots */ + for (netpt = obj->netobj_points, first = 1; netpt; + netpt = netpt->netpt_next, first = 0) + switch (netpt->netpt_type) { + case NETPT_TYPE_PIN: + case NETPT_TYPE_PSEUDO: + if (first || !netpt->netpt_next) + continue; + /* FALL THRU */ + case NETPT_TYPE_TJOIN: + printf("%d %d conndot\n", netpt->netpt_x, + netpt->netpt_y); + continue; + } +} + +print_graphblock(blk) + register struct graphblock *blk; +{ + puts("save"); + switch (blk->type) { + case GRAPHBLOCK_TYPE_PS: + write_graphblock_to_file(blk, schemfile_for_graphblocks, + stdout); + break; + case GRAPHBLOCK_TYPE_GSCHEM: + print_gschem_code_graphblk(schemfile_for_graphblocks, blk, + schem_being_printed->orig_filename); + break; + default: + fprintf(stderr, + "Fatal internal error: unknown graphblock type %d (from %s line %d)\n", + blk->type, schem_being_printed->orig_filename, + blk->lineno); + exit(1); + } + puts("restore"); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/prolog.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,101 @@ +/* + * The main work here is emitting the graphical symbol definitions + * and any user-requested additional procsets. + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "../libuschem/graphsym.h" +#include "../libuschem/schemstruct.h" + +extern FILE *find_symlib_file(); + +extern int total_graphsyms; + +extern struct schem **schem_pages; +extern int npages; + +extern char uschem_procset_pathname[]; +extern char transfont_procset_pathname[]; + +print_graphsym_def(sym) + struct graphsym *sym; +{ + FILE *f; + + printf("/%s {\n", sym->gs_name); + f = fopen(sym->gs_pathname, "r"); + if (!f) { + fprintf(stderr, "Unable to reopen %s for printing: ", + sym->gs_pathname); + perror(NULL); + exit(1); + } + print_gschem_code_sym(f, sym); + fclose(f); + puts("} bind def"); +} + +emit_prolog() +{ + register int i; + + puts("%%BeginProlog"); + emit_file(uschem_procset_pathname); + emit_file(transfont_procset_pathname); + for (i = 0; i < npages; i++) + emit_extra_procsets(schem_pages[i]); + printf("%d dict begin\n", total_graphsyms); + graphsym_forall(print_graphsym_def); + puts("currentdict end"); + puts("$uschem exch /symbols exch put"); + puts("%%EndProlog"); +} + +#define MAX_EXTRA_PROCSETS 128 + +emit_extra_procsets(schem) + struct schem *schem; +{ + static char *procset_list[MAX_EXTRA_PROCSETS]; + static int nprocsets; + register struct schemobj *obj; + register char *psname; + register int i; + register FILE *f; + char buf[512]; + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) { + if (obj->obj_type != OBJTYPE_COMMENT) + continue; + if (strncmp(obj->commentobj_text, "Need procset: ", 14)) + continue; + psname = obj->commentobj_text + 14; + if (!psname[0]) + continue; + /* have we already seen it? */ + for (i = 0; i < nprocsets; i++) + if (!strcmp(procset_list[i], psname)) + break; + if (i < nprocsets) + continue; + if (nprocsets >= MAX_EXTRA_PROCSETS) { + fprintf(stderr, "%s: line %d: too many procsets\n", + schem->orig_filename, obj->obj_lineno); + exit(1); + } + /* get it and put it out */ + f = find_symlib_file(psname, NULL); + if (!f) { + fprintf(stderr, "procset %s not found (%s line %d)\n", + psname, schem->orig_filename, obj->obj_lineno); + exit(1); + } + while ((i = fread(buf, 1, sizeof buf, f)) > 0) + fwrite(buf, 1, i, stdout); + fclose(f); + procset_list[nprocsets++] = psname; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/pstring.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,24 @@ +/* + * Emitting PostScript strings, handling all special characters + */ + +#include <ctype.h> + +emit_ps_string(str) + char *str; +{ + register char *cp; + register int c; + + putchar('('); + for (cp = str; c = *cp; cp++) { + if (!isprint(c)) { + printf("\\%03o", c); + continue; + } + if (c == '(' || c == ')' || c == '\\') + putchar('\\'); + putchar(c); + } + putchar(')'); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/transfont.ps Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,23 @@ +%!PS-Adobe-3.0 Resource-ProcSet +%%LanguageLevel: 2 +%%BeginResource: procset (Procedure for recoding fonts to ISOLatin1Encoding on the fly) 1.0 0 +currentglobal true setglobal +/transfontdict 20 dict def +/transfont { + dup //transfontdict exch known { + //transfontdict exch get + } { + currentglobal exch true setglobal + dup + findfont dup length dict begin + {1 index /FID ne {def} {pop pop} ifelse} forall + /Encoding //ISOLatin1Encoding def + currentdict end + /transfont-dummy-fontname exch definefont + //transfontdict 2 index 2 index put + exch pop + exch setglobal + } ifelse +} bind def +setglobal +%%EndResource
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-print/uschem-procset.ps Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,106 @@ +%!PS-Adobe-3.0 Resource-ProcSet +%%LanguageLevel: 2 +%%BeginResource: procset (uschem-print procedures) 1.0 0 +40 dict begin +/setscale { + /xscale printsize_x printmargin 2 mul sub drawingsize_x div def + /yscale printsize_y printmargin 2 mul sub drawingsize_y div def + xscale yscale ge { + printsize_x drawingsize_x yscale mul sub 2 div + printmargin translate + yscale dup scale + } { + printsize_y drawingsize_y xscale mul sub 2 div + printmargin exch translate + xscale dup scale + } ifelse +} bind def +% text stuff +/ptsize { + textscalefactor mul +} bind def +/settextfudge { + 1000 72 div mul + /textscalefactor exch def +} bind def +/selfnt { + ptsize selectfont +} bind def +/selisofnt { + exch transfont exch ptsize scalefont setfont +} bind def +3 dict begin + /left 0 def + /ctr { + 1 index stringwidth pop + 2 div neg + } bind def + /right { + 1 index stringwidth pop neg + } bind def +currentdict end +/Tshow_halign exch def +3 dict begin + /bottom 0 def + /ctr { + 0 0 moveto + 1 index true charpath flattenpath pathbbox newpath + 4 1 roll pop pop pop + 2 div neg + } bind def + /top { + 0 0 moveto + 1 index true charpath flattenpath pathbbox newpath + 4 1 roll pop pop pop + neg + } bind def +currentdict end +/Tshow_valign exch def +/Tshow { % string halign valign rot x y + gsave translate rotate + exch //Tshow_halign exch get exec + exch //Tshow_valign exch get exec + moveto show + grestore +} bind def +% simple graphic utilities +/circlefill { + newpath 0 360 arc closepath fill +} bind def +/circlestroke { + newpath 0 360 arc closepath stroke +} bind def +/setsolid { + {} 0 setdash +} bind def +% for symbols +/mirror { + mirrored {neg} if +} bind def +/mirrortext_table << + /left /right + /ctr /ctr + /right /left +>> def +/mirrortext { + mirrored {//mirrortext_table exch get} if +} bind def +/mirrorangle { + dup sin exch cos neg atan +} bind def +/mirrorarc { + mirrored {mirrorangle exch mirrorangle} if +} bind def +/drawpin { + gsave newpath + moveto lineto + pinthickness setlinewidth 0 setlinecap setsolid + stroke grestore +} bind def +% schematic stuff +/conndot { + conndotradius circlefill +} bind def +currentdict end +/$uschem exch def +%%EndResource
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-utils/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,2 @@ +check +rewrite
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-utils/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,21 @@ +CFLAGS= -O +PROGS= check rewrite +LIBS= ../libuschem/libuschem.a ../libueda/libueda.a +BINDIR= /usr/local + +all: ${PROGS} + +check: check.o checknets.o + ${CC} -o $@ $@.o checknets.o ${LIBS} + +rewrite: rewrite.o + ${CC} -o $@ $@.o ${LIBS} + +${PROGS}: ${LIBS} + +install: + install -c -o bin -g bin -m 755 check ${BINDIR}/uschem-check + install -c -o bin -g bin -m 755 rewrite ${BINDIR}/uschem-rewrite + +clean: + rm -f *.[ao] a.out core errs ${PROGS}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-utils/check.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,298 @@ +/* + * This program (uschem-check) reads a uschem schematic into core, exercising + * libuschem reading code. + * It then performs the most basic DRC, or more specifically, the check is + * focused on matching the graphical info with the netlist info - no attempt + * is made to guess the sensibility of the actual electrical circuit. + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "../libuschem/schemstruct.h" +#include "../libuschem/graphsym.h" + +extern int optind; +extern char *optarg; + +extern char *MCLfile; + +extern struct schem *read_schem(); + +struct schem *schem; +int domcl, dosymbols, checkhash, donets; + +main(argc, argv) + char **argv; +{ + register int c; + char **avp; + + while ((c = getopt(argc, argv, "hI:mM:s")) != EOF) + switch (c) { + case 'h': + checkhash++; + break; + case 'I': + add_symfile_dir(optarg); + break; + case 'm': + domcl++; + break; + case 'M': + MCLfile = optarg; + break; + case 's': + dosymbols++; + break; + default: +usage: fprintf(stderr, "usage: %s [-hImMs] schemfile...\n", + argv[0]); + exit(1); + } + if (!argv[optind]) + goto usage; + + if (domcl) { + read_MCL(); + hash_MCL(); + if (checkhash) + report_mclhash_quality(); + } + if (dosymbols) + set_default_sympath(); + + for (avp = argv + optind; *avp; avp++) { + schem = read_schem(*avp); + hash_component_instances(schem); + if (checkhash) + report_compinst_hash_quality(schem); + if (domcl) + match_schem_to_mcl(schem); + if (dosymbols) { + load_graphsyms(schem); + instantiate_graphsym_pins(schem, 1); + if (checkhash) + report_pininst_hash_quality(schem); + } + donets = 1; + check_schem_objects(); + if (preen_graphnets(schem, 1, dosymbols, 1, 0) < 0) + donets = 0; + if (donets && (!schem->is_graph || dosymbols)) + check_exclusive_nets(); + } + + report_exclusive_net_violations(); + if (checkhash && dosymbols) + report_graphsym_hash_quality(); + exit(0); +} + +check_schem_objects() +{ + register struct schemobj *obj; + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) { + switch (obj->obj_type) { + case OBJTYPE_COMPINST: + if (obj->compobj_isgraph && !schem->is_graph) + fprintf(stderr, + "%s: line %d: graphical symbol used in a non-graphical schematic\n", + schem->orig_filename, obj->obj_lineno); + if (obj->compobj_isgraph && dosymbols && + obj->compobj_graphsym->gs_forcenets) + fprintf(stderr, +"%s: line %d: symbol \"%s\" on %s: forcenets won't have the desired effect\n", + schem->orig_filename, obj->obj_lineno, + obj->compobj_graph_symname, + obj->compobj_instname); + break; + case OBJTYPE_GRAPHSYM: + if (!schem->is_graph) + fprintf(stderr, + "%s: line %d: GraphSym object in a non-graphical schematic\n", + schem->orig_filename, obj->obj_lineno); + break; + case OBJTYPE_GRAPHNET: + if (!schem->is_graph) { + fprintf(stderr, + "%s: line %d: GraphNet object in a non-graphical schematic\n", + schem->orig_filename, obj->obj_lineno); + donets = 0; + } + break; + case OBJTYPE_NETLINE: + if (!schem->is_graph) + fprintf(stderr, + "%s: line %d: NetLine object in a non-graphical schematic\n", + schem->orig_filename, obj->obj_lineno); + break; + case OBJTYPE_BUSSEG: + if (!schem->is_graph) + fprintf(stderr, + "%s: line %d: BusSeg object in a non-graphical schematic\n", + schem->orig_filename, obj->obj_lineno); + break; + case OBJTYPE_GRAPHBLOCK: + if (!schem->is_graph) + fprintf(stderr, + "%s: line %d: graphics block in a non-graphical schematic\n", + schem->orig_filename, obj->obj_lineno); + break; + } + check_obj_decors(obj); + } +} + +check_obj_decors(obj) + register struct schemobj *obj; +{ + register struct decoration *decor; + + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) + switch (decor->decor_type) { + case DECOR_TYPE_DISPLAYATTR: + if (!is_graphical_obj(obj)) + fprintf(stderr, + "%s: line %d: DisplayAttr on a non-graphical object\n", + schem->orig_filename, decor->decor_lineno); + continue; + case DECOR_TYPE_DISPLAYNETNAME: + if (obj->obj_type != OBJTYPE_GRAPHNET) + fprintf(stderr, + "%s: line %d: DisplayNetName invalid in objects other than GraphNet\n", + schem->orig_filename, decor->decor_lineno); + continue; + case DECOR_TYPE_GRAPHBLOCK: + if (!is_graphical_obj(obj)) + fprintf(stderr, + "%s: line %d: graphics block decoration on a non-graphical object\n", + schem->orig_filename, decor->decor_lineno); + break; + case DECOR_TYPE_PINTONET: + if (obj->obj_type != OBJTYPE_COMPINST) { + fprintf(stderr, + "%s: line %d: PinToNet invalid in objects other than components\n", + schem->orig_filename, decor->decor_lineno); + continue; + } + record_netname_reference(decor->decorpincon_netname, 0, + schem->orig_filename, + decor->decor_lineno); + if (obj->compobj_isgraph && dosymbols) + check_pintonet_graph(obj, decor); + continue; + case DECOR_TYPE_SYMONPIN: + if (obj->obj_type != OBJTYPE_COMPINST) { + fprintf(stderr, + "%s: line %d: SymOnPin invalid in objects other than components\n", + schem->orig_filename, decor->decor_lineno); + continue; + } + if (!obj->compobj_isgraph) { + fprintf(stderr, + "%s: line %d: SymOnPin invalid on a non-graphical component\n", + schem->orig_filename, decor->decor_lineno); + continue; + } + if (dosymbols) + check_symonpin(obj, decor); + } +} + +is_graphical_obj(obj) + register struct schemobj *obj; +{ + switch (obj->obj_type) { + case OBJTYPE_COMPINST: + return(obj->compobj_isgraph); + case OBJTYPE_GRAPHSYM: + case OBJTYPE_GRAPHNET: + case OBJTYPE_NETLINE: + case OBJTYPE_BUSSEG: + case OBJTYPE_GRAPHBLOCK: + return(1); + default: + return(0); + } +} + +check_pintonet_graph(obj, condec) + struct schemobj *obj; + register struct decoration *condec; +{ + register struct decoration *symdec; + + /* is this pin represented graphically? */ + if (!is_pin_graphical(obj->compobj_graphsym, condec->decorpincon_pin)) + return; + /* it is graphical -- look for matching SymOnPin */ + for (symdec = obj->obj_decorations; symdec; symdec = symdec->decor_next) + if (symdec->decor_type == DECOR_TYPE_SYMONPIN && + !strcmp(condec->decorpincon_pin, symdec->decorpinsym_pin)) + break; + if (!symdec) + fprintf(stderr, "%s: line %d: pin %s of %s is connected with PinToNet, but not marked with SymOnPin\n", + schem->orig_filename, condec->decor_lineno, + condec->decorpincon_pin, obj->compobj_instname); +} + +is_pin_graphical(gs, matchkey) + struct graphsym *gs; + register char *matchkey; +{ + int bynum; + register struct graphsym_pindef *pd; + register char *pinid; + + if (matchkey[0] == '#') { + bynum = 1; + matchkey++; + } else + bynum = 0; + for (pd = gs->gs_pins; pd; pd = pd->gspd_next) { + pinid = bynum ? pd->gspd_pinnumber : pd->gspd_pinname; + if (pinid && !strcmp(pinid, matchkey)) + return(1); + } + return(0); +} + +check_symonpin(obj, symdec) + struct schemobj *obj; + struct decoration *symdec; +{ + struct graphsym *gs; + struct graphsym_pindef *pindef; + register struct decoration *ndec; + + gs = symdec->decorpinsym_gs; + if (gs->gs_npins > 1) { + fprintf(stderr, + "%s: line %d: SymOnPin symbols may not have more than 1 pin\n", + schem->orig_filename, symdec->decor_lineno); + return; + } + pindef = gs->gs_pins; + if (!pindef->gspd_forcenet) + return; + /* look for matching PinToNet */ + for (ndec = obj->obj_decorations; ndec; ndec = ndec->decor_next) + if (ndec->decor_type == DECOR_TYPE_PINTONET && + !strcmp(ndec->decorpincon_pin, symdec->decorpinsym_pin)) + break; + if (!ndec) { + fprintf(stderr, +"%s: line %d: SymOnPin implies connection to %s, but no matching PinToNet\n", + schem->orig_filename, symdec->decor_lineno, + pindef->gspd_forcenet); + return; + } + if (strcmp(ndec->decorpincon_netname, pindef->gspd_forcenet)) + fprintf(stderr, +"%s: SymOnPin (line %d) and PinToNet (line %d) call for different nets!\n", + schem->orig_filename, symdec->decor_lineno, + ndec->decor_lineno); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-utils/checknets.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,190 @@ +/* + * Pseudo-netlist functionality for uschem-check + */ + +#include <sys/types.h> +#include <stdio.h> +#include <strings.h> +#include "../libuschem/schemstruct.h" + +extern char *malloc(); + +extern struct schem *schem; + +struct netname { + char *name; + int refcnt; + struct netexcl *excl; + struct netname *next; +}; + +struct netexcl { + char *filename; + int lineno; + struct netexcl *next; +}; + +#define HASH_SIZE 1103 + +static struct netname *hashtab[HASH_SIZE]; + +static int +hash_netname(str) + char *str; +{ + register u_long accum = 0; + register char *cp; + register int c, i; + + for (cp = str, i = 1; c = *cp; cp++, i++) + accum += c * i; + return(accum % HASH_SIZE); +} + +static struct netname * +get_netname_struct(name) + register char *name; +{ + register struct netname *n, **np; + + for (np = hashtab + hash_netname(name); n = *np; np = &n->next) + if (!strcmp(n->name, name)) + return(n); + n = (struct netname *) malloc(sizeof(struct netname)); + if (!n) { + perror("malloc"); + exit(1); + } + bzero(n, sizeof(struct netname)); + n->name = name; + *np = n; + return(n); +} + +record_netname_reference(netname, excl, filename, lineno) + char *netname, *filename; +{ + register struct netname *n; + register struct netexcl *e; + + n = get_netname_struct(netname); + n->refcnt++; + if (!excl) + return; + e = (struct netexcl *) malloc(sizeof(struct netexcl)); + if (!e) { + perror("malloc"); + exit(1); + } + e->filename = filename; + e->lineno = lineno; + e->next = n->excl; + n->excl = e; +} + +static +get_exclusive_attr(obj, flagp) + struct schemobj *obj; + int *flagp; +{ + register struct decoration *decor; + register char *val; + + for (decor = obj->obj_decorations; decor; decor = decor->decor_next) + if (decor->decor_type == DECOR_TYPE_ATTR && + !strcmp(decor->decorattr_name, "exclusive")) + break; + if (!decor) + return(0); + val = decor->decorattr_value; + if (!strcmp(val, "yes") || !strcmp(val, "true") || !strcmp(val, "1")) { + *flagp = 1; + return(1); + } + if (!strcmp(val, "no") || !strcmp(val, "false") || !strcmp(val, "0")) { + *flagp = 0; + return(1); + } + return(0); +} + +static +visual_netname_cues(grouphead) + struct schemobj *grouphead; +{ + register struct schemobj *obj; + register struct decoration *decor; + + for (obj = grouphead; ; obj = obj->obj_next) { + if (obj->obj_type != OBJTYPE_GRAPHNET) + break; + if (obj->netobj_grouphead != grouphead) + break; + if (obj->netobj_forcenets) + return(1); + for (decor = obj->obj_decorations; decor; + decor = decor->decor_next) + if (decor->decor_type == DECOR_TYPE_DISPLAYNETNAME) + return(1); + } + return(0); +} + +check_exclusive_nets() +{ + register struct schemobj *obj; + int isexcl; + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) { + switch (obj->obj_type) { + case OBJTYPE_NET: + if (!obj->netobj_netname) + continue; + if (!get_exclusive_attr(obj, &isexcl)) + isexcl = 0; + record_netname_reference(obj->netobj_netname, isexcl, + schem->orig_filename, + obj->obj_lineno); + continue; + case OBJTYPE_GRAPHNET: + if (obj->netobj_grouphead != obj) + continue; + if (!obj->netobj_netname) + continue; + if (!get_exclusive_attr(obj, &isexcl)) { + if (visual_netname_cues(obj)) + isexcl = 0; + else + isexcl = 1; + } + record_netname_reference(obj->netobj_netname, isexcl, + schem->orig_filename, + obj->obj_lineno); + continue; + } + } +} + +static +check_netname_for_excl(n) + struct netname *n; +{ + register struct netexcl *e; + + for (e = n->excl; e; e = e->next) + fprintf(stderr, + "Exclusive net %s at %s line %d has other connections\n", + n->name, e->filename, e->lineno); +} + +report_exclusive_net_violations() +{ + register struct netname *n, **hb; + register int i; + + for (hb = hashtab, i = 0; i < HASH_SIZE; hb++, i++) + for (n = *hb; n; n = n->next) + if (n->refcnt > 1) + check_netname_for_excl(n); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/uschem-utils/rewrite.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,268 @@ +/* + * This program reads a uschem schematic into core and then writes it back out. + * -g options converts NetLines to GraphNets and then preens/canonicalizes + * all GraphNets, otherwise just exercises the parser & writer code in + * libuschem. + */ + +#include <sys/types.h> +#include <sys/file.h> +#include <stdio.h> +#include <strings.h> +#include "../libuschem/schemstruct.h" +#include "../libuschem/graphsym.h" + +extern int optind; +extern char *optarg; +extern char *malloc(); + +extern struct schem *read_schem(); +extern struct netpoint *parser_alloc_netpoint(); +extern struct graphsym_pininst *find_pin_by_coord(); + +struct schem *schem; +char *outfile; +int replace_orig; +int gflag, Oflag; + +char * +mk_temp_newfilename() +{ + int len; + register char *str; + + len = strlen(schem->orig_filename) + 5; + str = malloc(len); + if (!str) { + perror("malloc"); + exit(1); + } + sprintf(str, "%s.new", schem->orig_filename); + return(str); +} + +main(argc, argv) + char **argv; +{ + register int c; + int fd; + FILE *outf; + + while ((c = getopt(argc, argv, "gI:o:O")) != EOF) + switch (c) { + case 'g': + gflag++; + break; + case 'I': + add_symfile_dir(optarg); + break; + case 'o': + outfile = optarg; + break; + case 'O': + Oflag++; + break; + default: +usage: fprintf(stderr, "usage: %s [-o newfile] schemfile\n", + argv[0]); + exit(1); + } + if (!argv[optind]) + goto usage; + + schem = read_schem(argv[optind]); + if (!outfile) { + outfile = mk_temp_newfilename(); + replace_orig = 1; + } + + if (gflag) { + if (hash_component_instances(schem) < 0) + exit(1); + set_default_sympath(); + load_graphsyms(schem); + if (instantiate_graphsym_pins(schem, 1) < 0 && !Oflag) + exit(1); + convert_netlines_to_graphnets(); + if (preen_graphnets(schem, 1, 1, 0, 1) < 0) + exit(1); + } + + c = O_WRONLY | O_CREAT; + if (replace_orig) + c |= O_EXCL; + else + c |= O_TRUNC; + fd = open(outfile, c, 0644); + if (fd < 0) { + perror(outfile); + exit(1); + } + outf = fdopen(fd, "w"); + if (!outf) { + perror("fdopen"); + exit(1); + } + write_schem(schem, outf); + fclose(outf); + if (replace_orig) + rename(outfile, schem->orig_filename); + exit(0); +} + +convert_netlines_to_graphnets() +{ + register struct schemobj *obj; + + for (obj = schem->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) + if (obj->obj_type == OBJTYPE_NETLINE) + convert_netline(obj); +} + +convert_netline(obj) + register struct schemobj *obj; +{ + register struct netpoint *end1, *end2; + + end1 = parser_alloc_netpoint(NETPT_TYPE_POINT); + end1->netpt_x = obj->lineobj_x1; + end1->netpt_y = obj->lineobj_y1; + end1->netpt_coord_valid = 1; + pinify_netpoint(end1); + end2 = parser_alloc_netpoint(NETPT_TYPE_POINT); + end2->netpt_x = obj->lineobj_x2; + end2->netpt_y = obj->lineobj_y2; + end2->netpt_coord_valid = 1; + pinify_netpoint(end2); + end1->netpt_next = end2; + obj->obj_type = OBJTYPE_GRAPHNET; + obj->netobj_points = end1; + obj->netobj_netname = NULL; + if (!extend_new_graphnet(obj)) { + end1->netpt_next = NULL; + end2->netpt_next = end1; + obj->netobj_points = end2; + extend_new_graphnet(obj); + } + convert_netline_decors(obj); +} + +pinify_netpoint(netpt) + register struct netpoint *netpt; +{ + register struct graphsym_pininst *pin; + + pin = find_pin_by_coord(schem, netpt->netpt_x, netpt->netpt_y); + if (!pin) + return; + switch (pin->compinst->obj_type) { + case OBJTYPE_COMPINST: + netpt->netpt_type = NETPT_TYPE_PIN; + return; + case OBJTYPE_GRAPHSYM: + netpt->netpt_type = NETPT_TYPE_PSEUDO; + return; + } +} + +convert_netline_decors(obj) + struct schemobj *obj; +{ + register struct decoration *decor; + struct decoration **np; + + for (np = &obj->obj_decorations; decor = *np; ) { + switch (decor->decor_type) { + case DECOR_TYPE_ATTR: + if (strcmp(decor->decorattr_name, "netname")) + break; + if (obj->netobj_netname && + strcmp(obj->netobj_netname, decor->decorattr_value)) { + fprintf(stderr, + "%s: line %d: net name conflict\n", + schem->orig_filename, + decor->decor_lineno); + exit(1); + } + obj->netobj_netname = decor->decorattr_value; + /* drop the decoration */ + *np = decor->decor_next; + continue; + case DECOR_TYPE_DISPLAYATTR: + if (!strcmp(decor->decordisp_attr, "netname")) + decor->decor_type = DECOR_TYPE_DISPLAYNETNAME; + break; + } + np = &decor->decor_next; + } +} + +struct netpoint * +convert_netline_to_netpt(gn, nlobj, whichend) + struct schemobj *gn; + register struct schemobj *nlobj; + int whichend; +{ + register struct netpoint *netpt; + + netpt = parser_alloc_netpoint(NETPT_TYPE_POINT); + switch (whichend) { + case 1: + netpt->netpt_x = nlobj->lineobj_x1; + netpt->netpt_y = nlobj->lineobj_y1; + break; + case 2: + netpt->netpt_x = nlobj->lineobj_x2; + netpt->netpt_y = nlobj->lineobj_y2; + break; + } + netpt->netpt_coord_valid = 1; + pinify_netpoint(netpt); + netconvert_append_decors(gn, nlobj); + schemobj_unlink(nlobj); + return(netpt); +} + +extend_new_graphnet(gn) + struct schemobj *gn; +{ + register struct schemobj *obj; + register struct netpoint *tail, *new; + int success = 0; + + tail = gn->netobj_points->netpt_next; +loop: for (obj = gn->obj_next; obj != (struct schemobj *)schem; + obj = obj->obj_next) { + if (obj->obj_type != OBJTYPE_NETLINE) + continue; + if (obj->lineobj_x1 == tail->netpt_x && + obj->lineobj_y1 == tail->netpt_y) { + new = convert_netline_to_netpt(gn, obj, 2); + tail->netpt_next = new; + tail = new; + success = 1; + goto loop; + } + if (obj->lineobj_x2 == tail->netpt_x && + obj->lineobj_y2 == tail->netpt_y) { + new = convert_netline_to_netpt(gn, obj, 1); + tail->netpt_next = new; + tail = new; + success = 1; + goto loop; + } + } + return(success); +} + +netconvert_append_decors(gnobj, nlobj) + struct schemobj *gnobj, *nlobj; +{ + register struct decoration *decor; + register struct decoration **np; + + for (np = &gnobj->obj_decorations; decor = *np; np = &decor->decor_next) + ; + *np = nlobj->obj_decorations; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/utils/.cvsignore Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,2 @@ +cutelements +instfileelem
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/utils/Makefile Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,19 @@ +CFLAGS= -O +PROGS= cutelements instfileelem +BINDIR= /usr/local + +all: ${PROGS} + +${PROGS}: + ${CC} ${CFLAGS} -o $@ $@.c + +install: + install -c -o bin -g bin -m 755 cutelements ${BINDIR}/ueda-cutelements + install -c -o bin -g bin -m 755 instfileelem ${BINDIR}/ueda-instfileelem + install -c -o bin -g bin -m 755 runm4.sh ${BINDIR}/ueda-runm4 + +clean: + rm -f *.[ao] a.out core errs ${PROGS} + +cutelements: cutelements.c +instfileelem: instfileelem.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/utils/cutelements.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,191 @@ +/* + * This program cuts the "elements PCB" constructed by the + * ueda-getfps | ueda-runm4 pipeline into one file per element. + * + * Alternatively, this program can also be used to extract all elements + * out of any PCB layout file. + */ + +#include <ctype.h> +#include <stdio.h> +#include <strings.h> + +char *inputname; +FILE *inf; +int lineno, in_element, parencount; +FILE *elemf; + +char * +do_element_line(cp) + register char *cp; +{ + char copybuf[1024]; + char opench, closech; + char *fields[11], *pcbname; + int nfields; + register int c; + char *err; + + if (in_element) { + fprintf(stderr, "%s: line %d: nested Element\n", inputname, + lineno); + exit(1); + } + if (parencount) { + fprintf(stderr, + "%s: line %d: Element not at the top nesting level\n", + inputname, lineno); + exit(1); + } + + while (isspace(*cp)) + cp++; + opench = *cp++; + switch (opench) { + case '(': + closech = ')'; + break; + case '[': + closech = ']'; + break; + default: + err = "no valid opening char"; +inv: fprintf(stderr, "%s: line %d: invalid Element line: %s\n", + inputname, lineno, err); + exit(1); + } + + strcpy(copybuf, cp); + cp = copybuf; + + for (nfields = 0; ; ) { + while (isspace(*cp)) + cp++; + if (!*cp) { +badeol: err = "missing closing char"; + goto inv; + } + if (*cp == closech) { + cp++; + break; + } + if (nfields >= 11) { + err = "too many fields"; + goto inv; + } + if (*cp == '\"') { + cp++; + for (fields[nfields++] = cp; c = *cp; cp++) + if (c == '\"') + break; + } else { + fields[nfields++] = cp; + while ((c = *cp) && !isspace(c) && c != closech) + cp++; + } + if (!c) + goto badeol; + *cp++ = '\0'; + if (c == closech) + break; + } + + switch (nfields) { + case 7: + pcbname = fields[1]; + break; + case 8: + case 9: + case 11: + pcbname = fields[2]; + break; + default: + err = "unrecognized format"; + goto inv; + } + open_element(pcbname); + + return(cp); +} + +open_element(name) + register char *name; +{ + elemf = fopen(name, "w"); + if (!elemf) { + fprintf(stderr, "cannot create file: %s\n", name); + exit(1); + } + in_element = 1; +} + +main(argc, argv) + char **argv; +{ + char linebuf[1024]; + register char *cp; + + if (argc > 2) { + fprintf(stderr, "usage: %s [collection_file]\n", argv[0]); + exit(1); + } + if (argc == 2) { + inputname = argv[1]; + inf = fopen(inputname, "r"); + if (!inf) { + perror(inputname); + exit(1); + } + } else { + inputname = "stdin"; + inf = stdin; + } + + for (lineno = 1; fgets(linebuf, sizeof linebuf, inf); lineno++) { + for (cp = linebuf; isspace(*cp); cp++) + ; + if (!strncmp(cp, "Element", 7) && + (cp[7] == '(' || cp[7] == '[' || isspace(cp[7]))) + cp = do_element_line(cp + 7); + if (in_element) + fputs(linebuf, elemf); + scan_parens(cp); + } + + if (parencount || in_element) { + fprintf(stderr, "%s: unclosed structure(s) at the end\n", + inputname); + exit(1); + } + exit(0); +} + +scan_parens(line) + char *line; +{ + register char *cp; + register int c; + + for (cp = line; c = *cp; cp++) { + if (c == '\'' && cp[1] && cp[2] == '\'') { + cp += 2; + continue; + } + if (c == '(' || c == '[') + parencount++; + else if (c == ')' || c == ']') { + parencount--; + if (parencount < 0) { + fprintf(stderr, + "%s: line %d: negative paren count\n", + inputname, lineno); + exit(1); + } + if ((parencount == 0) && in_element) { + fclose(elemf); + in_element = 0; + } + } else if (c == '#') + return; + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/ueda/utils/instfileelem.c Mon Jul 20 00:24:37 2015 +0000 @@ -0,0 +1,145 @@ +/* + * This program instantiates a file element, i.e., locates it by name and emits + * it on stdout with the refdes filled in. The value can also be filled in + * (optionally). + */ + +#include <sys/param.h> +#include <ctype.h> +#include <stdio.h> +#include <strings.h> + +char dirlist_pathname[] = "/usr/local/eda/file-element-dirs"; +char *fpname, *refdes, *value; +char fileelem_pathname[MAXPATHLEN]; + +main(argc, argv) + char **argv; +{ + register FILE *lf, *ef; + char linebuf[1024]; + register char *cp; + + if (argc < 3 || argc > 4) { + fprintf(stderr, "usage: %s footprint refdes [value]\n", + argv[0]); + exit(1); + } + fpname = argv[1]; + refdes = argv[2]; + value = argv[3]; + + lf = fopen(dirlist_pathname, "r"); + if (!lf) { + perror(dirlist_pathname); + exit(1); + } + for (ef = NULL; fgets(linebuf, sizeof linebuf, lf); ) { + if (linebuf[0] == '\0' || isspace(linebuf[0])) + continue; + cp = index(linebuf, '\0'); + while (isspace(cp[-1])) + cp--; + *cp = '\0'; + sprintf(fileelem_pathname, "%s/%s", linebuf, fpname); + if (ef = fopen(fileelem_pathname, "r")) + break; + sprintf(fileelem_pathname, "%s/%s.fp", linebuf, fpname); + if (ef = fopen(fileelem_pathname, "r")) + break; + } + fclose(lf); + if (!ef) { + fprintf(stderr, "No footprint named %s\n", fpname); + exit(1); + } + + while (fgets(linebuf, sizeof linebuf, ef)) { + for (cp = linebuf; isspace(*cp); cp++) + ; + if (!strncmp(cp, "Element", 7) && + (cp[7] == '(' || cp[7] == '[' || isspace(cp[7]))) + do_element_line(cp + 7); + else + fputs(linebuf, stdout); + } + fclose(ef); + exit(0); +} + +do_element_line(cp) + register char *cp; +{ + char opench, closech; + char *fields[11], refdesq[64], valueq[64]; + int nfields; + register int c; + char *err; + + while (isspace(*cp)) + cp++; + opench = *cp++; + switch (opench) { + case '(': + closech = ')'; + break; + case '[': + closech = ']'; + break; + default: + err = "no valid opening char"; +inv: fprintf(stderr, "%s: invalid Element line: %s\n", + fileelem_pathname, err); + exit(1); + } + + for (nfields = 0; ; ) { + while (isspace(*cp)) + cp++; + if (!*cp) { +badeol: err = "missing closing char"; + goto inv; + } + if (*cp == closech) { + cp++; + break; + } + if (nfields >= 11) { + err = "too many fields"; + goto inv; + } + fields[nfields++] = cp; + while ((c = *cp) && !isspace(c) && c != closech) + cp++; + if (!c) + goto badeol; + *cp++ = '\0'; + if (c == closech) + break; + } + + sprintf(refdesq, "\"%s\"", refdes); + if (value) + sprintf(valueq, "\"%s\"", value); + if (nfields == 11 || nfields == 9) { + fields[2] = refdesq; + if (value) + fields[3] = valueq; + } else if (nfields == 8) + fields[2] = refdesq; + else if (nfields == 7) + fields[1] = refdesq; + else { + err = "unrecognized format"; + goto inv; + } + + printf("Element%c", opench); + for (c = 0; c < nfields; c++) { + if (c) + putchar(' '); + fputs(fields[c], stdout); + } + putchar(closech); + fputs(cp, stdout); +}