| Sun, 09 Jun 2024 06:00:43 +0000 |
Mychaela Falconia |
top Makefile: add efr-sid
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| Sun, 09 Jun 2024 05:57:48 +0000 |
Mychaela Falconia |
efr-sid: hack created
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| Sun, 09 Jun 2024 05:28:22 +0000 |
Mychaela Falconia |
efr-sid: starting with dtx01-frame71.cod as good SID
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| Tue, 14 May 2024 08:26:00 +0000 |
Mychaela Falconia |
ae-dec-dhf: generate TCH UL input
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| Tue, 14 May 2024 08:18:17 +0000 |
Mychaela Falconia |
ae-dec-dhf: complete generation
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| Tue, 14 May 2024 08:13:01 +0000 |
Mychaela Falconia |
ae-dec-dhf: initial generation
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| Tue, 14 May 2024 05:36:38 +0000 |
Mychaela Falconia |
ul-test: generate hex include files for PCMU
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| Tue, 14 May 2024 04:39:30 +0000 |
Mychaela Falconia |
ul-test: generate TCH uplink bits
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| Tue, 14 May 2024 04:26:18 +0000 |
Mychaela Falconia |
dhf: generate binary form of FR1 DHF
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| Tue, 14 May 2024 03:46:12 +0000 |
Mychaela Falconia |
dhf: generate binary form of EFR DHF
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| Tue, 14 May 2024 03:36:31 +0000 |
Mychaela Falconia |
dhf: generate EFR hex DHF in C form
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| Mon, 13 May 2024 22:49:21 +0000 |
Mychaela Falconia |
ul-test: initial generation
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| Mon, 13 May 2024 06:26:22 +0000 |
Mychaela Falconia |
dhf: generate hex forms of EFR DHF
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| Mon, 13 May 2024 05:56:13 +0000 |
Mychaela Falconia |
pcma2efr: emit full input sequence
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| Mon, 13 May 2024 05:40:56 +0000 |
Mychaela Falconia |
pcma2efr: emit the set of computed frames
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