| Mon, 12 Aug 2024 03:06:17 +0000 |
Mychaela Falconia |
efr-sid OS#6538: generate test frames in hex form
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| Mon, 12 Aug 2024 02:49:28 +0000 |
Mychaela Falconia |
efr-sid OS#6538: more sensible 2-bit errors
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| Mon, 12 Aug 2024 02:37:21 +0000 |
Mychaela Falconia |
efr-sid OS#6538: more sensible 15-bit and 16-bit errors
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| Sun, 11 Aug 2024 22:17:37 +0000 |
Mychaela Falconia |
efr-sid: generate efr-sid-test2.gsmx for OS#6538
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| Wed, 24 Jul 2024 05:39:51 +0000 |
Mychaela Falconia |
hr-sid: add conversion of misordered SID field
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| Sun, 09 Jun 2024 08:58:44 +0000 |
Mychaela Falconia |
top Makefile: add hr-sid
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| Sun, 09 Jun 2024 08:57:28 +0000 |
Mychaela Falconia |
hr-sid: hack created
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| Sun, 09 Jun 2024 06:00:43 +0000 |
Mychaela Falconia |
top Makefile: add efr-sid
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| Sun, 09 Jun 2024 05:57:48 +0000 |
Mychaela Falconia |
efr-sid: hack created
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| Sun, 09 Jun 2024 05:28:22 +0000 |
Mychaela Falconia |
efr-sid: starting with dtx01-frame71.cod as good SID
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| Tue, 14 May 2024 08:26:00 +0000 |
Mychaela Falconia |
ae-dec-dhf: generate TCH UL input
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| Tue, 14 May 2024 08:18:17 +0000 |
Mychaela Falconia |
ae-dec-dhf: complete generation
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| Tue, 14 May 2024 08:13:01 +0000 |
Mychaela Falconia |
ae-dec-dhf: initial generation
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| Tue, 14 May 2024 05:36:38 +0000 |
Mychaela Falconia |
ul-test: generate hex include files for PCMU
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| Tue, 14 May 2024 04:39:30 +0000 |
Mychaela Falconia |
ul-test: generate TCH uplink bits
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| Tue, 14 May 2024 04:26:18 +0000 |
Mychaela Falconia |
dhf: generate binary form of FR1 DHF
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